3 * TI TSC2101 Audio CODEC and TS control registers definition
6 * Copyright 2003 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 #ifndef __ASM_HARDWARE_TSC2101_H
32 #define __ASM_HARDWARE_TSC2101_H
34 /* Page 0 Touch Screen Data Registers */
35 #define TSC2101_TS_X (0x00)
36 #define TSC2101_TS_Y (0x01)
37 #define TSC2101_TS_Z1 (0x02)
38 #define TSC2101_TS_Z2 (0x03)
39 #define TSC2101_TS_BAT (0x05)
40 #define TSC2101_TS_AUX1 (0x07)
41 #define TSC2101_TS_AUX2 (0x08)
42 #define TSC2101_TS_TEMP1 (0x09)
43 #define TSC2101_TS_TEMP2 (0x0A)
45 /* Page 1 Touch Screen Control registers */
46 #define TSC2101_TS_ADC_CTRL (0x00)
47 #define TSC2101_TS_STATUS (0x01)
48 #define TSC2101_TS_BUFFER_CTRL (0x02)
49 #define TSC2101_TS_REF_CTRL (0x03)
50 #define TSC2101_TS_RESET_CTRL (0x04)
51 #define TSC2101_TS_CONFIG_CTRL (0x05)
52 #define TSC2101_TS_TEMP_MAX_THRESHOLD (0x06)
53 #define TSC2101_TS_TEMP_MIN_THRESHOLD (0x07)
54 #define TSC2101_TS_AUX1_MAX_THRESHOLD (0x08)
55 #define TSC2101_TS_AUX1_MIN_THRESHOLD (0x09)
56 #define TSC2101_TS_AUX2_MAX_THRESHOLD (0x0A)
57 #define TSC2101_TS_AUX2_MIN_THRESHOLD (0x0B)
58 #define TSC2101_TS_MEASURE_CONFIG (0x0C)
59 #define TSC2101_TS_PROG_DELAY (0x0D)
61 /* Page 2 Audio codec Control registers */
62 #define TSC2101_AUDIO_CTRL_1 (0x00)
63 #define TSC2101_HEADSET_GAIN_CTRL (0x01)
64 #define TSC2101_DAC_GAIN_CTRL (0x02)
65 #define TSC2101_MIXER_PGA_CTRL (0x03)
66 #define TSC2101_AUDIO_CTRL_2 (0x04)
67 #define TSC2101_CODEC_POWER_CTRL (0x05)
68 #define TSC2101_AUDIO_CTRL_3 (0x06)
69 #define TSC2101_LCH_BASS_BOOST_N0 (0x07)
70 #define TSC2101_LCH_BASS_BOOST_N1 (0x08)
71 #define TSC2101_LCH_BASS_BOOST_N2 (0x09)
72 #define TSC2101_LCH_BASS_BOOST_N3 (0x0A)
73 #define TSC2101_LCH_BASS_BOOST_N4 (0x0B)
74 #define TSC2101_LCH_BASS_BOOST_N5 (0x0C)
75 #define TSC2101_LCH_BASS_BOOST_D1 (0x0D)
76 #define TSC2101_LCH_BASS_BOOST_D2 (0x0E)
77 #define TSC2101_LCH_BASS_BOOST_D4 (0x0F)
78 #define TSC2101_LCH_BASS_BOOST_D5 (0x10)
79 #define TSC2101_RCH_BASS_BOOST_N0 (0x11)
80 #define TSC2101_RCH_BASS_BOOST_N1 (0x12)
81 #define TSC2101_RCH_BASS_BOOST_N2 (0x13)
82 #define TSC2101_RCH_BASS_BOOST_N3 (0x14)
83 #define TSC2101_RCH_BASS_BOOST_N4 (0x15)
84 #define TSC2101_RCH_BASS_BOOST_N5 (0x16)
85 #define TSC2101_RCH_BASS_BOOST_D1 (0x17)
86 #define TSC2101_RCH_BASS_BOOST_D2 (0x18)
87 #define TSC2101_RCH_BASS_BOOST_D4 (0x19)
88 #define TSC2101_RCH_BASS_BOOST_D5 (0x1A)
89 #define TSC2101_PLL_PROG_1 (0x1B)
90 #define TSC2101_PLL_PROG_2 (0x1C)
91 #define TSC2101_AUDIO_CTRL_4 (0x1D)
92 #define TSC2101_HANDSET_GAIN_CTRL (0x1E)
93 #define TSC2101_BUZZER_GAIN_CTRL (0x1F)
94 #define TSC2101_AUDIO_CTRL_5 (0x20)
95 #define TSC2101_AUDIO_CTRL_6 (0x21)
96 #define TSC2101_AUDIO_CTRL_7 (0x22)
97 #define TSC2101_GPIO_CTRL (0x23)
98 #define TSC2101_AGC_CTRL (0x24)
99 #define TSC2101_POWERDOWN_STS (0x25)
100 #define TSC2101_MIC_AGC_CONTROL (0x26)
101 #define TSC2101_CELL_AGC_CONTROL (0x27)
103 /* Bit field definitions for TS Control */
104 #define TSC2101_DATA_AVAILABLE 0x4000
105 #define TSC2101_BUFFERMODE_DISABLE 0x0
106 #define TSC2101_REF_POWERUP 0x16
107 #define TSC2101_ENABLE_TOUCHDETECT 0x08
108 #define TSC2101_PRG_DELAY 0x0900
109 #define TSC2101_ADC_CONTROL 0x8874
110 #define TSC2101_ADC_POWERDOWN 0x4000
113 #define TSC2101_BIT(ARG) ((0x01)<<(ARG))
115 /* Field masks for Audio Control 1 */
116 #define AC1_ADCHPF(ARG) (((ARG) & 0x03) << 14)
117 #define AC1_WLEN(ARG) (((ARG) & 0x03) << 10)
118 #define AC1_DATFM(ARG) (((ARG) & 0x03) << 8)
119 #define AC1_DACFS(ARG) (((ARG) & 0x07) << 3)
120 #define AC1_ADCFS(ARG) (((ARG) & 0x07))
122 /* Field masks for TSC2101_HEADSET_GAIN_CTRL */
123 #define HGC_ADMUT_HED TSC2101_BIT(15)
124 #define HGC_ADPGA_HED(ARG) (((ARG) & 0x7F) << 8)
125 #define HGC_AGCTG_HED(ARG) (((ARG) & 0x07) << 5)
126 #define HGC_AGCTC_HED(ARG) (((ARG) & 0x0F) << 1)
127 #define HGC_AGCEN_HED (0x01)
129 /* Field masks for TSC2101_DAC_GAIN_CTRL */
130 #define DGC_DALMU TSC2101_BIT(15)
131 #define DGC_DALVL(ARG) (((ARG) & 0x7F) << 8)
132 #define DGC_DARMU TSC2101_BIT(7)
133 #define DGC_DARVL(ARG) (((ARG) & 0x7F))
135 /* Field masks for TSC2101_MIXER_PGA_CTRL */
136 #define MPC_ASTMU TSC2101_BIT(15)
137 #define MPC_ASTG(ARG) (((ARG) & 0x7F) << 8)
138 #define MPC_MICSEL(ARG) (((ARG) & 0x07) << 5)
139 #define MPC_MICADC TSC2101_BIT(4)
140 #define MPC_CPADC TSC2101_BIT(3)
141 #define MPC_ASTGF (0x01)
143 /* Field formats for TSC2101_AUDIO_CTRL_2 */
144 #define AC2_KCLEN TSC2101_BIT(15)
145 #define AC2_KCLAC(ARG) (((ARG) & 0x07) << 12)
146 #define AC2_APGASS TSC2101_BIT(11)
147 #define AC2_KCLFRQ(ARG) (((ARG) & 0x07) << 8)
148 #define AC2_KCLLN(ARG) (((ARG) & 0x0F) << 4)
149 #define AC2_DLGAF TSC2101_BIT(3)
150 #define AC2_DRGAF TSC2101_BIT(2)
151 #define AC2_DASTC TSC2101_BIT(1)
152 #define AC2_ADGAF (0x01)
154 /* Field masks for TSC2101_CODEC_POWER_CTRL */
155 #define CPC_MBIAS_HND TSC2101_BIT(15)
156 #define CPC_MBIAS_HED TSC2101_BIT(14)
157 #define CPC_ASTPWD TSC2101_BIT(13)
158 #define CPC_SP1PWDN TSC2101_BIT(12)
159 #define CPC_SP2PWDN TSC2101_BIT(11)
160 #define CPC_DAPWDN TSC2101_BIT(10)
161 #define CPC_ADPWDN TSC2101_BIT(9)
162 #define CPC_VGPWDN TSC2101_BIT(8)
163 #define CPC_COPWDN TSC2101_BIT(7)
164 #define CPC_LSPWDN TSC2101_BIT(6)
165 #define CPC_ADPWDF TSC2101_BIT(5)
166 #define CPC_LDAPWDF TSC2101_BIT(4)
167 #define CPC_RDAPWDF TSC2101_BIT(3)
168 #define CPC_ASTPWF TSC2101_BIT(2)
169 #define CPC_BASSBC TSC2101_BIT(1)
170 #define CPC_DEEMPF (0x01)
172 /* Field masks for TSC2101_AUDIO_CTRL_3 */
173 #define AC3_DMSVOL(ARG) (((ARG) & 0x03) << 14)
174 #define AC3_REFFS TSC2101_BIT(13)
175 #define AC3_DAXFM TSC2101_BIT(12)
176 #define AC3_SLVMS TSC2101_BIT(11)
177 #define AC3_ADCOVF TSC2101_BIT(8)
178 #define AC3_DALOVF TSC2101_BIT(7)
179 #define AC3_DAROVF TSC2101_BIT(6)
180 #define AC3_CLPST TSC2101_BIT(3)
181 #define AC3_REVID(ARG) (((ARG) & 0x07))
183 /* Field masks for TSC2101_PLL_PROG_1 */
184 #define PLL1_PLLSEL TSC2101_BIT(15)
185 #define PLL1_QVAL(ARG) (((ARG) & 0x0F) << 11)
186 #define PLL1_PVAL(ARG) (((ARG) & 0x07) << 8)
187 #define PLL1_I_VAL(ARG) (((ARG) & 0x3F) << 2)
189 /* Field masks of TSC2101_PLL_PROG_2 */
190 #define PLL2_D_VAL(ARG) (((ARG) & 0x3FFF) << 2)
192 /* Field masks for TSC2101_AUDIO_CTRL_4 */
193 #define AC4_ADSTPD TSC2101_BIT(15)
194 #define AC4_DASTPD TSC2101_BIT(14)
195 #define AC4_ASSTPD TSC2101_BIT(13)
196 #define AC4_CISTPD TSC2101_BIT(12)
197 #define AC4_BISTPD TSC2101_BIT(11)
198 #define AC4_AGCHYS(ARG) (((ARG) & 0x03) << 9)
199 #define AC4_MB_HED(ARG) (((ARG) & 0x03) << 7)
200 #define AC4_MB_HND TSC2101_BIT(6)
201 #define AC4_SCPFL TSC2101_BIT(1)
203 /* Field masks settings for TSC2101_HANDSET_GAIN_CTRL */
204 #define HNGC_ADMUT_HND TSC2101_BIT(15)
205 #define HNGC_ADPGA_HND(ARG) (((ARG) & 0x7F) << 8)
206 #define HNGC_AGCTG_HND(ARG) (((ARG) & 0x07) << 5)
207 #define HNGC_AGCTC_HND(ARG) (((ARG) & 0x0F) << 1)
208 #define HNGC_AGCEN_HND (0x01)
210 /* Field masks settings for TSC2101_BUZZER_GAIN_CTRL */
211 #define BGC_MUT_CP TSC2101_BIT(15)
212 #define BGC_CPGA(ARG) (((ARG) & 0x7F) << 8)
213 #define BGC_CPGF TSC2101_BIT(7)
214 #define BGC_MUT_BU TSC2101_BIT(6)
215 #define BGC_BPGA(ARG) (((ARG) & 0x0F) << 2)
216 #define BGC_BUGF TSC2101_BIT(1)
218 /* Field masks settings for TSC2101_AUDIO_CTRL_5 */
219 #define AC5_DIFFIN TSC2101_BIT(15)
220 #define AC5_DAC2SPK1(ARG) (((ARG) & 0x03) << 13)
221 #define AC5_AST2SPK1 TSC2101_BIT(12)
222 #define AC5_BUZ2SPK1 TSC2101_BIT(11)
223 #define AC5_KCL2SPK1 TSC2101_BIT(10)
224 #define AC5_CPI2SPK1 TSC2101_BIT(9)
225 #define AC5_DAC2SPK2(ARG) (((ARG) & 0x03) << 7)
226 #define AC5_AST2SPK2 TSC2101_BIT(6)
227 #define AC5_BUZ2SPK2 TSC2101_BIT(5)
228 #define AC5_KCL2SPK2 TSC2101_BIT(4)
229 #define AC5_CPI2SPK2 TSC2101_BIT(3)
230 #define AC5_MUTSPK1 TSC2101_BIT(2)
231 #define AC5_MUTSPK2 TSC2101_BIT(1)
232 #define AC5_HDSCPTC (0x01)
234 /* Field masks settings for TSC2101_AUDIO_CTRL_6 */
235 #define AC6_SPL2LSK TSC2101_BIT(15)
236 #define AC6_AST2LSK TSC2101_BIT(14)
237 #define AC6_BUZ2LSK TSC2101_BIT(13)
238 #define AC6_KCL2LSK TSC2101_BIT(12)
239 #define AC6_CPI2LSK TSC2101_BIT(11)
240 #define AC6_MIC2CPO TSC2101_BIT(10)
241 #define AC6_SPL2CPO TSC2101_BIT(9)
242 #define AC6_SPR2CPO TSC2101_BIT(8)
243 #define AC6_MUTLSPK TSC2101_BIT(7)
244 #define AC6_MUTSPK2 TSC2101_BIT(6)
245 #define AC6_LDSCPTC TSC2101_BIT(5)
246 #define AC6_VGNDSCPTC TSC2101_BIT(4)
247 #define AC6_CAPINTF TSC2101_BIT(3)
249 /* Field masks settings for TSC2101_AUDIO_CTRL_7 */
250 #define AC7_DETECT TSC2101_BIT(15)
251 #define AC7_HESTYPE(ARG) (((ARG) & 0x03) << 13)
252 #define AC7_HDDETFL TSC2101_BIT(12)
253 #define AC7_BDETFL TSC2101_BIT(11)
254 #define AC7_HDDEBNPG(ARG) (((ARG) & 0x03) << 9)
255 #define AC7_BDEBNPG(ARG) (((ARG) & 0x03) << 6)
256 #define AC7_DGPIO2 TSC2101_BIT(4)
257 #define AC7_DGPIO1 TSC2101_BIT(3)
258 #define AC7_CLKGPIO2 TSC2101_BIT(2)
259 #define AC7_ADWSF(ARG) (((ARG) & 0x03))
261 /* Field masks settings for TSC2101_GPIO_CTRL */
262 #define GC_GPO2EN TSC2101_BIT(15)
263 #define GC_GPO2SG TSC2101_BIT(14)
264 #define GC_GPI2EN TSC2101_BIT(13)
265 #define GC_GPI2SGF TSC2101_BIT(12)
266 #define GC_GPO1EN TSC2101_BIT(11)
267 #define GC_GPO1SG TSC2101_BIT(10)
268 #define GC_GPI1EN TSC2101_BIT(9)
269 #define GC_GPI1SGF TSC2101_BIT(8)
271 /* Field masks for TSC2101_AGC_CTRL */
272 #define AC_AGCNF_CELL TSC2101_BIT(14)
273 #define AC_AGCNL(ARG) (((ARG) & 0x07) << 11)
274 #define AC_AGCHYS_CELL(ARG) (((ARG) & 0x03) << 9)
275 #define AC_CLPST_CELL TSC2101_BIT(8)
276 #define AC_AGCTG_CELL(ARG) (((ARG) & 0x07) << 5)
277 #define AC_AGCTC_CELL(ARG) (((ARG) & 0x0F) << 1)
278 #define AC_AGCEN_CELL (0x01)
280 /* Field masks for TSC2101_POWERDOWN_STS */
281 #define PS_SPK1FL TSC2101_BIT(15)
282 #define PS_SPK2FL TSC2101_BIT(14)
283 #define PS_HNDFL TSC2101_BIT(13)
284 #define PS_VGNDFL TSC2101_BIT(12)
285 #define PS_LSPKFL TSC2101_BIT(11)
286 #define PS_CELLFL TSC2101_BIT(10)
287 #define PS_PSEQ TSC2101_BIT(5)
288 #define PS_PSTIME TSC2101_BIT(4)
290 /* Field masks for Register Mic AGC Control */
291 #define MAC_MMPGA(ARG) (((ARG) & 0x7F) << 9)
292 #define MAC_MDEBNS(ARG) (((ARG) & 0x07) << 6)
293 #define MAC_MDEBSN(ARG) (((ARG) & 0x07) << 3)
295 /* Field masks for Register Cellphone AGC Control */
296 #define CAC_CMPGA(ARG) (((ARG) & 0x7F) << 9)
297 #define CAC_CDEBNS(ARG) (((ARG) & 0x07) << 6)
298 #define CAC_CDEBSN(ARG) (((ARG) & 0x07) << 3)
300 #endif /* __ASM_HARDWARE_TSC2101_H */