2 * linux/include/asm-arm/arch-omap/gpio.h
4 * Defines for Multi-Channel Buffered Serial Port
6 * Copyright (C) 2002 RidgeRun, Inc.
7 * Author: Steve Johnson
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #ifndef __ASM_ARCH_OMAP_MCBSP_H
25 #define __ASM_ARCH_OMAP_MCBSP_H
27 #include <asm/hardware.h>
29 #define OMAP730_MCBSP1_BASE 0xfffb1000
30 #define OMAP730_MCBSP2_BASE 0xfffb1800
32 #define OMAP1510_MCBSP1_BASE 0xe1011800
33 #define OMAP1510_MCBSP2_BASE 0xfffb1000
34 #define OMAP1510_MCBSP3_BASE 0xe1017000
36 #define OMAP1610_MCBSP1_BASE 0xe1011800
37 #define OMAP1610_MCBSP2_BASE 0xfffb1000
38 #define OMAP1610_MCBSP3_BASE 0xe1017000
40 #define OMAP24XX_MCBSP1_BASE 0x48074000
41 #define OMAP24XX_MCBSP2_BASE 0x48076000
43 #ifdef CONFIG_ARCH_OMAP16XX
45 #define OMAP_MCBSP_REG_DRR2 0x00
46 #define OMAP_MCBSP_REG_DRR1 0x02
47 #define OMAP_MCBSP_REG_DXR2 0x04
48 #define OMAP_MCBSP_REG_DXR1 0x06
49 #define OMAP_MCBSP_REG_SPCR2 0x08
50 #define OMAP_MCBSP_REG_SPCR1 0x0a
51 #define OMAP_MCBSP_REG_RCR2 0x0c
52 #define OMAP_MCBSP_REG_RCR1 0x0e
53 #define OMAP_MCBSP_REG_XCR2 0x10
54 #define OMAP_MCBSP_REG_XCR1 0x12
55 #define OMAP_MCBSP_REG_SRGR2 0x14
56 #define OMAP_MCBSP_REG_SRGR1 0x16
57 #define OMAP_MCBSP_REG_MCR2 0x18
58 #define OMAP_MCBSP_REG_MCR1 0x1a
59 #define OMAP_MCBSP_REG_RCERA 0x1c
60 #define OMAP_MCBSP_REG_RCERB 0x1e
61 #define OMAP_MCBSP_REG_XCERA 0x20
62 #define OMAP_MCBSP_REG_XCERB 0x22
63 #define OMAP_MCBSP_REG_PCR0 0x24
64 #define OMAP_MCBSP_REG_RCERC 0x26
65 #define OMAP_MCBSP_REG_RCERD 0x28
66 #define OMAP_MCBSP_REG_XCERC 0x2A
67 #define OMAP_MCBSP_REG_XCERD 0x2C
68 #define OMAP_MCBSP_REG_RCERE 0x2E
69 #define OMAP_MCBSP_REG_RCERF 0x30
70 #define OMAP_MCBSP_REG_XCERE 0x32
71 #define OMAP_MCBSP_REG_XCERF 0x34
72 #define OMAP_MCBSP_REG_RCERG 0x36
73 #define OMAP_MCBSP_REG_RCERH 0x38
74 #define OMAP_MCBSP_REG_XCERG 0x3A
75 #define OMAP_MCBSP_REG_XCERH 0x3C
77 #define OMAP_MAX_MCBSP_COUNT 3
79 #define AUDIO_MCBSP OMAP_MCBSP1
80 #define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX
81 #define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX
83 #elif defined(CONFIG_ARCH_OMAP24XX)
85 #define OMAP_MCBSP_REG_DRR2 0x00
86 #define OMAP_MCBSP_REG_DRR1 0x04
87 #define OMAP_MCBSP_REG_DXR2 0x08
88 #define OMAP_MCBSP_REG_DXR1 0x0C
89 #define OMAP_MCBSP_REG_SPCR2 0x10
90 #define OMAP_MCBSP_REG_SPCR1 0x14
91 #define OMAP_MCBSP_REG_RCR2 0x18
92 #define OMAP_MCBSP_REG_RCR1 0x1C
93 #define OMAP_MCBSP_REG_XCR2 0x20
94 #define OMAP_MCBSP_REG_XCR1 0x24
95 #define OMAP_MCBSP_REG_SRGR2 0x28
96 #define OMAP_MCBSP_REG_SRGR1 0x2C
97 #define OMAP_MCBSP_REG_MCR2 0x30
98 #define OMAP_MCBSP_REG_MCR1 0x34
99 #define OMAP_MCBSP_REG_RCERA 0x38
100 #define OMAP_MCBSP_REG_RCERB 0x3C
101 #define OMAP_MCBSP_REG_XCERA 0x40
102 #define OMAP_MCBSP_REG_XCERB 0x44
103 #define OMAP_MCBSP_REG_PCR0 0x48
104 #define OMAP_MCBSP_REG_RCERC 0x4C
105 #define OMAP_MCBSP_REG_RCERD 0x50
106 #define OMAP_MCBSP_REG_XCERC 0x54
107 #define OMAP_MCBSP_REG_XCERD 0x58
108 #define OMAP_MCBSP_REG_RCERE 0x5C
109 #define OMAP_MCBSP_REG_RCERF 0x60
110 #define OMAP_MCBSP_REG_XCERE 0x64
111 #define OMAP_MCBSP_REG_XCERF 0x68
112 #define OMAP_MCBSP_REG_RCERG 0x6C
113 #define OMAP_MCBSP_REG_RCERH 0x70
114 #define OMAP_MCBSP_REG_XCERG 0x74
115 #define OMAP_MCBSP_REG_XCERH 0x78
117 #define OMAP_MAX_MCBSP_COUNT 2
119 #define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
120 #define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
122 #define AUDIO_MCBSP OMAP_MCBSP2
123 #define AUDIO_DMA_TX OMAP24XX_DMA_MCBSP2_TX
124 #define AUDIO_DMA_RX OMAP24XX_DMA_MCBSP2_RX
128 #define OMAP_MCBSP_READ(base, reg) __raw_readw((base) + OMAP_MCBSP_REG_##reg)
129 #define OMAP_MCBSP_WRITE(base, reg, val) __raw_writew((val), (base) + OMAP_MCBSP_REG_##reg)
132 /************************** McBSP SPCR1 bit definitions ***********************/
136 #define RSYNC_ERR 0x0008
137 #define RINTM(value) ((value)<<4) /* bits 4:5 */
140 #define CLKSTP(value) ((value)<<11) /* bits 11:12 */
141 #define RJUST(value) ((value)<<13) /* bits 13:14 */
144 /************************** McBSP SPCR2 bit definitions ***********************/
147 #define XEMPTY 0x0004
148 #define XSYNC_ERR 0x0008
149 #define XINTM(value) ((value)<<4) /* bits 4:5 */
155 /************************** McBSP PCR bit definitions *************************/
160 #define DR_STAT 0x0010
161 #define DX_STAT 0x0020
162 #define CLKS_STAT 0x0040
163 #define SCLKME 0x0080
170 #define IDLE_EN 0x4000
172 /************************** McBSP RCR1 bit definitions ************************/
173 #define RWDLEN1(value) ((value)<<5) /* Bits 5:7 */
174 #define RFRLEN1(value) ((value)<<8) /* Bits 8:14 */
176 /************************** McBSP XCR1 bit definitions ************************/
177 #define XWDLEN1(value) ((value)<<5) /* Bits 5:7 */
178 #define XFRLEN1(value) ((value)<<8) /* Bits 8:14 */
180 /*************************** McBSP RCR2 bit definitions ***********************/
181 #define RDATDLY(value) (value) /* Bits 0:1 */
183 #define RCOMPAND(value) ((value)<<3) /* Bits 3:4 */
184 #define RWDLEN2(value) ((value)<<5) /* Bits 5:7 */
185 #define RFRLEN2(value) ((value)<<8) /* Bits 8:14 */
186 #define RPHASE 0x8000
188 /*************************** McBSP XCR2 bit definitions ***********************/
189 #define XDATDLY(value) (value) /* Bits 0:1 */
191 #define XCOMPAND(value) ((value)<<3) /* Bits 3:4 */
192 #define XWDLEN2(value) ((value)<<5) /* Bits 5:7 */
193 #define XFRLEN2(value) ((value)<<8) /* Bits 8:14 */
194 #define XPHASE 0x8000
196 /************************* McBSP SRGR1 bit definitions ************************/
197 #define CLKGDV(value) (value) /* Bits 0:7 */
198 #define FWID(value) ((value)<<8) /* Bits 8:15 */
200 /************************* McBSP SRGR2 bit definitions ************************/
201 #define FPER(value) (value) /* Bits 0:11 */
207 /************************* McBSP MCR1 bit definitions *************************/
209 #define RCBLK(value) ((value)<<2) /* Bits 2:4 */
210 #define RPABLK(value) ((value)<<5) /* Bits 5:6 */
211 #define RPBBLK(value) ((value)<<7) /* Bits 7:8 */
213 /************************* McBSP MCR2 bit definitions *************************/
214 #define XMCM(value) (value) /* Bits 0:1 */
215 #define XCBLK(value) ((value)<<2) /* Bits 2:4 */
216 #define XPABLK(value) ((value)<<5) /* Bits 5:6 */
217 #define XPBBLK(value) ((value)<<7) /* Bits 7:8 */
220 /* we don't do multichannel for now */
221 struct omap_mcbsp_reg_cfg {
254 OMAP_MCBSP_WORD_8 = 0,
260 } omap_mcbsp_word_length;
263 OMAP_MCBSP_CLK_RISING = 0,
264 OMAP_MCBSP_CLK_FALLING,
265 } omap_mcbsp_clk_polarity;
268 OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
269 OMAP_MCBSP_FS_ACTIVE_LOW,
270 } omap_mcbsp_fs_polarity;
273 OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
274 OMAP_MCBSP_CLK_STP_MODE_DELAY,
275 } omap_mcbsp_clk_stp_mode;
278 /******* SPI specific mode **********/
280 OMAP_MCBSP_SPI_MASTER = 0,
281 OMAP_MCBSP_SPI_SLAVE,
282 } omap_mcbsp_spi_mode;
284 struct omap_mcbsp_spi_cfg {
285 omap_mcbsp_spi_mode spi_mode;
286 omap_mcbsp_clk_polarity rx_clock_polarity;
287 omap_mcbsp_clk_polarity tx_clock_polarity;
288 omap_mcbsp_fs_polarity fsx_polarity;
290 omap_mcbsp_clk_stp_mode clk_stp_mode;
291 omap_mcbsp_word_length word_length;
294 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
295 int omap_mcbsp_request(unsigned int id);
296 void omap_mcbsp_free(unsigned int id);
297 void omap_mcbsp_start(unsigned int id);
298 void omap_mcbsp_stop(unsigned int id);
299 void omap_mcbsp_xmit_word(unsigned int id, u32 word);
300 u32 omap_mcbsp_recv_word(unsigned int id);
302 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
303 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
305 /* SPI specific API */
306 void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
308 /* Polled read/write functions */
309 int omap_mcbsp_pollread(unsigned int id, u16 * buf);
310 int omap_mcbsp_pollwrite(unsigned int id, u16 buf);