2 * Copyright 2005 Mentor Graphics Corporation
3 * USB High-Speed Multi-Point Dual-Role Controller Configuration
5 * Copyright Mentor Graphics Corporation and Licensors 2004
6 * Copyright (C) 2005 by Texas Instruments
8 * This file contains configuration constants for the (m)hdrc
9 * silicon as integrated into DaVinci CPUs.
12 #ifndef __ARCH_MUSB_HDRC_CNF
13 #define __ARCH_MUSB_HDRC_CNF
15 /* ** Number of Tx endpoints ** */
16 /* Legal values are 1 - 16 (this value includes EP0) */
17 #define MUSB_C_NUM_EPT 8
19 /* ** Number of Rx endpoints ** */
20 /* Legal values are 1 - 16 (this value includes EP0) */
21 #define MUSB_C_NUM_EPR 8
23 /* ** Endpoint 1 to 15 direction types ** */
24 /* C_EP1_DEF is defined if either Tx endpoint 1 or Rx endpoint 1 are used */
25 #define MUSB_C_EP1_DEF
27 /* C_EP1_TX_DEF is defined if Tx endpoint 1 is used */
28 #define MUSB_C_EP1_TX_DEF
30 /* C_EP1_RX_DEF is defined if Rx endpoint 1 is used */
31 #define MUSB_C_EP1_RX_DEF
33 /* C_EP1_TOR_DEF is defined if Tx endpoint 1 and Rx endpoint 1 share a FIFO */
34 /*`define C_EP1_TOR_DEF */
36 /* C_EP1_TAR_DEF is defined if both Tx endpoint 1 and Rx endpoint 1 are used */
37 /* and do not share a FIFO */
38 #define MUSB_C_EP1_TAR_DEF
40 /* Similarly for all other used endpoints */
41 #define MUSB_C_EP2_DEF
42 #define MUSB_C_EP2_TX_DEF
43 #define MUSB_C_EP2_RX_DEF
44 #define MUSB_C_EP2_TAR_DEF
45 #define MUSB_C_EP3_DEF
46 #define MUSB_C_EP3_TX_DEF
47 #define MUSB_C_EP3_RX_DEF
48 #define MUSB_C_EP3_TAR_DEF
49 #define MUSB_C_EP4_DEF
50 #define MUSB_C_EP4_TX_DEF
51 #define MUSB_C_EP4_RX_DEF
52 #define MUSB_C_EP4_TAR_DEF
53 #define MUSB_C_EP5_DEF
54 #define MUSB_C_EP5_TX_DEF
55 #define MUSB_C_EP5_RX_DEF
56 #define MUSB_C_EP5_TAR_DEF
57 #define MUSB_C_EP6_DEF
58 #define MUSB_C_EP6_TX_DEF
59 #define MUSB_C_EP6_RX_DEF
60 #define MUSB_C_EP6_TAR_DEF
61 #define MUSB_C_EP7_DEF
62 #define MUSB_C_EP7_TX_DEF
63 #define MUSB_C_EP7_RX_DEF
64 #define MUSB_C_EP7_TAR_DEF
66 /* ** Endpoint 1 to 15 FIFO address bits ** */
67 /* Legal values are 3 to 13 - corresponding to FIFO sizes of 8 to 8192 bytes. */
68 /* If an Tx endpoint shares a FIFO with an Rx endpoint then the Rx FIFO size */
69 /* must be the same as the Tx FIFO size. */
70 /* All endpoints 1 to 15 must be defined, unused endpoints should be set to 2. */
71 #define MUSB_C_EP1T_BITS 10
72 #define MUSB_C_EP1R_BITS 10
73 #define MUSB_C_EP2T_BITS 9
74 #define MUSB_C_EP2R_BITS 9
75 #define MUSB_C_EP3T_BITS 3
76 #define MUSB_C_EP3R_BITS 3
77 #define MUSB_C_EP4T_BITS 3
78 #define MUSB_C_EP4R_BITS 3
79 #define MUSB_C_EP5T_BITS 3
80 #define MUSB_C_EP5R_BITS 3
81 #define MUSB_C_EP6T_BITS 3
82 #define MUSB_C_EP6R_BITS 3
83 #define MUSB_C_EP7T_BITS 3
84 #define MUSB_C_EP7R_BITS 3
85 #define MUSB_C_EP8T_BITS 2
86 #define MUSB_C_EP8R_BITS 2
87 #define MUSB_C_EP9T_BITS 2
88 #define MUSB_C_EP9R_BITS 2
89 #define MUSB_C_EP10T_BITS 2
90 #define MUSB_C_EP10R_BITS 2
91 #define MUSB_C_EP11T_BITS 2
92 #define MUSB_C_EP11R_BITS 2
93 #define MUSB_C_EP12T_BITS 2
94 #define MUSB_C_EP12R_BITS 2
95 #define MUSB_C_EP13T_BITS 2
96 #define MUSB_C_EP13R_BITS 2
97 #define MUSB_C_EP14T_BITS 2
98 #define MUSB_C_EP14R_BITS 2
99 #define MUSB_C_EP15T_BITS 2
100 #define MUSB_C_EP15R_BITS 2
102 /* Define the following constant if the USB2.0 Transceiver Macrocell data width is 16-bits. */
103 /* `define C_UTM_16 */
105 /* Define this constant if the CPU uses big-endian byte ordering. */
106 /*`define C_BIGEND */
108 /* Define the following constant if any Tx endpoint is required to support multiple bulk packets. */
109 /* `define C_MP_TX */
111 /* Define the following constant if any Rx endpoint is required to support multiple bulk packets. */
112 /* `define C_MP_RX */
114 /* Define the following constant if any Tx endpoint is required to support high bandwidth ISO. */
115 /* `define C_HB_TX */
117 /* Define the following constant if any Rx endpoint is required to support high bandwidth ISO. */
118 /* `define C_HB_RX */
120 /* Define the following constant if software connect/disconnect control is required. */
121 #define MUSB_C_SOFT_CON
123 /* Define the following constant if Vendor Control Registers are required. */
124 /* `define C_VEND_REG */
126 /* Vendor control register widths. */
127 #define MUSB_C_VCTL_BITS 4
128 #define MUSB_C_VSTAT_BITS 8
131 /* Define the following constant to include a DMA controller. */
134 /* Define the following constant if 2 or more DMA channels are required. */
137 /* Define the following constant if 3 or more DMA channels are required. */
140 /* Define the following constant if 4 or more DMA channels are required. */
143 /* Define the following constant if 5 or more DMA channels are required. */
146 /* Define the following constant if 6 or more DMA channels are required. */
149 /* Define the following constant if 7 or more DMA channels are required. */
152 /* Define the following constant if 8 or more DMA channels are required. */
156 /* ** Enable Dynamic FIFO Sizing ** */
157 #define MUSB_C_DYNFIFO_DEF
159 /* ** Derived constants ** */
160 /* The following constants are derived from the previous configuration constants */
162 /* Total number of endpoints
163 * Legal values are 2 - 16
164 * This must be equal to the larger of C_NUM_EPT, C_NUM_EPR
166 #define MUSB_C_NUM_EPS 8
168 /* C_EPMAX_BITS is equal to the largest endpoint FIFO word address bits */
169 #define MUSB_C_EPMAX_BITS 12
171 /* C_RAM_BITS is the number of address bits required to address the RAM (32-bit
172 * addresses). It is defined as log2 of the sum of 2** of all the endpoint FIFO
173 * dword address bits (rounded up).
175 #define MUSB_C_RAM_BITS 12
177 #endif /* __ARCH_MUSB_HDRC_CNF */