2 * linux/include/asm-arm/arch-omap/hardware.h
4 * Hardware definitions for TI OMAP processors and boards
6 * NOTE: Please put device driver specific defines into a separate header
7 * file for each driver.
9 * Copyright (C) 2001 RidgeRun, Inc.
10 * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
12 * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
13 * and Dirk Behme <dirk.behme@de.bosch.com>
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
21 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
23 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
26 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 * You should have received a copy of the GNU General Public License along
32 * with this program; if not, write to the Free Software Foundation, Inc.,
33 * 675 Mass Ave, Cambridge, MA 02139, USA.
36 #ifndef __ASM_ARCH_OMAP_HARDWARE_H
37 #define __ASM_ARCH_OMAP_HARDWARE_H
39 #include <asm/sizes.h>
40 #include <linux/config.h>
42 #include <asm/types.h>
43 #include <asm/arch/cpu.h>
45 #include <asm/arch/io.h>
48 * ---------------------------------------------------------------------------
49 * Common definitions for all OMAP processors
50 * NOTE: Put all processor or board specific parts to the special header
52 * ---------------------------------------------------------------------------
56 * ----------------------------------------------------------------------------
58 * ----------------------------------------------------------------------------
60 #define OMAP_MPU_TIMER1_BASE (0xfffec500)
61 #define OMAP_MPU_TIMER2_BASE (0xfffec600)
62 #define OMAP_MPU_TIMER3_BASE (0xfffec700)
63 #define MPU_TIMER_FREE (1 << 6)
64 #define MPU_TIMER_CLOCK_ENABLE (1 << 5)
65 #define MPU_TIMER_AR (1 << 1)
66 #define MPU_TIMER_ST (1 << 0)
69 * ----------------------------------------------------------------------------
71 * ----------------------------------------------------------------------------
73 #define CLKGEN_REG_BASE (0xfffece00)
74 #define ARM_CKCTL (CLKGEN_REG_BASE + 0x0)
75 #define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4)
76 #define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8)
77 #define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC)
78 #define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10)
79 #define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14)
80 #define ARM_SYSST (CLKGEN_REG_BASE + 0x18)
81 #define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
87 #define SETARM_IDLE_SHIFT
89 /* DPLL control registers */
90 #define DPLL_CTL (0xfffecf00)
92 /* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
93 #define DSP_CONFIG_REG_BASE (0xe1008000)
94 #define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0)
95 #define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)
96 #define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)
97 #define DSP_RSTCT2 (DSP_CONFIG_REG_BASE + 0x14)
100 * ---------------------------------------------------------------------------
102 * ---------------------------------------------------------------------------
104 #define ULPD_REG_BASE (0xfffe0800)
105 #define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14)
106 #define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24)
107 #define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30)
108 # define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */
109 # define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */
110 #define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34)
111 # define SOFT_UDC_REQ (1 << 4)
112 # define SOFT_USB_CLK_REQ (1 << 3)
113 # define SOFT_DPLL_REQ (1 << 0)
114 #define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c)
115 #define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40)
116 #define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c)
117 #define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50)
118 #define ULPD_SOFT_DISABLE_REQ_REG (ULPD_REG_BASE + 0x68)
119 # define DIS_MMC2_DPLL_REQ (1 << 11)
120 # define DIS_MMC1_DPLL_REQ (1 << 10)
121 # define DIS_UART3_DPLL_REQ (1 << 9)
122 # define DIS_UART2_DPLL_REQ (1 << 8)
123 # define DIS_UART1_DPLL_REQ (1 << 7)
124 # define DIS_USB_HOST_DPLL_REQ (1 << 6)
125 #define ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74)
126 #define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c)
129 * ---------------------------------------------------------------------------
131 * ---------------------------------------------------------------------------
134 /* Watchdog timer within the OMAP3.2 gigacell */
135 #define OMAP_MPU_WATCHDOG_BASE (0xfffec800)
136 #define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0)
137 #define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
138 #define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
139 #define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8)
142 * ---------------------------------------------------------------------------
144 * ---------------------------------------------------------------------------
146 #define OMAP_IH1_BASE 0xfffecb00
147 #define OMAP_IH2_BASE 0xfffe0000
149 #define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00)
150 #define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04)
151 #define OMAP_IH1_SIR_IRQ (OMAP_IH1_BASE + 0x10)
152 #define OMAP_IH1_SIR_FIQ (OMAP_IH1_BASE + 0x14)
153 #define OMAP_IH1_CONTROL (OMAP_IH1_BASE + 0x18)
154 #define OMAP_IH1_ILR0 (OMAP_IH1_BASE + 0x1c)
155 #define OMAP_IH1_ISR (OMAP_IH1_BASE + 0x9c)
157 #define OMAP_IH2_ITR (OMAP_IH2_BASE + 0x00)
158 #define OMAP_IH2_MIR (OMAP_IH2_BASE + 0x04)
159 #define OMAP_IH2_SIR_IRQ (OMAP_IH2_BASE + 0x10)
160 #define OMAP_IH2_SIR_FIQ (OMAP_IH2_BASE + 0x14)
161 #define OMAP_IH2_CONTROL (OMAP_IH2_BASE + 0x18)
162 #define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c)
163 #define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c)
165 #define IRQ_ITR_REG_OFFSET 0x00
166 #define IRQ_MIR_REG_OFFSET 0x04
167 #define IRQ_SIR_IRQ_REG_OFFSET 0x10
168 #define IRQ_SIR_FIQ_REG_OFFSET 0x14
169 #define IRQ_CONTROL_REG_OFFSET 0x18
170 #define IRQ_ISR_REG_OFFSET 0x9c
171 #define IRQ_ILR0_REG_OFFSET 0x1c
172 #define IRQ_GMR_REG_OFFSET 0xa0
175 * ----------------------------------------------------------------------------
176 * System control registers
177 * ----------------------------------------------------------------------------
179 #define MOD_CONF_CTRL_0 0xfffe1080
180 #define MOD_CONF_CTRL_1 0xfffe1110
183 * ----------------------------------------------------------------------------
184 * Pin multiplexing registers
185 * ----------------------------------------------------------------------------
187 #define FUNC_MUX_CTRL_0 0xfffe1000
188 #define FUNC_MUX_CTRL_1 0xfffe1004
189 #define FUNC_MUX_CTRL_2 0xfffe1008
190 #define COMP_MODE_CTRL_0 0xfffe100c
191 #define FUNC_MUX_CTRL_3 0xfffe1010
192 #define FUNC_MUX_CTRL_4 0xfffe1014
193 #define FUNC_MUX_CTRL_5 0xfffe1018
194 #define FUNC_MUX_CTRL_6 0xfffe101C
195 #define FUNC_MUX_CTRL_7 0xfffe1020
196 #define FUNC_MUX_CTRL_8 0xfffe1024
197 #define FUNC_MUX_CTRL_9 0xfffe1028
198 #define FUNC_MUX_CTRL_A 0xfffe102C
199 #define FUNC_MUX_CTRL_B 0xfffe1030
200 #define FUNC_MUX_CTRL_C 0xfffe1034
201 #define FUNC_MUX_CTRL_D 0xfffe1038
202 #define PULL_DWN_CTRL_0 0xfffe1040
203 #define PULL_DWN_CTRL_1 0xfffe1044
204 #define PULL_DWN_CTRL_2 0xfffe1048
205 #define PULL_DWN_CTRL_3 0xfffe104c
206 #define PULL_DWN_CTRL_4 0xfffe10ac
208 /* OMAP-1610 specific multiplexing registers */
209 #define FUNC_MUX_CTRL_E 0xfffe1090
210 #define FUNC_MUX_CTRL_F 0xfffe1094
211 #define FUNC_MUX_CTRL_10 0xfffe1098
212 #define FUNC_MUX_CTRL_11 0xfffe109c
213 #define FUNC_MUX_CTRL_12 0xfffe10a0
214 #define PU_PD_SEL_0 0xfffe10b4
215 #define PU_PD_SEL_1 0xfffe10b8
216 #define PU_PD_SEL_2 0xfffe10bc
217 #define PU_PD_SEL_3 0xfffe10c0
218 #define PU_PD_SEL_4 0xfffe10c4
220 /* Timer32K for 1610 and 1710*/
221 #define OMAP_TIMER32K_BASE 0xFFFBC400
224 * ---------------------------------------------------------------------------
226 * ---------------------------------------------------------------------------
228 #define TIPB_PUBLIC_CNTL_BASE 0xfffed300
229 #define MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8)
230 #define TIPB_PRIVATE_CNTL_BASE 0xfffeca00
231 #define MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8)
234 * ----------------------------------------------------------------------------
236 * ----------------------------------------------------------------------------
238 #define MPUI_BASE (0xfffec900)
239 #define MPUI_CTRL (MPUI_BASE + 0x0)
240 #define MPUI_DEBUG_ADDR (MPUI_BASE + 0x4)
241 #define MPUI_DEBUG_DATA (MPUI_BASE + 0x8)
242 #define MPUI_DEBUG_FLAG (MPUI_BASE + 0xc)
243 #define MPUI_STATUS_REG (MPUI_BASE + 0x10)
244 #define MPUI_DSP_STATUS (MPUI_BASE + 0x14)
245 #define MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18)
246 #define MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c)
249 * ----------------------------------------------------------------------------
250 * LED Pulse Generator
251 * ----------------------------------------------------------------------------
253 #define OMAP_LPG1_BASE 0xfffbd000
254 #define OMAP_LPG2_BASE 0xfffbd800
255 #define OMAP_LPG1_LCR (OMAP_LPG1_BASE + 0x00)
256 #define OMAP_LPG1_PMR (OMAP_LPG1_BASE + 0x04)
257 #define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00)
258 #define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04)
260 #ifndef __ASSEMBLER__
263 * ---------------------------------------------------------------------------
265 * ---------------------------------------------------------------------------
267 #define OMAP_UART1_BASE (unsigned char *)0xfffb0000
268 #define OMAP_UART2_BASE (unsigned char *)0xfffb0800
269 #define OMAP_UART3_BASE (unsigned char *)0xfffb9800
270 #define OMAP_MAX_NR_PORTS 3
271 #define OMAP1510_BASE_BAUD (12000000/16)
272 #define OMAP16XX_BASE_BAUD (48000000/16)
274 #define is_omap_port(p) ({int __ret = 0; \
275 if (p == IO_ADDRESS(OMAP_UART1_BASE) || \
276 p == IO_ADDRESS(OMAP_UART2_BASE) || \
277 p == IO_ADDRESS(OMAP_UART3_BASE)) \
283 * ---------------------------------------------------------------------------
284 * Processor specific defines
285 * ---------------------------------------------------------------------------
289 #include "omap1510.h"
290 #include "omap16xx.h"
293 * ---------------------------------------------------------------------------
294 * Board specific defines
295 * ---------------------------------------------------------------------------
298 #ifdef CONFIG_MACH_OMAP_INNOVATOR
299 #include "board-innovator.h"
302 #ifdef CONFIG_MACH_OMAP_H2
303 #include "board-h2.h"
306 #ifdef CONFIG_MACH_OMAP_PERSEUS2
307 #include "board-perseus2.h"
310 #ifdef CONFIG_MACH_OMAP_H3
311 #include "board-h3.h"
314 #ifdef CONFIG_MACH_OMAP_H4
315 #include "board-h4.h"
316 #error "Support for H4 board not yet implemented."
319 #ifdef CONFIG_MACH_OMAP_OSK
320 #include "board-osk.h"
323 #ifdef CONFIG_MACH_VOICEBLUE
324 #include "board-voiceblue.h"
327 #ifdef CONFIG_MACH_NETSTAR
328 #include "board-netstar.h"
331 #endif /* !__ASSEMBLER__ */
333 #endif /* __ASM_ARCH_OMAP_HARDWARE_H */