2 * linux/include/asm-arm/arch-omap/clock.h
4 * Copyright (C) 2004 - 2005 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/cpufreq.h>
15 #ifndef __ARCH_ARM_OMAP_CLOCK_H
16 #define __ARCH_ARM_OMAP_CLOCK_H
21 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
31 const struct clksel_rate *rates;
35 void __iomem *mult_div1_reg;
40 unsigned long last_rounded_rate;
41 unsigned int rate_tolerance;
45 # if defined(CONFIG_ARCH_OMAP3)
48 void __iomem *control_reg;
53 void __iomem *autoidle_reg;
55 void __iomem *idlest_reg;
63 struct list_head node;
70 void __iomem *enable_reg;
73 void (*recalc)(struct clk *);
74 int (*set_rate)(struct clk *, unsigned long);
75 long (*round_rate)(struct clk *, unsigned long);
76 void (*init)(struct clk *);
77 int (*enable)(struct clk *);
78 void (*disable)(struct clk *);
79 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
81 void __iomem *clksel_reg;
83 const struct clksel *clksel;
84 struct dpll_data *dpll_data;
91 struct clk_functions {
92 int (*clk_enable)(struct clk *clk);
93 void (*clk_disable)(struct clk *clk);
94 long (*clk_round_rate)(struct clk *clk, unsigned long rate);
95 int (*clk_set_rate)(struct clk *clk, unsigned long rate);
96 int (*clk_set_parent)(struct clk *clk, struct clk *parent);
97 struct clk * (*clk_get_parent)(struct clk *clk);
98 void (*clk_allow_idle)(struct clk *clk);
99 void (*clk_deny_idle)(struct clk *clk);
100 void (*clk_disable_unused)(struct clk *clk);
101 #ifdef CONFIG_CPU_FREQ
102 void (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **table);
106 extern unsigned int mpurate;
108 extern int clk_init(struct clk_functions * custom_clocks);
109 extern int clk_register(struct clk *clk);
110 extern void clk_unregister(struct clk *clk);
111 extern void propagate_rate(struct clk *clk);
112 extern void recalculate_root_clocks(void);
113 extern void followparent_recalc(struct clk * clk);
114 extern void clk_allow_idle(struct clk *clk);
115 extern void clk_deny_idle(struct clk *clk);
116 extern int clk_get_usecount(struct clk *clk);
117 extern void clk_enable_init_clocks(void);
118 #ifdef CONFIG_CPU_FREQ
119 extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
123 #define RATE_CKCTL (1 << 0) /* Main fixed ratio clocks */
124 #define RATE_FIXED (1 << 1) /* Fixed clock rate */
125 #define RATE_PROPAGATES (1 << 2) /* Program children too */
126 #define VIRTUAL_CLOCK (1 << 3) /* Composite clock from table */
127 #define ALWAYS_ENABLED (1 << 4) /* Clock cannot be disabled */
128 #define ENABLE_REG_32BIT (1 << 5) /* Use 32-bit access */
129 #define VIRTUAL_IO_ADDRESS (1 << 6) /* Clock in virtual address */
130 #define CLOCK_IDLE_CONTROL (1 << 7)
131 #define CLOCK_NO_IDLE_PARENT (1 << 8)
132 #define DELAYED_APP (1 << 9) /* Delay application of clock */
133 #define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */
134 #define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */
135 #define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */
136 /* bits 13-20 are currently free */
137 #define CLOCK_IN_OMAP310 (1 << 21)
138 #define CLOCK_IN_OMAP730 (1 << 22)
139 #define CLOCK_IN_OMAP1510 (1 << 23)
140 #define CLOCK_IN_OMAP16XX (1 << 24)
141 #define CLOCK_IN_OMAP242X (1 << 25)
142 #define CLOCK_IN_OMAP243X (1 << 26)
143 #define CLOCK_IN_OMAP343X (1 << 27) /* clocks common to all 343X */
144 #define PARENT_CONTROLS_CLOCK (1 << 28)
145 #define CLOCK_IN_OMAP3430ES1 (1 << 29) /* 3430ES1 clocks only */
146 #define CLOCK_IN_OMAP3430ES2 (1 << 30) /* 3430ES2 clocks only */
148 /* Clksel_rate flags */
149 #define DEFAULT_RATE (1 << 0)
150 #define RATE_IN_242X (1 << 1)
151 #define RATE_IN_243X (1 << 2)
152 #define RATE_IN_343X (1 << 3) /* rates common to all 343X */
153 #define RATE_IN_3430ES2 (1 << 4) /* 3430ES2 rates only */
155 #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
158 /* CM_CLKSEL2_PLL.CORE_CLK_SRC options (24XX) */
159 #define CORE_CLK_SRC_32K 0
160 #define CORE_CLK_SRC_DPLL 1
161 #define CORE_CLK_SRC_DPLL_X2 2