2 * include/asm-arm/arch-at91rm9200/hardware.h
4 * Copyright (C) 2003 SAN People
5 * Copyright (C) 2003 ATMEL
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
14 #ifndef __ASM_ARCH_HARDWARE_H
15 #define __ASM_ARCH_HARDWARE_H
17 #include <asm/sizes.h>
19 #include <asm/arch/at91rm9200.h>
20 #include <asm/arch/at91rm9200_sys.h>
23 * Remap the peripherals from address 0xFFFA0000 .. 0xFFFFFFFF
24 * to 0xFEFA0000 .. 0xFF000000. (384Kb)
26 #define AT91_IO_PHYS_BASE 0xFFFA0000
27 #define AT91_IO_SIZE (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1)
28 #define AT91_IO_VIRT_BASE (0xFF000000 - AT91_IO_SIZE)
30 /* Convert a physical IO address to virtual IO address */
31 #define AT91_IO_P2V(x) ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE)
34 * Virtual to Physical Address mapping for IO devices.
36 #define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS)
37 #define AT91_VA_BASE_SPI AT91_IO_P2V(AT91RM9200_BASE_SPI)
38 #define AT91_VA_BASE_SSC2 AT91_IO_P2V(AT91RM9200_BASE_SSC2)
39 #define AT91_VA_BASE_SSC1 AT91_IO_P2V(AT91RM9200_BASE_SSC1)
40 #define AT91_VA_BASE_SSC0 AT91_IO_P2V(AT91RM9200_BASE_SSC0)
41 #define AT91_VA_BASE_US3 AT91_IO_P2V(AT91RM9200_BASE_US3)
42 #define AT91_VA_BASE_US2 AT91_IO_P2V(AT91RM9200_BASE_US2)
43 #define AT91_VA_BASE_US1 AT91_IO_P2V(AT91RM9200_BASE_US1)
44 #define AT91_VA_BASE_US0 AT91_IO_P2V(AT91RM9200_BASE_US0)
45 #define AT91_VA_BASE_EMAC AT91_IO_P2V(AT91RM9200_BASE_EMAC)
46 #define AT91_VA_BASE_TWI AT91_IO_P2V(AT91RM9200_BASE_TWI)
47 #define AT91_VA_BASE_MCI AT91_IO_P2V(AT91RM9200_BASE_MCI)
48 #define AT91_VA_BASE_UDP AT91_IO_P2V(AT91RM9200_BASE_UDP)
49 #define AT91_VA_BASE_TCB1 AT91_IO_P2V(AT91RM9200_BASE_TCB1)
50 #define AT91_VA_BASE_TCB0 AT91_IO_P2V(AT91RM9200_BASE_TCB0)
52 /* Internal SRAM is mapped below the IO devices */
53 #define AT91_SRAM_VIRT_BASE (AT91_IO_VIRT_BASE - AT91RM9200_SRAM_SIZE)
56 #define AT91_NR_UART 5 /* 4 USART3's and one DBGU port */
59 #define AT91_FLASH_BASE 0x10000000 /* NCS0: Flash physical base address */
62 #define AT91_SDRAM_BASE 0x20000000 /* NCS1: SDRAM physical base address */
65 #define AT91_SMARTMEDIA_BASE 0x40000000 /* NCS3: Smartmedia physical base address */
68 #define AT91_CF_BASE 0x50000000 /* NCS4-NCS6: Compact Flash physical base address */
71 #define AT91_SLOW_CLOCK 32768 /* slow clock */
76 static inline unsigned int at91_sys_read(unsigned int reg_offset)
78 void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
80 return __raw_readl(addr + reg_offset);
83 static inline void at91_sys_write(unsigned int reg_offset, unsigned long value)
85 void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
87 __raw_writel(value, addr + reg_offset);