drivers/w1/masters/omap_hdq.c

   1 /*
   2  * drivers/w1/masters/omap_hdq.c
   3  *
   4  * Copyright (C) 2007 Texas Instruments, Inc.
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2. This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  *
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/err.h>
  16 #include <linux/clk.h>
  17 #include <linux/io.h>
  18 #include <asm/irq.h>
  19 #include <mach/hardware.h>
  20
  21 #include "../w1.h"
  22 #include "../w1_int.h"
  23
  24 #define MOD_NAME        "OMAP_HDQ:"
  25
  26 #define OMAP_HDQ_REVISION                       0x00
  27 #define OMAP_HDQ_TX_DATA                        0x04
  28 #define OMAP_HDQ_RX_DATA                        0x08
  29 #define OMAP_HDQ_CTRL_STATUS                    0x0c
  30 #define OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK      (1<<6)
  31 #define OMAP_HDQ_CTRL_STATUS_CLOCKENABLE        (1<<5)
  32 #define OMAP_HDQ_CTRL_STATUS_GO                 (1<<4)
  33 #define OMAP_HDQ_CTRL_STATUS_INITIALIZATION     (1<<2)
  34 #define OMAP_HDQ_CTRL_STATUS_DIR                (1<<1)
  35 #define OMAP_HDQ_CTRL_STATUS_MODE               (1<<0)
  36 #define OMAP_HDQ_INT_STATUS                     0x10
  37 #define OMAP_HDQ_INT_STATUS_TXCOMPLETE          (1<<2)
  38 #define OMAP_HDQ_INT_STATUS_RXCOMPLETE          (1<<1)
  39 #define OMAP_HDQ_INT_STATUS_TIMEOUT             (1<<0)
  40 #define OMAP_HDQ_SYSCONFIG                      0x14
  41 #define OMAP_HDQ_SYSCONFIG_SOFTRESET            (1<<1)
  42 #define OMAP_HDQ_SYSCONFIG_AUTOIDLE             (1<<0)
  43 #define OMAP_HDQ_SYSSTATUS                      0x18
  44 #define OMAP_HDQ_SYSSTATUS_RESETDONE            (1<<0)
  45
  46 #define OMAP_HDQ_FLAG_CLEAR                     0
  47 #define OMAP_HDQ_FLAG_SET                       1
  48 #define OMAP_HDQ_TIMEOUT                        (HZ/5)
  49
  50 #define OMAP_HDQ_MAX_USER                       4
  51
  52 DECLARE_WAIT_QUEUE_HEAD(hdq_wait_queue);
  53 int W1_ID;
  54
  55 struct hdq_data {
  56         struct device           *dev;
  57         resource_size_t         hdq_base;
  58         struct  semaphore       hdq_semlock;
  59         int                     hdq_usecount;
  60         struct  clk             *hdq_ick;
  61         struct  clk             *hdq_fck;
  62         u8                      hdq_irqstatus;
  63         spinlock_t              hdq_spinlock;
  64 };
  65
  66 static int omap_hdq_get(struct hdq_data *hdq_data);
  67 static int omap_hdq_put(struct hdq_data *hdq_data);
  68 static int omap_hdq_break(struct hdq_data *hdq_data);
  69
  70 static int __init omap_hdq_probe(struct platform_device *pdev);
  71 static int omap_hdq_remove(struct platform_device *pdev);
  72
  73 static struct platform_driver omap_hdq_driver = {
  74         .probe = omap_hdq_probe,
  75         .remove = omap_hdq_remove,
  76         .suspend = NULL,
  77         .resume = NULL,
  78         .driver = {
  79                 .name = "omap_hdq",
  80         },
  81 };
  82
  83 static u8 omap_w1_read_byte(void *_hdq);
  84 static void omap_w1_write_byte(void *_hdq, u8 byte);
  85 static u8 omap_w1_reset_bus(void *_hdq);
  86 static void omap_w1_search_bus(void *_hdq, u8 search_type,
  87         w1_slave_found_callback slave_found);
  88
  89
  90 static struct w1_bus_master omap_w1_master = {
  91         .read_byte      = omap_w1_read_byte,
  92         .write_byte     = omap_w1_write_byte,
  93         .reset_bus      = omap_w1_reset_bus,
  94         .search         = omap_w1_search_bus,
  95 };
  96
  97 /*
  98  * HDQ register I/O routines
  99  */
 100 static inline u8 hdq_reg_in(struct hdq_data *hdq_data, u32 offset)
 101 {
 102         return omap_readb(hdq_data->hdq_base + offset);
 103 }
 104
 105 static inline u8 hdq_reg_out(struct hdq_data *hdq_data, u32 offset, u8 val)
 106 {
 107         omap_writeb(val, hdq_data->hdq_base + offset);
 108
 109         return val;
 110 }
 111
 112 static inline u8 hdq_reg_merge(struct hdq_data *hdq_data, u32 offset,
 113                         u8 val, u8 mask)
 114 {
 115         u8 new_val = (omap_readb(hdq_data->hdq_base + offset) & ~mask)
 116                         | (val & mask);
 117         omap_writeb(new_val, hdq_data->hdq_base + offset);
 118
 119         return new_val;
 120 }
 121
 122 /*
 123  * Wait for one or more bits in flag change.
 124  * HDQ_FLAG_SET: wait until any bit in the flag is set.
 125  * HDQ_FLAG_CLEAR: wait until all bits in the flag are cleared.
 126  * return 0 on success and -ETIMEDOUT in the case of timeout.
 127  */
 128 static int hdq_wait_for_flag(struct hdq_data *hdq_data, u32 offset,
 129                 u8 flag, u8 flag_set, u8 *status)
 130 {
 131         int ret = 0;
 132         unsigned long timeout = jiffies + OMAP_HDQ_TIMEOUT;
 133
 134         if (flag_set == OMAP_HDQ_FLAG_CLEAR) {
 135                 /* wait for the flag clear */
 136                 while (((*status = hdq_reg_in(hdq_data, offset)) & flag)
 137                         && time_before(jiffies, timeout)) {
 138                         set_current_state(TASK_UNINTERRUPTIBLE);
 139                         schedule_timeout(1);
 140                 }
 141                 if (unlikely(*status & flag))
 142                         ret = -ETIMEDOUT;
 143         } else if (flag_set == OMAP_HDQ_FLAG_SET) {
 144                 /* wait for the flag set */
 145                 while (!((*status = hdq_reg_in(hdq_data, offset)) & flag)
 146                         && time_before(jiffies, timeout)) {
 147                         set_current_state(TASK_UNINTERRUPTIBLE);
 148                         schedule_timeout(1);
 149                 }
 150                 if (unlikely(!(*status & flag)))
 151                         ret = -ETIMEDOUT;
 152         } else
 153                 return -EINVAL;
 154
 155         return ret;
 156 }
 157
 158 /*
 159  * write out a byte and fill *status with HDQ_INT_STATUS
 160  */
 161 static int
 162 hdq_write_byte(struct hdq_data *hdq_data, u8 val, u8 *status)
 163 {
 164         int ret;
 165         u8 tmp_status;
 166         unsigned long irqflags;
 167
 168         *status = 0;
 169
 170         spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
 171         /* clear interrupt flags via a dummy read */
 172         hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
 173         /* ISR loads it with new INT_STATUS */
 174         hdq_data->hdq_irqstatus = 0;
 175         spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
 176
 177         hdq_reg_out(hdq_data, OMAP_HDQ_TX_DATA, val);
 178
 179         /* set the GO bit */
 180         hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, OMAP_HDQ_CTRL_STATUS_GO,
 181                 OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO);
 182         /* wait for the TXCOMPLETE bit */
 183         ret = wait_event_interruptible_timeout(hdq_wait_queue,
 184                 hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT);
 185         if (unlikely(ret < 0)) {
 186                 dev_dbg(hdq_data->dev, "wait interrupted");
 187                 return -EINTR;
 188         }
 189
 190         spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
 191         *status = hdq_data->hdq_irqstatus;
 192         spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
 193         /* check irqstatus */
 194         if (!(*status & OMAP_HDQ_INT_STATUS_TXCOMPLETE)) {
 195                 dev_dbg(hdq_data->dev, "timeout waiting for"
 196                         "TXCOMPLETE/RXCOMPLETE, %x", *status);
 197                 return -ETIMEDOUT;
 198         }
 199
 200         /* wait for the GO bit return to zero */
 201         ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_CTRL_STATUS,
 202                         OMAP_HDQ_CTRL_STATUS_GO,
 203                         OMAP_HDQ_FLAG_CLEAR, &tmp_status);
 204         if (ret) {
 205                 dev_dbg(hdq_data->dev, "timeout waiting GO bit"
 206                         "return to zero, %x", tmp_status);
 207                 return ret;
 208         }
 209
 210         return ret;
 211 }
 212
 213 /*
 214  * HDQ Interrupt service routine.
 215  */
 216 static irqreturn_t hdq_isr(int irq, void *_hdq)
 217 {
 218         struct hdq_data *hdq_data = _hdq;
 219         unsigned long irqflags;
 220
 221         spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
 222         hdq_data->hdq_irqstatus = hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
 223         spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
 224         dev_dbg(hdq_data->dev, "hdq_isr: %x", hdq_data->hdq_irqstatus);
 225
 226         if (hdq_data->hdq_irqstatus &
 227                 (OMAP_HDQ_INT_STATUS_TXCOMPLETE | OMAP_HDQ_INT_STATUS_RXCOMPLETE
 228                 | OMAP_HDQ_INT_STATUS_TIMEOUT)) {
 229                 /* wake up sleeping process */
 230                 wake_up_interruptible(&hdq_wait_queue);
 231         }
 232
 233         return IRQ_HANDLED;
 234 }
 235
 236 /*
 237  * HDQ Mode: always return success.
 238  */
 239 static u8 omap_w1_reset_bus(void *_hdq)
 240 {
 241         return 0;
 242 }
 243
 244 /*
 245  * W1 search callback function.
 246  */
 247 static void omap_w1_search_bus(void *_hdq, u8 search_type,
 248         w1_slave_found_callback slave_found)
 249 {
 250         u64 module_id, rn_le, cs, id;
 251
 252         if (W1_ID)
 253                 module_id = W1_ID;
 254         else
 255                 module_id = 0x1;
 256
 257         rn_le = cpu_to_le64(module_id);
 258         /*
 259          * HDQ might not obey truly the 1-wire spec.
 260          * So calculate CRC based on module parameter.
 261          */
 262         cs = w1_calc_crc8((u8 *)&rn_le, 7);
 263         id = (cs << 56) | module_id;
 264
 265         slave_found(_hdq, id);
 266 }
 267
 268 static int _omap_hdq_reset(struct hdq_data *hdq_data)
 269 {
 270         int ret;
 271         u8 tmp_status;
 272
 273         hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG, OMAP_HDQ_SYSCONFIG_SOFTRESET);
 274         /*
 275          * Select HDQ mode & enable clocks.
 276          * It is observed that INT flags can't be cleared via a read and GO/INIT
 277          * won't return to zero if interrupt is disabled. So we always enable
 278          * interrupt.
 279          */
 280         hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
 281                 OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
 282                 OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
 283
 284         /* wait for reset to complete */
 285         ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_SYSSTATUS,
 286                 OMAP_HDQ_SYSSTATUS_RESETDONE, OMAP_HDQ_FLAG_SET, &tmp_status);
 287         if (ret)
 288                 dev_dbg(hdq_data->dev, "timeout waiting HDQ reset, %x",
 289                                 tmp_status);
 290         else {
 291                 hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
 292                         OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
 293                         OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
 294                 hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG,
 295                         OMAP_HDQ_SYSCONFIG_AUTOIDLE);
 296         }
 297
 298         return ret;
 299 }
 300
 301 /*
 302  * Issue break pulse to the device.
 303  */
 304 static int
 305 omap_hdq_break(struct hdq_data *hdq_data)
 306 {
 307         int ret;
 308         u8 tmp_status;
 309         unsigned long irqflags;
 310
 311         ret = down_interruptible(&hdq_data->hdq_semlock);
 312         if (ret < 0)
 313                 return -EINTR;
 314
 315         if (!hdq_data->hdq_usecount) {
 316                 up(&hdq_data->hdq_semlock);
 317                 return -EINVAL;
 318         }
 319
 320         spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
 321         /* clear interrupt flags via a dummy read */
 322         hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
 323         /* ISR loads it with new INT_STATUS */
 324         hdq_data->hdq_irqstatus = 0;
 325         spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
 326
 327         /* set the INIT and GO bit */
 328         hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS,
 329                 OMAP_HDQ_CTRL_STATUS_INITIALIZATION | OMAP_HDQ_CTRL_STATUS_GO,
 330                 OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_INITIALIZATION |
 331                 OMAP_HDQ_CTRL_STATUS_GO);
 332
 333         /* wait for the TIMEOUT bit */
 334         ret = wait_event_interruptible_timeout(hdq_wait_queue,
 335                 hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT);
 336         if (unlikely(ret < 0)) {
 337                 dev_dbg(hdq_data->dev, "wait interrupted");
 338                 up(&hdq_data->hdq_semlock);
 339                 return -EINTR;
 340         }
 341
 342         spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
 343         tmp_status = hdq_data->hdq_irqstatus;
 344         spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
 345         /* check irqstatus */
 346         if (!(tmp_status & OMAP_HDQ_INT_STATUS_TIMEOUT)) {
 347                 dev_dbg(hdq_data->dev, "timeout waiting for TIMEOUT, %x",
 348                                 tmp_status);
 349                 up(&hdq_data->hdq_semlock);
 350                 return -ETIMEDOUT;
 351         }
 352         /*
 353          * wait for both INIT and GO bits rerurn to zero.
 354          * zero wait time expected for interrupt mode.
 355          */
 356         ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_CTRL_STATUS,
 357                         OMAP_HDQ_CTRL_STATUS_INITIALIZATION |
 358                         OMAP_HDQ_CTRL_STATUS_GO, OMAP_HDQ_FLAG_CLEAR,
 359                         &tmp_status);
 360         if (ret)
 361                 dev_dbg(hdq_data->dev, "timeout waiting INIT&GO bits"
 362                         "return to zero, %x", tmp_status);
 363
 364         up(&hdq_data->hdq_semlock);
 365         return ret;
 366 }
 367
 368 static int hdq_read_byte(struct hdq_data *hdq_data, u8 *val)
 369 {
 370         int ret;
 371         u8 status;
 372         unsigned long irqflags;
 373
 374         ret = down_interruptible(&hdq_data->hdq_semlock);
 375         if (ret < 0)
 376                 return -EINTR;
 377
 378         if (!hdq_data->hdq_usecount) {
 379                 up(&hdq_data->hdq_semlock);
 380                 return -EINVAL;
 381         }
 382
 383         if (!(hdq_data->hdq_irqstatus & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) {
 384                 hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS,
 385                         OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO,
 386                         OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO);
 387                 /*
 388                  * The RX comes immediately after TX. It
 389                  * triggers another interrupt before we
 390                  * sleep. So we have to wait for RXCOMPLETE bit.
 391                  */
 392                 {
 393                         unsigned long timeout = jiffies + OMAP_HDQ_TIMEOUT;
 394                         while (!(hdq_data->hdq_irqstatus
 395                                 & OMAP_HDQ_INT_STATUS_RXCOMPLETE)
 396                                 && time_before(jiffies, timeout)) {
 397                                 set_current_state(TASK_UNINTERRUPTIBLE);
 398                                 schedule_timeout(1);
 399                         }
 400                 }
 401                 hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, 0,
 402                         OMAP_HDQ_CTRL_STATUS_DIR);
 403                 spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
 404                 status = hdq_data->hdq_irqstatus;
 405                 spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
 406                 /* check irqstatus */
 407                 if (!(status & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) {
 408                         dev_dbg(hdq_data->dev, "timeout waiting for"
 409                                 "RXCOMPLETE, %x", status);
 410                         up(&hdq_data->hdq_semlock);
 411                         return -ETIMEDOUT;
 412                 }
 413         }
 414         /* the data is ready. Read it in! */
 415         *val = hdq_reg_in(hdq_data, OMAP_HDQ_RX_DATA);
 416         up(&hdq_data->hdq_semlock);
 417
 418         return 0;
 419
 420 }
 421
 422 /*
 423  * Enable clocks and set the controller to HDQ mode.
 424  */
 425 static int
 426 omap_hdq_get(struct hdq_data *hdq_data)
 427 {
 428         int ret = 0;
 429
 430         ret = down_interruptible(&hdq_data->hdq_semlock);
 431         if (ret < 0)
 432                 return -EINTR;
 433
 434         if (OMAP_HDQ_MAX_USER == hdq_data->hdq_usecount) {
 435                 dev_dbg(hdq_data->dev, "attempt to exceed the max use count");
 436                 up(&hdq_data->hdq_semlock);
 437                 ret = -EINVAL;
 438         } else {
 439                 hdq_data->hdq_usecount++;
 440                 try_module_get(THIS_MODULE);
 441                 if (1 == hdq_data->hdq_usecount) {
 442                         if (clk_enable(hdq_data->hdq_ick)) {
 443                                 dev_dbg(hdq_data->dev, "Can not enable ick\n");
 444                                 clk_put(hdq_data->hdq_ick);
 445                                 clk_put(hdq_data->hdq_fck);
 446                                 up(&hdq_data->hdq_semlock);
 447                                 return -ENODEV;
 448                         }
 449                         if (clk_enable(hdq_data->hdq_fck)) {
 450                                 dev_dbg(hdq_data->dev, "Can not enable fck\n");
 451                                 clk_put(hdq_data->hdq_ick);
 452                                 clk_put(hdq_data->hdq_fck);
 453                                 up(&hdq_data->hdq_semlock);
 454                                 return -ENODEV;
 455                         }
 456
 457                         /* make sure HDQ is out of reset */
 458                         if (!(hdq_reg_in(hdq_data, OMAP_HDQ_SYSSTATUS) &
 459                                 OMAP_HDQ_SYSSTATUS_RESETDONE)) {
 460                                 ret = _omap_hdq_reset(hdq_data);
 461                                 if (ret)
 462                                         /* back up the count */
 463                                         hdq_data->hdq_usecount--;
 464                         } else {
 465                                 /* select HDQ mode & enable clocks */
 466                                 hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
 467                                         OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
 468                                         OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
 469                                 hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG,
 470                                         OMAP_HDQ_SYSCONFIG_AUTOIDLE);
 471                                 hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
 472                         }
 473                 }
 474         }
 475         up(&hdq_data->hdq_semlock);
 476         return ret;
 477 }
 478
 479 /*
 480  * Disable clocks to the module.
 481  */
 482 static int
 483 omap_hdq_put(struct hdq_data *hdq_data)
 484 {
 485         int ret = 0;
 486
 487         ret = down_interruptible(&hdq_data->hdq_semlock);
 488         if (ret < 0)
 489                 return -EINTR;
 490
 491         if (0 == hdq_data->hdq_usecount) {
 492                 dev_dbg(hdq_data->dev, "attempt to decrement use count"
 493                         "when it is zero");
 494                 ret = -EINVAL;
 495         } else {
 496                 hdq_data->hdq_usecount--;
 497                 module_put(THIS_MODULE);
 498                 if (0 == hdq_data->hdq_usecount) {
 499                         clk_disable(hdq_data->hdq_ick);
 500                         clk_disable(hdq_data->hdq_fck);
 501                 }
 502         }
 503         up(&hdq_data->hdq_semlock);
 504         return ret;
 505 }
 506
 507 /*
 508  * Used to control the call to omap_hdq_get and omap_hdq_put.
 509  * HDQ Protocol: Write the CMD|REG_address first, followed by
 510  * the data wrire or read.
 511  */
 512 static int init_trans;
 513
 514 /*
 515  * Read a byte of data from the device.
 516  */
 517 static u8 omap_w1_read_byte(void *_hdq)
 518 {
 519         struct hdq_data *hdq_data = _hdq;
 520         u8 val;
 521         int ret;
 522
 523         ret = hdq_read_byte(hdq_data, &val);
 524         if (ret) {
 525                 init_trans = 0;
 526                 omap_hdq_put(hdq_data);
 527                 return -1;
 528         }
 529
 530         /* Write followed by a read, release the module */
 531         if (init_trans) {
 532                 init_trans = 0;
 533                 omap_hdq_put(hdq_data);
 534         }
 535
 536         return val;
 537 }
 538
 539 /*
 540  * Write a byte of data to the device.
 541  */
 542 static void omap_w1_write_byte(void *_hdq, u8 byte)
 543 {
 544         struct hdq_data *hdq_data = _hdq;
 545         u8 status;
 546
 547         /* First write to initialize the transfer */
 548         if (init_trans == 0)
 549                 omap_hdq_get(hdq_data);
 550
 551         init_trans++;
 552
 553         hdq_write_byte(hdq_data, byte, &status);
 554         dev_dbg(hdq_data->dev, "Ctrl status %x\n", status);
 555
 556         /* Second write, data transfered. Release the module */
 557         if (init_trans > 1) {
 558                 omap_hdq_put(hdq_data);
 559                 init_trans = 0;
 560         }
 561
 562         return;
 563 }
 564
 565 static int __init omap_hdq_probe(struct platform_device *pdev)
 566 {
 567         struct hdq_data *hdq_data;
 568         struct resource *res;
 569         int ret, irq;
 570         u8 rev;
 571
 572         if (!pdev)
 573                 return -ENODEV;
 574
 575         hdq_data = kmalloc(sizeof(*hdq_data), GFP_KERNEL);
 576         if (!hdq_data) {
 577                 dev_dbg(&pdev->dev, "unable to allocate memory\n");
 578                 ret = -ENODEV;
 579                 goto err_kmalloc;
 580         }
 581
 582         hdq_data->dev = &pdev->dev;
 583         platform_set_drvdata(pdev, hdq_data);
 584
 585         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 586         if (!res) {
 587                 dev_dbg(&pdev->dev, "unable to get resource\n");
 588                 ret = ENXIO;
 589                 goto err_resource;
 590         }
 591
 592         hdq_data->hdq_base = res->start;
 593
 594         /* get interface & functional clock objects */
 595         hdq_data->hdq_ick = clk_get(&pdev->dev, "hdq_ick");
 596         hdq_data->hdq_fck = clk_get(&pdev->dev, "hdq_fck");
 597
 598         if (IS_ERR(hdq_data->hdq_ick) || IS_ERR(hdq_data->hdq_fck)) {
 599                 dev_dbg(&pdev->dev, "Can't get HDQ clock objects\n");
 600                 if (IS_ERR(hdq_data->hdq_ick)) {
 601                         ret = PTR_ERR(hdq_data->hdq_ick);
 602                         goto err_clk;
 603                 }
 604                 if (IS_ERR(hdq_data->hdq_fck)) {
 605                         ret = PTR_ERR(hdq_data->hdq_fck);
 606                         clk_put(hdq_data->hdq_ick);
 607                         goto err_clk;
 608                 }
 609         }
 610
 611         hdq_data->hdq_usecount = 0;
 612         sema_init(&hdq_data->hdq_semlock, 1);
 613
 614         if (clk_enable(hdq_data->hdq_ick)) {
 615                 dev_dbg(&pdev->dev, "Can not enable ick\n");
 616                 ret = -ENODEV;
 617                 goto err_ick;
 618         }
 619
 620         if (clk_enable(hdq_data->hdq_fck)) {
 621                 dev_dbg(&pdev->dev, "Can not enable fck\n");
 622                 ret = -ENODEV;
 623                 goto err_fck;
 624         }
 625
 626         rev = hdq_reg_in(hdq_data, OMAP_HDQ_REVISION);
 627         dev_info(&pdev->dev, "OMAP HDQ Hardware Rev %c.%c. Driver in %s mode\n",
 628                 (rev >> 4) + '0', (rev & 0x0f) + '0', "Interrupt");
 629
 630         spin_lock_init(&hdq_data->hdq_spinlock);
 631         omap_hdq_break(hdq_data);
 632
 633         irq = platform_get_irq(pdev, 0);
 634         if (irq < 0) {
 635                 ret = -ENXIO;
 636                 goto err_irq;
 637         }
 638
 639         ret = request_irq(irq, hdq_isr, IRQF_DISABLED, "omap_hdq", hdq_data);
 640         if (ret < 0) {
 641                 dev_dbg(&pdev->dev, "could not request irq\n");
 642                 goto err_irq;
 643         }
 644
 645         /* don't clock the HDQ until it is needed */
 646         clk_disable(hdq_data->hdq_ick);
 647         clk_disable(hdq_data->hdq_fck);
 648
 649         omap_w1_master.data = hdq_data;
 650
 651         ret = w1_add_master_device(&omap_w1_master);
 652         if (ret) {
 653                 dev_dbg(&pdev->dev, "Failure in registering w1 master\n");
 654                 goto err_w1;
 655         }
 656
 657         return 0;
 658
 659 err_w1:
 660 err_irq:
 661         clk_disable(hdq_data->hdq_fck);
 662
 663 err_fck:
 664         clk_disable(hdq_data->hdq_ick);
 665
 666 err_ick:
 667         clk_put(hdq_data->hdq_ick);
 668         clk_put(hdq_data->hdq_fck);
 669
 670 err_clk:
 671         hdq_data->hdq_base = NULL;
 672
 673 err_resource:
 674         platform_set_drvdata(pdev, NULL);
 675         kfree(hdq_data);
 676
 677 err_kmalloc:
 678         return ret;
 679
 680 }
 681
 682 static int omap_hdq_remove(struct platform_device *pdev)
 683 {
 684         struct hdq_data *hdq_data = platform_get_drvdata(pdev);
 685
 686         down_interruptible(&hdq_data->hdq_semlock);
 687         if (0 != hdq_data->hdq_usecount) {
 688                 dev_dbg(&pdev->dev, "removed when use count is not zero\n");
 689                 return -EBUSY;
 690         }
 691         up(&hdq_data->hdq_semlock);
 692
 693         /* remove module dependency */
 694         clk_put(hdq_data->hdq_ick);
 695         clk_put(hdq_data->hdq_fck);
 696         free_irq(INT_24XX_HDQ_IRQ, hdq_data);
 697         platform_set_drvdata(pdev, NULL);
 698         kfree(hdq_data);
 699
 700         return 0;
 701 }
 702
 703 static int __init
 704 omap_hdq_init(void)
 705 {
 706         return platform_driver_register(&omap_hdq_driver);
 707 }
 708
 709 static void __exit
 710 omap_hdq_exit(void)
 711 {
 712         platform_driver_unregister(&omap_hdq_driver);
 713 }
 714
 715 module_init(omap_hdq_init);
 716 module_exit(omap_hdq_exit);
 717
 718 module_param(W1_ID, int, S_IRUSR);
 719
 720 MODULE_AUTHOR("Texas Instruments");
 721 MODULE_DESCRIPTION("HDQ driver Library");
 722 MODULE_LICENSE("GPL");