drivers/w1/masters/omap_hdq.c

   1 /*
   2  * drivers/w1/masters/omap_hdq.c
   3  *
   4  * Copyright (C) 2007 Texas Instruments, Inc.
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2. This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  *
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/err.h>
  16 #include <linux/clk.h>
  17 #include <linux/io.h>
  18 #include <asm/irq.h>
  19 #include <asm/hardware.h>
  20
  21 #include "../w1.h"
  22 #include "../w1_int.h"
  23
  24 #define MOD_NAME        "OMAP_HDQ:"
  25
  26 #define OMAP_HDQ_REVISION                       0x00
  27 #define OMAP_HDQ_TX_DATA                        0x04
  28 #define OMAP_HDQ_RX_DATA                        0x08
  29 #define OMAP_HDQ_CTRL_STATUS                    0x0c
  30 #define OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK      (1<<6)
  31 #define OMAP_HDQ_CTRL_STATUS_CLOCKENABLE        (1<<5)
  32 #define OMAP_HDQ_CTRL_STATUS_GO                 (1<<4)
  33 #define OMAP_HDQ_CTRL_STATUS_INITIALIZATION     (1<<2)
  34 #define OMAP_HDQ_CTRL_STATUS_DIR                (1<<1)
  35 #define OMAP_HDQ_CTRL_STATUS_MODE               (1<<0)
  36 #define OMAP_HDQ_INT_STATUS                     0x10
  37 #define OMAP_HDQ_INT_STATUS_TXCOMPLETE          (1<<2)
  38 #define OMAP_HDQ_INT_STATUS_RXCOMPLETE          (1<<1)
  39 #define OMAP_HDQ_INT_STATUS_TIMEOUT             (1<<0)
  40 #define OMAP_HDQ_SYSCONFIG                      0x14
  41 #define OMAP_HDQ_SYSCONFIG_SOFTRESET            (1<<1)
  42 #define OMAP_HDQ_SYSCONFIG_AUTOIDLE             (1<<0)
  43 #define OMAP_HDQ_SYSSTATUS                      0x18
  44 #define OMAP_HDQ_SYSSTATUS_RESETDONE            (1<<0)
  45
  46 #define OMAP_HDQ_FLAG_CLEAR                     0
  47 #define OMAP_HDQ_FLAG_SET                       1
  48 #define OMAP_HDQ_TIMEOUT                        (HZ/5)
  49
  50 #define OMAP_HDQ_MAX_USER                       4
  51
  52 DECLARE_WAIT_QUEUE_HEAD(hdq_wait_queue);
  53 int W1_ID;
  54
  55 struct hdq_data {
  56         resource_size_t         hdq_base;
  57         struct  semaphore       hdq_semlock;
  58         int                     hdq_usecount;
  59         struct  clk             *hdq_ick;
  60         struct  clk             *hdq_fck;
  61         u8                      hdq_irqstatus;
  62         spinlock_t              hdq_spinlock;
  63 };
  64
  65 static struct hdq_data *hdq_data;
  66
  67 static int omap_hdq_get(void);
  68 static int omap_hdq_put(void);
  69 static int omap_hdq_break(void);
  70
  71 static int __init omap_hdq_probe(struct platform_device *pdev);
  72 static int omap_hdq_remove(struct platform_device *pdev);
  73
  74 static struct platform_driver omap_hdq_driver = {
  75         .probe = omap_hdq_probe,
  76         .remove = omap_hdq_remove,
  77         .suspend = NULL,
  78         .resume = NULL,
  79         .driver = {
  80                 .name = "omap_hdq",
  81         },
  82 };
  83
  84 static u8 omap_w1_read_byte(void *data);
  85 static void omap_w1_write_byte(void *data, u8 byte);
  86 static u8 omap_w1_reset_bus(void *data);
  87 static void omap_w1_search_bus(void *data, u8 search_type,
  88         w1_slave_found_callback slave_found);
  89
  90 static struct w1_bus_master omap_w1_master = {
  91         .read_byte      = omap_w1_read_byte,
  92         .write_byte     = omap_w1_write_byte,
  93         .reset_bus      = omap_w1_reset_bus,
  94         .search         = omap_w1_search_bus,
  95 };
  96
  97 /*
  98  * HDQ register I/O routines
  99  */
 100 static inline u8
 101 hdq_reg_in(u32 offset)
 102 {
 103         return omap_readb(hdq_data->hdq_base + offset);
 104 }
 105
 106 static inline u8
 107 hdq_reg_out(u32 offset, u8 val)
 108 {
 109         omap_writeb(val, hdq_data->hdq_base + offset);
 110         return val;
 111 }
 112
 113 static inline u8
 114 hdq_reg_merge(u32 offset, u8 val, u8 mask)
 115 {
 116         u8 new_val = (omap_readb(hdq_data->hdq_base + offset) & ~mask)
 117                         | (val & mask);
 118         omap_writeb(new_val, hdq_data->hdq_base + offset);
 119         return new_val;
 120 }
 121
 122 /*
 123  * Wait for one or more bits in flag change.
 124  * HDQ_FLAG_SET: wait until any bit in the flag is set.
 125  * HDQ_FLAG_CLEAR: wait until all bits in the flag are cleared.
 126  * return 0 on success and -ETIMEDOUT in the case of timeout.
 127  */
 128 static int
 129 hdq_wait_for_flag(u32 offset, u8 flag, u8 flag_set, u8 *status)
 130 {
 131         int ret = 0;
 132         unsigned long timeout = jiffies + OMAP_HDQ_TIMEOUT;
 133
 134         if (flag_set == OMAP_HDQ_FLAG_CLEAR) {
 135                 /* wait for the flag clear */
 136                 while (((*status = hdq_reg_in(offset)) & flag)
 137                         && time_before(jiffies, timeout)) {
 138                         set_current_state(TASK_UNINTERRUPTIBLE);
 139                         schedule_timeout(1);
 140                 }
 141                 if (unlikely(*status & flag))
 142                         ret = -ETIMEDOUT;
 143         } else if (flag_set == OMAP_HDQ_FLAG_SET) {
 144                 /* wait for the flag set */
 145                 while (!((*status = hdq_reg_in(offset)) & flag)
 146                         && time_before(jiffies, timeout)) {
 147                         set_current_state(TASK_UNINTERRUPTIBLE);
 148                         schedule_timeout(1);
 149                 }
 150                 if (unlikely(!(*status & flag)))
 151                         ret = -ETIMEDOUT;
 152         } else
 153                 return -EINVAL;
 154
 155         return ret;
 156 }
 157
 158 /*
 159  * write out a byte and fill *status with HDQ_INT_STATUS
 160  */
 161 static int
 162 hdq_write_byte(u8 val, u8 *status)
 163 {
 164         int ret;
 165         u8 tmp_status;
 166         unsigned long irqflags;
 167
 168         *status = 0;
 169
 170         spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
 171         /* clear interrupt flags via a dummy read */
 172         hdq_reg_in(OMAP_HDQ_INT_STATUS);
 173         /* ISR loads it with new INT_STATUS */
 174         hdq_data->hdq_irqstatus = 0;
 175         spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
 176
 177         hdq_reg_out(OMAP_HDQ_TX_DATA, val);
 178
 179         /* set the GO bit */
 180         hdq_reg_merge(OMAP_HDQ_CTRL_STATUS, OMAP_HDQ_CTRL_STATUS_GO,
 181                 OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO);
 182         /* wait for the TXCOMPLETE bit */
 183         ret = wait_event_interruptible_timeout(hdq_wait_queue,
 184                 hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT);
 185         if (unlikely(ret < 0)) {
 186                 pr_debug("wait interrupted");
 187                 return -EINTR;
 188         }
 189
 190         spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
 191         *status = hdq_data->hdq_irqstatus;
 192         spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
 193         /* check irqstatus */
 194         if (!(*status & OMAP_HDQ_INT_STATUS_TXCOMPLETE)) {
 195                 pr_debug("timeout waiting for TXCOMPLETE/RXCOMPLETE, %x",
 196                         *status);
 197                 return -ETIMEDOUT;
 198         }
 199
 200         /* wait for the GO bit return to zero */
 201         ret = hdq_wait_for_flag(OMAP_HDQ_CTRL_STATUS, OMAP_HDQ_CTRL_STATUS_GO,
 202                 OMAP_HDQ_FLAG_CLEAR, &tmp_status);
 203         if (ret) {
 204                 pr_debug("timeout waiting GO bit return to zero, %x",
 205                         tmp_status);
 206                 return ret;
 207         }
 208
 209         return ret;
 210 }
 211
 212 /*
 213  * HDQ Interrupt service routine.
 214  */
 215 static irqreturn_t
 216 hdq_isr(int irq, void *arg)
 217 {
 218         unsigned long irqflags;
 219
 220         spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
 221         hdq_data->hdq_irqstatus = hdq_reg_in(OMAP_HDQ_INT_STATUS);
 222         spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
 223         pr_debug("hdq_isr: %x", hdq_data->hdq_irqstatus);
 224
 225         if (hdq_data->hdq_irqstatus &
 226                 (OMAP_HDQ_INT_STATUS_TXCOMPLETE | OMAP_HDQ_INT_STATUS_RXCOMPLETE
 227                 | OMAP_HDQ_INT_STATUS_TIMEOUT)) {
 228                 /* wake up sleeping process */
 229                 wake_up_interruptible(&hdq_wait_queue);
 230         }
 231
 232         return IRQ_HANDLED;
 233 }
 234
 235 /*
 236  * HDQ Mode: always return success.
 237  */
 238 static u8 omap_w1_reset_bus(void *data)
 239 {
 240         return 0;
 241 }
 242
 243 /*
 244  * W1 search callback function.
 245  */
 246 static void omap_w1_search_bus(void *data, u8 search_type,
 247         w1_slave_found_callback slave_found)
 248 {
 249         u64 module_id, rn_le, cs, id;
 250
 251         if (W1_ID)
 252                 module_id = W1_ID;
 253         else
 254                 module_id = 0x1;
 255
 256         rn_le = cpu_to_le64(module_id);
 257         /*
 258          * HDQ might not obey truly the 1-wire spec.
 259          * So calculate CRC based on module parameter.
 260          */
 261         cs = w1_calc_crc8((u8 *)&rn_le, 7);
 262         id = (cs << 56) | module_id;
 263
 264         slave_found(data, id);
 265 }
 266
 267 static int
 268 _omap_hdq_reset(void)
 269 {
 270         int ret;
 271         u8 tmp_status;
 272
 273         hdq_reg_out(OMAP_HDQ_SYSCONFIG, OMAP_HDQ_SYSCONFIG_SOFTRESET);
 274         /*
 275          * Select HDQ mode & enable clocks.
 276          * It is observed that INT flags can't be cleared via a read and GO/INIT
 277          * won't return to zero if interrupt is disabled. So we always enable
 278          * interrupt.
 279          */
 280         hdq_reg_out(OMAP_HDQ_CTRL_STATUS,
 281                 OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
 282                 OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
 283
 284         /* wait for reset to complete */
 285         ret = hdq_wait_for_flag(OMAP_HDQ_SYSSTATUS,
 286                 OMAP_HDQ_SYSSTATUS_RESETDONE, OMAP_HDQ_FLAG_SET, &tmp_status);
 287         if (ret)
 288                 pr_debug("timeout waiting HDQ reset, %x", tmp_status);
 289         else {
 290                 hdq_reg_out(OMAP_HDQ_CTRL_STATUS,
 291                         OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
 292                         OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
 293                 hdq_reg_out(OMAP_HDQ_SYSCONFIG, OMAP_HDQ_SYSCONFIG_AUTOIDLE);
 294         }
 295
 296         return ret;
 297 }
 298
 299 /*
 300  * Issue break pulse to the device.
 301  */
 302 static int
 303 omap_hdq_break()
 304 {
 305         int ret;
 306         u8 tmp_status;
 307         unsigned long irqflags;
 308
 309         ret = down_interruptible(&hdq_data->hdq_semlock);
 310         if (ret < 0)
 311                 return -EINTR;
 312
 313         if (!hdq_data->hdq_usecount) {
 314                 up(&hdq_data->hdq_semlock);
 315                 return -EINVAL;
 316         }
 317
 318         spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
 319         /* clear interrupt flags via a dummy read */
 320         hdq_reg_in(OMAP_HDQ_INT_STATUS);
 321         /* ISR loads it with new INT_STATUS */
 322         hdq_data->hdq_irqstatus = 0;
 323         spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
 324
 325         /* set the INIT and GO bit */
 326         hdq_reg_merge(OMAP_HDQ_CTRL_STATUS,
 327                 OMAP_HDQ_CTRL_STATUS_INITIALIZATION | OMAP_HDQ_CTRL_STATUS_GO,
 328                 OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_INITIALIZATION |
 329                 OMAP_HDQ_CTRL_STATUS_GO);
 330
 331         /* wait for the TIMEOUT bit */
 332         ret = wait_event_interruptible_timeout(hdq_wait_queue,
 333                 hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT);
 334         if (unlikely(ret < 0)) {
 335                 pr_debug("wait interrupted");
 336                 up(&hdq_data->hdq_semlock);
 337                 return -EINTR;
 338         }
 339
 340         spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
 341         tmp_status = hdq_data->hdq_irqstatus;
 342         spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
 343         /* check irqstatus */
 344         if (!(tmp_status & OMAP_HDQ_INT_STATUS_TIMEOUT)) {
 345                 pr_debug("timeout waiting for TIMEOUT, %x", tmp_status);
 346                 up(&hdq_data->hdq_semlock);
 347                 return -ETIMEDOUT;
 348         }
 349         /*
 350          * wait for both INIT and GO bits rerurn to zero.
 351          * zero wait time expected for interrupt mode.
 352          */
 353         ret = hdq_wait_for_flag(OMAP_HDQ_CTRL_STATUS,
 354                         OMAP_HDQ_CTRL_STATUS_INITIALIZATION |
 355                         OMAP_HDQ_CTRL_STATUS_GO, OMAP_HDQ_FLAG_CLEAR,
 356                         &tmp_status);
 357         if (ret)
 358                 pr_debug("timeout waiting INIT&GO bits return to zero, %x",
 359                         tmp_status);
 360
 361         up(&hdq_data->hdq_semlock);
 362         return ret;
 363 }
 364
 365 static int hdq_read_byte(u8 *val)
 366 {
 367         int ret;
 368         u8 status;
 369         unsigned long irqflags;
 370
 371         ret = down_interruptible(&hdq_data->hdq_semlock);
 372         if (ret < 0)
 373                 return -EINTR;
 374
 375         if (!hdq_data->hdq_usecount) {
 376                 up(&hdq_data->hdq_semlock);
 377                 return -EINVAL;
 378         }
 379
 380         if (!(hdq_data->hdq_irqstatus & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) {
 381                 hdq_reg_merge(OMAP_HDQ_CTRL_STATUS,
 382                         OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO,
 383                         OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO);
 384                 /*
 385                  * The RX comes immediately after TX. It
 386                  * triggers another interrupt before we
 387                  * sleep. So we have to wait for RXCOMPLETE bit.
 388                  */
 389                 {
 390                         unsigned long timeout = jiffies + OMAP_HDQ_TIMEOUT;
 391                         while (!(hdq_data->hdq_irqstatus
 392                                 & OMAP_HDQ_INT_STATUS_RXCOMPLETE)
 393                                 && time_before(jiffies, timeout)) {
 394                                 set_current_state(TASK_UNINTERRUPTIBLE);
 395                                 schedule_timeout(1);
 396                         }
 397                 }
 398                 hdq_reg_merge(OMAP_HDQ_CTRL_STATUS, 0,
 399                         OMAP_HDQ_CTRL_STATUS_DIR);
 400                 spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
 401                 status = hdq_data->hdq_irqstatus;
 402                 spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
 403                 /* check irqstatus */
 404                 if (!(status & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) {
 405                         pr_debug("timeout waiting for RXCOMPLETE, %x", status);
 406                         up(&hdq_data->hdq_semlock);
 407                         return -ETIMEDOUT;
 408                 }
 409         }
 410         /* the data is ready. Read it in! */
 411         *val = hdq_reg_in(OMAP_HDQ_RX_DATA);
 412         up(&hdq_data->hdq_semlock);
 413
 414         return 0;
 415
 416 }
 417
 418 /*
 419  * Enable clocks and set the controller to HDQ mode.
 420  */
 421 static int
 422 omap_hdq_get()
 423 {
 424         int ret = 0;
 425
 426         ret = down_interruptible(&hdq_data->hdq_semlock);
 427         if (ret < 0)
 428                 return -EINTR;
 429
 430         if (OMAP_HDQ_MAX_USER == hdq_data->hdq_usecount) {
 431                 pr_debug("attempt to exceed the max use count");
 432                 up(&hdq_data->hdq_semlock);
 433                 ret = -EINVAL;
 434         } else {
 435                 hdq_data->hdq_usecount++;
 436                 try_module_get(THIS_MODULE);
 437                 if (1 == hdq_data->hdq_usecount) {
 438                         if (clk_enable(hdq_data->hdq_ick)) {
 439                                 pr_debug("Can not enable ick\n");
 440                                 clk_put(hdq_data->hdq_ick);
 441                                 clk_put(hdq_data->hdq_fck);
 442                                 up(&hdq_data->hdq_semlock);
 443                                 return -ENODEV;
 444                         }
 445                         if (clk_enable(hdq_data->hdq_fck)) {
 446                                 pr_debug("Can not enable fck\n");
 447                                 clk_put(hdq_data->hdq_ick);
 448                                 clk_put(hdq_data->hdq_fck);
 449                                 up(&hdq_data->hdq_semlock);
 450                                 return -ENODEV;
 451                         }
 452
 453                         /* make sure HDQ is out of reset */
 454                         if (!(hdq_reg_in(OMAP_HDQ_SYSSTATUS) &
 455                                 OMAP_HDQ_SYSSTATUS_RESETDONE)) {
 456                                 ret = _omap_hdq_reset();
 457                                 if (ret)
 458                                         /* back up the count */
 459                                         hdq_data->hdq_usecount--;
 460                         } else {
 461                                 /* select HDQ mode & enable clocks */
 462                                 hdq_reg_out(OMAP_HDQ_CTRL_STATUS,
 463                                         OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
 464                                         OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
 465                                 hdq_reg_out(OMAP_HDQ_SYSCONFIG,
 466                                         OMAP_HDQ_SYSCONFIG_AUTOIDLE);
 467                                 hdq_reg_in(OMAP_HDQ_INT_STATUS);
 468                         }
 469                 }
 470         }
 471         up(&hdq_data->hdq_semlock);
 472         return ret;
 473 }
 474
 475 /*
 476  * Disable clocks to the module.
 477  */
 478 static int
 479 omap_hdq_put()
 480 {
 481         int ret = 0;
 482
 483         ret = down_interruptible(&hdq_data->hdq_semlock);
 484         if (ret < 0)
 485                 return -EINTR;
 486
 487         if (0 == hdq_data->hdq_usecount) {
 488                 pr_debug("attempt to decrement use count when it is zero");
 489                 ret = -EINVAL;
 490         } else {
 491                 hdq_data->hdq_usecount--;
 492                 module_put(THIS_MODULE);
 493                 if (0 == hdq_data->hdq_usecount) {
 494                         clk_disable(hdq_data->hdq_ick);
 495                         clk_disable(hdq_data->hdq_fck);
 496                 }
 497         }
 498         up(&hdq_data->hdq_semlock);
 499         return ret;
 500 }
 501
 502 /*
 503  * Used to control the call to omap_hdq_get and omap_hdq_put.
 504  * HDQ Protocol: Write the CMD|REG_address first, followed by
 505  * the data wrire or read.
 506  */
 507 static int init_trans;
 508
 509 /*
 510  * Read a byte of data from the device.
 511  */
 512 static u8 omap_w1_read_byte(void *data)
 513 {
 514         u8 val;
 515         int ret;
 516
 517         ret = hdq_read_byte(&val);
 518         if (ret) {
 519                 init_trans = 0;
 520                 omap_hdq_put();
 521                 return -1;
 522         }
 523
 524         /* Write followed by a read, release the module */
 525         if (init_trans) {
 526                 init_trans = 0;
 527                 omap_hdq_put();
 528         }
 529
 530         return val;
 531 }
 532
 533 /*
 534  * Write a byte of data to the device.
 535  */
 536 static void omap_w1_write_byte(void *data, u8 byte)
 537 {
 538         u8 status;
 539
 540         /* First write to initialize the transfer */
 541         if (init_trans == 0)
 542                 omap_hdq_get();
 543
 544         init_trans++;
 545
 546         hdq_write_byte(byte, &status);
 547         pr_debug("Ctrl status %x\n", status);
 548
 549         /* Second write, data transfered. Release the module */
 550         if (init_trans > 1) {
 551                 omap_hdq_put();
 552                 init_trans = 0;
 553         }
 554
 555         return;
 556 }
 557
 558 static int __init omap_hdq_probe(struct platform_device *pdev)
 559 {
 560         struct resource *res;
 561         int ret, irq;
 562         u8 rev;
 563
 564         if (!pdev)
 565                 return -ENODEV;
 566
 567         hdq_data = kmalloc(sizeof(*hdq_data), GFP_KERNEL);
 568         if (!hdq_data)
 569                 return -ENODEV;
 570
 571         platform_set_drvdata(pdev, hdq_data);
 572
 573         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 574         if (res == NULL) {
 575                 platform_set_drvdata(pdev, NULL);
 576                 kfree(hdq_data);
 577                 return -ENXIO;
 578         }
 579
 580         hdq_data->hdq_base = res->start;
 581
 582         /* get interface & functional clock objects */
 583         hdq_data->hdq_ick = clk_get(&pdev->dev, "hdq_ick");
 584         hdq_data->hdq_fck = clk_get(&pdev->dev, "hdq_fck");
 585
 586         if (IS_ERR(hdq_data->hdq_ick) || IS_ERR(hdq_data->hdq_fck)) {
 587                 pr_debug("Can't get HDQ clock objects\n");
 588                 if (IS_ERR(hdq_data->hdq_ick)) {
 589                         ret = PTR_ERR(hdq_data->hdq_ick);
 590                         platform_set_drvdata(pdev, NULL);
 591                         kfree(hdq_data);
 592                         return ret;
 593                 }
 594                 if (IS_ERR(hdq_data->hdq_fck)) {
 595                         ret = PTR_ERR(hdq_data->hdq_fck);
 596                         platform_set_drvdata(pdev, NULL);
 597                         kfree(hdq_data);
 598                         return ret;
 599                 }
 600         }
 601
 602         hdq_data->hdq_usecount = 0;
 603         sema_init(&hdq_data->hdq_semlock, 1);
 604
 605         if (clk_enable(hdq_data->hdq_ick)) {
 606                 pr_debug("Can not enable ick\n");
 607                 clk_put(hdq_data->hdq_ick);
 608                 clk_put(hdq_data->hdq_fck);
 609                 platform_set_drvdata(pdev, NULL);
 610                 kfree(hdq_data);
 611                 return -ENODEV;
 612         }
 613
 614         if (clk_enable(hdq_data->hdq_fck)) {
 615                 pr_debug("Can not enable fck\n");
 616                 clk_disable(hdq_data->hdq_ick);
 617                 clk_put(hdq_data->hdq_ick);
 618                 clk_put(hdq_data->hdq_fck);
 619                 platform_set_drvdata(pdev, NULL);
 620                 kfree(hdq_data);
 621                 return -ENODEV;
 622         }
 623
 624         rev = hdq_reg_in(OMAP_HDQ_REVISION);
 625         pr_info("OMAP HDQ Hardware Revision %c.%c. Driver in %s mode.\n",
 626                 (rev >> 4) + '0', (rev & 0x0f) + '0', "Interrupt");
 627
 628         spin_lock_init(&hdq_data->hdq_spinlock);
 629         omap_hdq_break();
 630
 631         irq = platform_get_irq(pdev, 0);
 632         if (irq < 0) {
 633                 platform_set_drvdata(pdev, NULL);
 634                 kfree(hdq_data);
 635                 return -ENXIO;
 636         }
 637
 638         if (request_irq(irq, hdq_isr, IRQF_DISABLED, "OMAP HDQ",
 639                 &hdq_data->hdq_semlock)) {
 640                 pr_debug("request_irq failed\n");
 641                 clk_disable(hdq_data->hdq_ick);
 642                 clk_put(hdq_data->hdq_ick);
 643                 clk_put(hdq_data->hdq_fck);
 644                 platform_set_drvdata(pdev, NULL);
 645                 kfree(hdq_data);
 646                 return -ENODEV;
 647         }
 648
 649         /* don't clock the HDQ until it is needed */
 650         clk_disable(hdq_data->hdq_ick);
 651         clk_disable(hdq_data->hdq_fck);
 652
 653         ret = w1_add_master_device(&omap_w1_master);
 654         if (ret) {
 655                 pr_debug("Failure in registering w1 master\n");
 656                 clk_put(hdq_data->hdq_ick);
 657                 clk_put(hdq_data->hdq_fck);
 658                 platform_set_drvdata(pdev, NULL);
 659                 kfree(hdq_data);
 660                 return ret;
 661         }
 662
 663         return 0;
 664 }
 665
 666 static int omap_hdq_remove(struct platform_device *pdev)
 667 {
 668         down_interruptible(&hdq_data->hdq_semlock);
 669         if (0 != hdq_data->hdq_usecount) {
 670                 pr_debug("removed when use count is not zero\n");
 671                 return -EBUSY;
 672         }
 673         up(&hdq_data->hdq_semlock);
 674
 675         /* remove module dependency */
 676         clk_put(hdq_data->hdq_ick);
 677         clk_put(hdq_data->hdq_fck);
 678         free_irq(INT_24XX_HDQ_IRQ, &hdq_data->hdq_semlock);
 679         platform_set_drvdata(pdev, NULL);
 680         kfree(hdq_data);
 681
 682         return 0;
 683 }
 684
 685 static int __init
 686 omap_hdq_init(void)
 687 {
 688         return platform_driver_register(&omap_hdq_driver);
 689 }
 690
 691 static void __exit
 692 omap_hdq_exit(void)
 693 {
 694         platform_driver_unregister(&omap_hdq_driver);
 695 }
 696
 697 module_init(omap_hdq_init);
 698 module_exit(omap_hdq_exit);
 699
 700 module_param(W1_ID, int, S_IRUSR);
 701
 702 MODULE_AUTHOR("Texas Instruments");
 703 MODULE_DESCRIPTION("HDQ driver Library");
 704 MODULE_LICENSE("GPL");