drivers/w1/masters/omap_hdq.c

   1 /*
   2  * drivers/w1/masters/omap_hdq.c
   3  *
   4  * Copyright (C) 2007 Texas Instruments, Inc.
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2. This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  *
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/err.h>
  16 #include <linux/clk.h>
  17 #include <linux/io.h>
  18 #include <asm/irq.h>
  19 #include <mach/hardware.h>
  20
  21 #include "../w1.h"
  22 #include "../w1_int.h"
  23
  24 #define MOD_NAME        "OMAP_HDQ:"
  25
  26 #define OMAP_HDQ_REVISION                       0x00
  27 #define OMAP_HDQ_TX_DATA                        0x04
  28 #define OMAP_HDQ_RX_DATA                        0x08
  29 #define OMAP_HDQ_CTRL_STATUS                    0x0c
  30 #define OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK      (1<<6)
  31 #define OMAP_HDQ_CTRL_STATUS_CLOCKENABLE        (1<<5)
  32 #define OMAP_HDQ_CTRL_STATUS_GO                 (1<<4)
  33 #define OMAP_HDQ_CTRL_STATUS_INITIALIZATION     (1<<2)
  34 #define OMAP_HDQ_CTRL_STATUS_DIR                (1<<1)
  35 #define OMAP_HDQ_CTRL_STATUS_MODE               (1<<0)
  36 #define OMAP_HDQ_INT_STATUS                     0x10
  37 #define OMAP_HDQ_INT_STATUS_TXCOMPLETE          (1<<2)
  38 #define OMAP_HDQ_INT_STATUS_RXCOMPLETE          (1<<1)
  39 #define OMAP_HDQ_INT_STATUS_TIMEOUT             (1<<0)
  40 #define OMAP_HDQ_SYSCONFIG                      0x14
  41 #define OMAP_HDQ_SYSCONFIG_SOFTRESET            (1<<1)
  42 #define OMAP_HDQ_SYSCONFIG_AUTOIDLE             (1<<0)
  43 #define OMAP_HDQ_SYSSTATUS                      0x18
  44 #define OMAP_HDQ_SYSSTATUS_RESETDONE            (1<<0)
  45
  46 #define OMAP_HDQ_FLAG_CLEAR                     0
  47 #define OMAP_HDQ_FLAG_SET                       1
  48 #define OMAP_HDQ_TIMEOUT                        (HZ/5)
  49
  50 #define OMAP_HDQ_MAX_USER                       4
  51
  52 static DECLARE_WAIT_QUEUE_HEAD(hdq_wait_queue);
  53 static int w1_id;
  54
  55 struct hdq_data {
  56         struct device           *dev;
  57         void __iomem            *hdq_base;
  58         /* lock status update */
  59         struct  mutex           hdq_mutex;
  60         int                     hdq_usecount;
  61         struct  clk             *hdq_ick;
  62         struct  clk             *hdq_fck;
  63         u8                      hdq_irqstatus;
  64         /* device lock */
  65         spinlock_t              hdq_spinlock;
  66         /*
  67          * Used to control the call to omap_hdq_get and omap_hdq_put.
  68          * HDQ Protocol: Write the CMD|REG_address first, followed by
  69          * the data wrire or read.
  70          */
  71         int                     init_trans;
  72 };
  73
  74 static int omap_hdq_get(struct hdq_data *hdq_data);
  75 static int omap_hdq_put(struct hdq_data *hdq_data);
  76 static int omap_hdq_break(struct hdq_data *hdq_data);
  77
  78 static int __init omap_hdq_probe(struct platform_device *pdev);
  79 static int omap_hdq_remove(struct platform_device *pdev);
  80
  81 static struct platform_driver omap_hdq_driver = {
  82         .probe =        omap_hdq_probe,
  83         .remove =       omap_hdq_remove,
  84         .driver =       {
  85                 .name = "omap_hdq",
  86         },
  87 };
  88
  89 static u8 omap_w1_read_byte(void *_hdq);
  90 static void omap_w1_write_byte(void *_hdq, u8 byte);
  91 static u8 omap_w1_reset_bus(void *_hdq);
  92 static void omap_w1_search_bus(void *_hdq, struct w1_master *master_dev,
  93                 u8 search_type, w1_slave_found_callback slave_found);
  94
  95
  96 static struct w1_bus_master omap_w1_master = {
  97         .read_byte      = omap_w1_read_byte,
  98         .write_byte     = omap_w1_write_byte,
  99         .reset_bus      = omap_w1_reset_bus,
 100         .search         = omap_w1_search_bus,
 101 };
 102
 103 /* HDQ register I/O routines */
 104 static inline u8 hdq_reg_in(struct hdq_data *hdq_data, u32 offset)
 105 {
 106         return __raw_readb(hdq_data->hdq_base + offset);
 107 }
 108
 109 static inline void hdq_reg_out(struct hdq_data *hdq_data, u32 offset, u8 val)
 110 {
 111         __raw_writeb(val, hdq_data->hdq_base + offset);
 112 }
 113
 114 static inline u8 hdq_reg_merge(struct hdq_data *hdq_data, u32 offset,
 115                         u8 val, u8 mask)
 116 {
 117         u8 new_val = (__raw_readb(hdq_data->hdq_base + offset) & ~mask)
 118                         | (val & mask);
 119         __raw_writeb(new_val, hdq_data->hdq_base + offset);
 120
 121         return new_val;
 122 }
 123
 124 /*
 125  * Wait for one or more bits in flag change.
 126  * HDQ_FLAG_SET: wait until any bit in the flag is set.
 127  * HDQ_FLAG_CLEAR: wait until all bits in the flag are cleared.
 128  * return 0 on success and -ETIMEDOUT in the case of timeout.
 129  */
 130 static int hdq_wait_for_flag(struct hdq_data *hdq_data, u32 offset,
 131                 u8 flag, u8 flag_set, u8 *status)
 132 {
 133         int ret = 0;
 134         unsigned long timeout = jiffies + OMAP_HDQ_TIMEOUT;
 135
 136         if (flag_set == OMAP_HDQ_FLAG_CLEAR) {
 137                 /* wait for the flag clear */
 138                 while (((*status = hdq_reg_in(hdq_data, offset)) & flag)
 139                         && time_before(jiffies, timeout)) {
 140                         set_current_state(TASK_UNINTERRUPTIBLE);
 141                         schedule_timeout(1);
 142                 }
 143                 if (*status & flag)
 144                         ret = -ETIMEDOUT;
 145         } else if (flag_set == OMAP_HDQ_FLAG_SET) {
 146                 /* wait for the flag set */
 147                 while (!((*status = hdq_reg_in(hdq_data, offset)) & flag)
 148                         && time_before(jiffies, timeout)) {
 149                         set_current_state(TASK_UNINTERRUPTIBLE);
 150                         schedule_timeout(1);
 151                 }
 152                 if (!(*status & flag))
 153                         ret = -ETIMEDOUT;
 154         } else
 155                 return -EINVAL;
 156
 157         return ret;
 158 }
 159
 160 /* write out a byte and fill *status with HDQ_INT_STATUS */
 161 static int hdq_write_byte(struct hdq_data *hdq_data, u8 val, u8 *status)
 162 {
 163         int ret;
 164         u8 tmp_status;
 165         unsigned long irqflags;
 166
 167         *status = 0;
 168
 169         spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
 170         /* clear interrupt flags via a dummy read */
 171         hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
 172         /* ISR loads it with new INT_STATUS */
 173         hdq_data->hdq_irqstatus = 0;
 174         spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
 175
 176         hdq_reg_out(hdq_data, OMAP_HDQ_TX_DATA, val);
 177
 178         /* set the GO bit */
 179         hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, OMAP_HDQ_CTRL_STATUS_GO,
 180                 OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO);
 181         /* wait for the TXCOMPLETE bit */
 182         ret = wait_event_interruptible_timeout(hdq_wait_queue,
 183                 hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT);
 184         if (ret < 0) {
 185                 dev_dbg(hdq_data->dev, "wait interrupted");
 186                 return -EINTR;
 187         }
 188
 189         spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
 190         *status = hdq_data->hdq_irqstatus;
 191         spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
 192         /* check irqstatus */
 193         if (!(*status & OMAP_HDQ_INT_STATUS_TXCOMPLETE)) {
 194                 dev_dbg(hdq_data->dev, "timeout waiting for"
 195                         "TXCOMPLETE/RXCOMPLETE, %x", *status);
 196                 return -ETIMEDOUT;
 197         }
 198
 199         /* wait for the GO bit return to zero */
 200         ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_CTRL_STATUS,
 201                         OMAP_HDQ_CTRL_STATUS_GO,
 202                         OMAP_HDQ_FLAG_CLEAR, &tmp_status);
 203         if (ret) {
 204                 dev_dbg(hdq_data->dev, "timeout waiting GO bit"
 205                         "return to zero, %x", tmp_status);
 206                 return ret;
 207         }
 208
 209         return ret;
 210 }
 211
 212 /* HDQ Interrupt service routine */
 213 static irqreturn_t hdq_isr(int irq, void *_hdq)
 214 {
 215         struct hdq_data *hdq_data = _hdq;
 216         unsigned long irqflags;
 217
 218         spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
 219         hdq_data->hdq_irqstatus = hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
 220         spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
 221         dev_dbg(hdq_data->dev, "hdq_isr: %x", hdq_data->hdq_irqstatus);
 222
 223         if (hdq_data->hdq_irqstatus &
 224                 (OMAP_HDQ_INT_STATUS_TXCOMPLETE | OMAP_HDQ_INT_STATUS_RXCOMPLETE
 225                 | OMAP_HDQ_INT_STATUS_TIMEOUT)) {
 226                 /* wake up sleeping process */
 227                 wake_up_interruptible(&hdq_wait_queue);
 228         }
 229
 230         return IRQ_HANDLED;
 231 }
 232
 233 /* HDQ Mode: always return success */
 234 static u8 omap_w1_reset_bus(void *_hdq)
 235 {
 236         return 0;
 237 }
 238
 239 /* W1 search callback function */
 240 static void omap_w1_search_bus(void *_hdq, struct w1_master *master_dev,
 241                 u8 search_type, w1_slave_found_callback slave_found)
 242 {
 243         u64 module_id, rn_le, cs, id;
 244
 245         if (w1_id)
 246                 module_id = w1_id;
 247         else
 248                 module_id = 0x1;
 249
 250         rn_le = cpu_to_le64(module_id);
 251         /*
 252          * HDQ might not obey truly the 1-wire spec.
 253          * So calculate CRC based on module parameter.
 254          */
 255         cs = w1_calc_crc8((u8 *)&rn_le, 7);
 256         id = (cs << 56) | module_id;
 257
 258         slave_found(master_dev, id);
 259 }
 260
 261 static int _omap_hdq_reset(struct hdq_data *hdq_data)
 262 {
 263         int ret;
 264         u8 tmp_status;
 265
 266         hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG, OMAP_HDQ_SYSCONFIG_SOFTRESET);
 267         /*
 268          * Select HDQ mode & enable clocks.
 269          * It is observed that INT flags can't be cleared via a read and GO/INIT
 270          * won't return to zero if interrupt is disabled. So we always enable
 271          * interrupt.
 272          */
 273         hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
 274                 OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
 275                 OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
 276
 277         /* wait for reset to complete */
 278         ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_SYSSTATUS,
 279                 OMAP_HDQ_SYSSTATUS_RESETDONE, OMAP_HDQ_FLAG_SET, &tmp_status);
 280         if (ret)
 281                 dev_dbg(hdq_data->dev, "timeout waiting HDQ reset, %x",
 282                                 tmp_status);
 283         else {
 284                 hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
 285                         OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
 286                         OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
 287                 hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG,
 288                         OMAP_HDQ_SYSCONFIG_AUTOIDLE);
 289         }
 290
 291         return ret;
 292 }
 293
 294 /* Issue break pulse to the device */
 295 static int omap_hdq_break(struct hdq_data *hdq_data)
 296 {
 297         int ret;
 298         u8 tmp_status;
 299         unsigned long irqflags;
 300
 301         ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
 302         if (ret < 0)
 303                 return -EINTR;
 304
 305         if (!hdq_data->hdq_usecount) {
 306                 mutex_unlock(&hdq_data->hdq_mutex);
 307                 return -EINVAL;
 308         }
 309
 310         spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
 311         /* clear interrupt flags via a dummy read */
 312         hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
 313         /* ISR loads it with new INT_STATUS */
 314         hdq_data->hdq_irqstatus = 0;
 315         spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
 316
 317         /* set the INIT and GO bit */
 318         hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS,
 319                 OMAP_HDQ_CTRL_STATUS_INITIALIZATION | OMAP_HDQ_CTRL_STATUS_GO,
 320                 OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_INITIALIZATION |
 321                 OMAP_HDQ_CTRL_STATUS_GO);
 322
 323         /* wait for the TIMEOUT bit */
 324         ret = wait_event_interruptible_timeout(hdq_wait_queue,
 325                 hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT);
 326         if (ret < 0) {
 327                 dev_dbg(hdq_data->dev, "wait interrupted");
 328                 mutex_unlock(&hdq_data->hdq_mutex);
 329                 return -EINTR;
 330         }
 331
 332         spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
 333         tmp_status = hdq_data->hdq_irqstatus;
 334         spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
 335         /* check irqstatus */
 336         if (!(tmp_status & OMAP_HDQ_INT_STATUS_TIMEOUT)) {
 337                 dev_dbg(hdq_data->dev, "timeout waiting for TIMEOUT, %x",
 338                                 tmp_status);
 339                 mutex_unlock(&hdq_data->hdq_mutex);
 340                 return -ETIMEDOUT;
 341         }
 342         /*
 343          * wait for both INIT and GO bits rerurn to zero.
 344          * zero wait time expected for interrupt mode.
 345          */
 346         ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_CTRL_STATUS,
 347                         OMAP_HDQ_CTRL_STATUS_INITIALIZATION |
 348                         OMAP_HDQ_CTRL_STATUS_GO, OMAP_HDQ_FLAG_CLEAR,
 349                         &tmp_status);
 350         if (ret)
 351                 dev_dbg(hdq_data->dev, "timeout waiting INIT&GO bits"
 352                         "return to zero, %x", tmp_status);
 353
 354         mutex_unlock(&hdq_data->hdq_mutex);
 355
 356         return ret;
 357 }
 358
 359 static int hdq_read_byte(struct hdq_data *hdq_data, u8 *val)
 360 {
 361         int ret;
 362         u8 status;
 363         unsigned long irqflags;
 364         unsigned long timeout = jiffies + OMAP_HDQ_TIMEOUT;
 365
 366         ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
 367         if (ret < 0)
 368                 return -EINTR;
 369
 370         if (!hdq_data->hdq_usecount) {
 371                 mutex_unlock(&hdq_data->hdq_mutex);
 372                 return -EINVAL;
 373         }
 374
 375         if (!(hdq_data->hdq_irqstatus & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) {
 376                 hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS,
 377                         OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO,
 378                         OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO);
 379                 /*
 380                  * The RX comes immediately after TX. It
 381                  * triggers another interrupt before we
 382                  * sleep. So we have to wait for RXCOMPLETE bit.
 383                  */
 384                 while (!(hdq_data->hdq_irqstatus
 385                         & OMAP_HDQ_INT_STATUS_RXCOMPLETE)
 386                         && time_before(jiffies, timeout)) {
 387                         set_current_state(TASK_UNINTERRUPTIBLE);
 388                         schedule_timeout(1);
 389                 }
 390                 hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, 0,
 391                         OMAP_HDQ_CTRL_STATUS_DIR);
 392                 spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
 393                 status = hdq_data->hdq_irqstatus;
 394                 spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
 395                 /* check irqstatus */
 396                 if (!(status & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) {
 397                         dev_dbg(hdq_data->dev, "timeout waiting for"
 398                                 "RXCOMPLETE, %x", status);
 399                         mutex_unlock(&hdq_data->hdq_mutex);
 400                         return -ETIMEDOUT;
 401                 }
 402         }
 403         /* the data is ready. Read it in! */
 404         *val = hdq_reg_in(hdq_data, OMAP_HDQ_RX_DATA);
 405         mutex_unlock(&hdq_data->hdq_mutex);
 406
 407         return 0;
 408
 409 }
 410
 411 /* Enable clocks and set the controller to HDQ mode */
 412 static int omap_hdq_get(struct hdq_data *hdq_data)
 413 {
 414         int ret = 0;
 415
 416         ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
 417         if (ret < 0)
 418                 return -EINTR;
 419
 420         if (OMAP_HDQ_MAX_USER == hdq_data->hdq_usecount) {
 421                 dev_dbg(hdq_data->dev, "attempt to exceed the max use count");
 422                 mutex_unlock(&hdq_data->hdq_mutex);
 423                 ret = -EINVAL;
 424         } else {
 425                 hdq_data->hdq_usecount++;
 426                 try_module_get(THIS_MODULE);
 427                 if (1 == hdq_data->hdq_usecount) {
 428                         if (clk_enable(hdq_data->hdq_ick)) {
 429                                 dev_dbg(hdq_data->dev, "Can not enable ick\n");
 430                                 clk_put(hdq_data->hdq_ick);
 431                                 clk_put(hdq_data->hdq_fck);
 432                                 mutex_unlock(&hdq_data->hdq_mutex);
 433                                 return -ENODEV;
 434                         }
 435                         if (clk_enable(hdq_data->hdq_fck)) {
 436                                 dev_dbg(hdq_data->dev, "Can not enable fck\n");
 437                                 clk_put(hdq_data->hdq_ick);
 438                                 clk_put(hdq_data->hdq_fck);
 439                                 mutex_unlock(&hdq_data->hdq_mutex);
 440                                 return -ENODEV;
 441                         }
 442
 443                         /* make sure HDQ is out of reset */
 444                         if (!(hdq_reg_in(hdq_data, OMAP_HDQ_SYSSTATUS) &
 445                                 OMAP_HDQ_SYSSTATUS_RESETDONE)) {
 446                                 ret = _omap_hdq_reset(hdq_data);
 447                                 if (ret)
 448                                         /* back up the count */
 449                                         hdq_data->hdq_usecount--;
 450                         } else {
 451                                 /* select HDQ mode & enable clocks */
 452                                 hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
 453                                         OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
 454                                         OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
 455                                 hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG,
 456                                         OMAP_HDQ_SYSCONFIG_AUTOIDLE);
 457                                 hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
 458                         }
 459                 }
 460         }
 461         mutex_unlock(&hdq_data->hdq_mutex);
 462
 463         return ret;
 464 }
 465
 466 /* Disable clocks to the module */
 467 static int omap_hdq_put(struct hdq_data *hdq_data)
 468 {
 469         int ret = 0;
 470
 471         ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
 472         if (ret < 0)
 473                 return -EINTR;
 474
 475         if (0 == hdq_data->hdq_usecount) {
 476                 dev_dbg(hdq_data->dev, "attempt to decrement use count"
 477                         "when it is zero");
 478                 ret = -EINVAL;
 479         } else {
 480                 hdq_data->hdq_usecount--;
 481                 module_put(THIS_MODULE);
 482                 if (0 == hdq_data->hdq_usecount) {
 483                         clk_disable(hdq_data->hdq_ick);
 484                         clk_disable(hdq_data->hdq_fck);
 485                 }
 486         }
 487         mutex_unlock(&hdq_data->hdq_mutex);
 488
 489         return ret;
 490 }
 491
 492 /* Read a byte of data from the device */
 493 static u8 omap_w1_read_byte(void *_hdq)
 494 {
 495         struct hdq_data *hdq_data = _hdq;
 496         u8 val;
 497         int ret;
 498
 499         ret = hdq_read_byte(hdq_data, &val);
 500         if (ret) {
 501                 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
 502                 if (ret < 0) {
 503                         dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
 504                         return -EINTR;
 505                 }
 506                 hdq_data->init_trans = 0;
 507                 mutex_unlock(&hdq_data->hdq_mutex);
 508                 omap_hdq_put(hdq_data);
 509                 return -1;
 510         }
 511
 512         /* Write followed by a read, release the module */
 513         if (hdq_data->init_trans) {
 514                 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
 515                 if (ret < 0) {
 516                         dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
 517                         return -EINTR;
 518                 }
 519                 hdq_data->init_trans = 0;
 520                 mutex_unlock(&hdq_data->hdq_mutex);
 521                 omap_hdq_put(hdq_data);
 522         }
 523
 524         return val;
 525 }
 526
 527 /* Write a byte of data to the device */
 528 static void omap_w1_write_byte(void *_hdq, u8 byte)
 529 {
 530         struct hdq_data *hdq_data = _hdq;
 531         int ret;
 532         u8 status;
 533
 534         /* First write to initialize the transfer */
 535         if (hdq_data->init_trans == 0)
 536                 omap_hdq_get(hdq_data);
 537
 538         ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
 539         if (ret < 0) {
 540                 dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
 541                 return;
 542         }
 543         hdq_data->init_trans++;
 544         mutex_unlock(&hdq_data->hdq_mutex);
 545
 546         hdq_write_byte(hdq_data, byte, &status);
 547         dev_dbg(hdq_data->dev, "Ctrl status %x\n", status);
 548
 549         /* Second write, data transfered. Release the module */
 550         if (hdq_data->init_trans > 1) {
 551                 omap_hdq_put(hdq_data);
 552                 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
 553                 if (ret < 0) {
 554                         dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
 555                         return;
 556                 }
 557                 hdq_data->init_trans = 0;
 558                 mutex_unlock(&hdq_data->hdq_mutex);
 559         }
 560
 561         return;
 562 }
 563
 564 static int __init omap_hdq_probe(struct platform_device *pdev)
 565 {
 566         struct hdq_data *hdq_data;
 567         struct resource *res;
 568         int ret, irq;
 569         u8 rev;
 570
 571         if (!pdev)
 572                 return -ENODEV;
 573
 574         hdq_data = kmalloc(sizeof(*hdq_data), GFP_KERNEL);
 575         if (!hdq_data) {
 576                 dev_dbg(&pdev->dev, "unable to allocate memory\n");
 577                 ret = -ENODEV;
 578                 goto err_kmalloc;
 579         }
 580
 581         hdq_data->dev = &pdev->dev;
 582         platform_set_drvdata(pdev, hdq_data);
 583
 584         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 585         if (!res) {
 586                 dev_dbg(&pdev->dev, "unable to get resource\n");
 587                 ret = ENXIO;
 588                 goto err_resource;
 589         }
 590
 591         hdq_data->hdq_base = ioremap(res->start, SZ_4K);
 592         if (!hdq_data->hdq_base) {
 593                 dev_dbg(&pdev->dev, "ioremap failed\n");
 594                 ret = -EINVAL;
 595                 goto err_ioremap;
 596         }
 597
 598         /* get interface & functional clock objects */
 599         hdq_data->hdq_ick = clk_get(&pdev->dev, "hdq_ick");
 600         hdq_data->hdq_fck = clk_get(&pdev->dev, "hdq_fck");
 601
 602         if (IS_ERR(hdq_data->hdq_ick) || IS_ERR(hdq_data->hdq_fck)) {
 603                 dev_dbg(&pdev->dev, "Can't get HDQ clock objects\n");
 604                 if (IS_ERR(hdq_data->hdq_ick)) {
 605                         ret = PTR_ERR(hdq_data->hdq_ick);
 606                         goto err_clk;
 607                 }
 608                 if (IS_ERR(hdq_data->hdq_fck)) {
 609                         ret = PTR_ERR(hdq_data->hdq_fck);
 610                         clk_put(hdq_data->hdq_ick);
 611                         goto err_clk;
 612                 }
 613         }
 614
 615         hdq_data->hdq_usecount = 0;
 616         mutex_init(&hdq_data->hdq_mutex);
 617
 618         if (clk_enable(hdq_data->hdq_ick)) {
 619                 dev_dbg(&pdev->dev, "Can not enable ick\n");
 620                 ret = -ENODEV;
 621                 goto err_ick;
 622         }
 623
 624         if (clk_enable(hdq_data->hdq_fck)) {
 625                 dev_dbg(&pdev->dev, "Can not enable fck\n");
 626                 ret = -ENODEV;
 627                 goto err_fck;
 628         }
 629
 630         rev = hdq_reg_in(hdq_data, OMAP_HDQ_REVISION);
 631         dev_info(&pdev->dev, "OMAP HDQ Hardware Rev %c.%c. Driver in %s mode\n",
 632                 (rev >> 4) + '0', (rev & 0x0f) + '0', "Interrupt");
 633
 634         spin_lock_init(&hdq_data->hdq_spinlock);
 635         omap_hdq_break(hdq_data);
 636
 637         irq = platform_get_irq(pdev, 0);
 638         if (irq < 0) {
 639                 ret = -ENXIO;
 640                 goto err_irq;
 641         }
 642
 643         ret = request_irq(irq, hdq_isr, IRQF_DISABLED, "omap_hdq", hdq_data);
 644         if (ret < 0) {
 645                 dev_dbg(&pdev->dev, "could not request irq\n");
 646                 goto err_irq;
 647         }
 648
 649         /* don't clock the HDQ until it is needed */
 650         clk_disable(hdq_data->hdq_ick);
 651         clk_disable(hdq_data->hdq_fck);
 652
 653         omap_w1_master.data = hdq_data;
 654
 655         ret = w1_add_master_device(&omap_w1_master);
 656         if (ret) {
 657                 dev_dbg(&pdev->dev, "Failure in registering w1 master\n");
 658                 goto err_w1;
 659         }
 660
 661         return 0;
 662
 663 err_w1:
 664 err_irq:
 665         clk_disable(hdq_data->hdq_fck);
 666
 667 err_fck:
 668         clk_disable(hdq_data->hdq_ick);
 669
 670 err_ick:
 671         clk_put(hdq_data->hdq_ick);
 672         clk_put(hdq_data->hdq_fck);
 673
 674 err_clk:
 675         iounmap(hdq_data->hdq_base);
 676
 677 err_ioremap:
 678 err_resource:
 679         platform_set_drvdata(pdev, NULL);
 680         kfree(hdq_data);
 681
 682 err_kmalloc:
 683         return ret;
 684
 685 }
 686
 687 static int omap_hdq_remove(struct platform_device *pdev)
 688 {
 689         struct hdq_data *hdq_data = platform_get_drvdata(pdev);
 690
 691         mutex_lock(&hdq_data->hdq_mutex);
 692
 693         if (0 != hdq_data->hdq_usecount) {
 694                 dev_dbg(&pdev->dev, "removed when use count is not zero\n");
 695                 return -EBUSY;
 696         }
 697
 698         mutex_unlock(&hdq_data->hdq_mutex);
 699
 700         /* remove module dependency */
 701         clk_put(hdq_data->hdq_ick);
 702         clk_put(hdq_data->hdq_fck);
 703         free_irq(INT_24XX_HDQ_IRQ, hdq_data);
 704         platform_set_drvdata(pdev, NULL);
 705         iounmap(hdq_data->hdq_base);
 706         kfree(hdq_data);
 707
 708         return 0;
 709 }
 710
 711 static int __init
 712 omap_hdq_init(void)
 713 {
 714         return platform_driver_register(&omap_hdq_driver);
 715 }
 716 module_init(omap_hdq_init);
 717
 718 static void __exit
 719 omap_hdq_exit(void)
 720 {
 721         platform_driver_unregister(&omap_hdq_driver);
 722 }
 723 module_exit(omap_hdq_exit);
 724
 725 module_param(w1_id, int, S_IRUSR);
 726 MODULE_PARM_DESC(w1_id, "1-wire id for the slave detection");
 727
 728 MODULE_AUTHOR("Texas Instruments");
 729 MODULE_DESCRIPTION("HDQ driver Library");
 730 MODULE_LICENSE("GPL");