2 * drivers/w1/masters/omap_hdq.c
4 * Copyright (C) 2007 Texas Instruments, Inc.
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/interrupt.h>
15 #include <linux/err.h>
16 #include <linux/clk.h>
19 #include <asm/hardware.h>
22 #include "../w1_int.h"
24 #define MOD_NAME "OMAP_HDQ:"
26 #define OMAP_HDQ_REVISION 0x00
27 #define OMAP_HDQ_TX_DATA 0x04
28 #define OMAP_HDQ_RX_DATA 0x08
29 #define OMAP_HDQ_CTRL_STATUS 0x0c
30 #define OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK (1<<6)
31 #define OMAP_HDQ_CTRL_STATUS_CLOCKENABLE (1<<5)
32 #define OMAP_HDQ_CTRL_STATUS_GO (1<<4)
33 #define OMAP_HDQ_CTRL_STATUS_INITIALIZATION (1<<2)
34 #define OMAP_HDQ_CTRL_STATUS_DIR (1<<1)
35 #define OMAP_HDQ_CTRL_STATUS_MODE (1<<0)
36 #define OMAP_HDQ_INT_STATUS 0x10
37 #define OMAP_HDQ_INT_STATUS_TXCOMPLETE (1<<2)
38 #define OMAP_HDQ_INT_STATUS_RXCOMPLETE (1<<1)
39 #define OMAP_HDQ_INT_STATUS_TIMEOUT (1<<0)
40 #define OMAP_HDQ_SYSCONFIG 0x14
41 #define OMAP_HDQ_SYSCONFIG_SOFTRESET (1<<1)
42 #define OMAP_HDQ_SYSCONFIG_AUTOIDLE (1<<0)
43 #define OMAP_HDQ_SYSSTATUS 0x18
44 #define OMAP_HDQ_SYSSTATUS_RESETDONE (1<<0)
46 #define OMAP_HDQ_FLAG_CLEAR 0
47 #define OMAP_HDQ_FLAG_SET 1
48 #define OMAP_HDQ_TIMEOUT (HZ/5)
50 #define OMAP_HDQ_MAX_USER 4
52 DECLARE_WAIT_QUEUE_HEAD(hdq_wait_queue);
56 resource_size_t hdq_base;
57 struct semaphore hdq_semlock;
62 spinlock_t hdq_spinlock;
65 static struct hdq_data *hdq_data;
67 static int omap_hdq_get(void);
68 static int omap_hdq_put(void);
69 static int omap_hdq_break(void);
71 static int __init omap_hdq_probe(struct platform_device *pdev);
72 static int omap_hdq_remove(struct platform_device *pdev);
74 static struct platform_driver omap_hdq_driver = {
75 .probe = omap_hdq_probe,
76 .remove = omap_hdq_remove,
84 static u8 omap_w1_read_byte(void *data);
85 static void omap_w1_write_byte(void *data, u8 byte);
86 static u8 omap_w1_reset_bus(void *data);
87 static void omap_w1_search_bus(void *data, u8 search_type,
88 w1_slave_found_callback slave_found);
90 static struct w1_bus_master omap_w1_master = {
91 .read_byte = omap_w1_read_byte,
92 .write_byte = omap_w1_write_byte,
93 .reset_bus = omap_w1_reset_bus,
94 .search = omap_w1_search_bus,
98 * HDQ register I/O routines
101 hdq_reg_in(u32 offset)
103 return omap_readb(hdq_data->hdq_base + offset);
107 hdq_reg_out(u32 offset, u8 val)
109 omap_writeb(val, hdq_data->hdq_base + offset);
114 hdq_reg_merge(u32 offset, u8 val, u8 mask)
116 u8 new_val = (omap_readb(hdq_data->hdq_base + offset) & ~mask)
118 omap_writeb(new_val, hdq_data->hdq_base + offset);
123 * Wait for one or more bits in flag change.
124 * HDQ_FLAG_SET: wait until any bit in the flag is set.
125 * HDQ_FLAG_CLEAR: wait until all bits in the flag are cleared.
126 * return 0 on success and -ETIMEDOUT in the case of timeout.
129 hdq_wait_for_flag(u32 offset, u8 flag, u8 flag_set, u8 *status)
132 unsigned long timeout = jiffies + OMAP_HDQ_TIMEOUT;
134 if (flag_set == OMAP_HDQ_FLAG_CLEAR) {
135 /* wait for the flag clear */
136 while (((*status = hdq_reg_in(offset)) & flag)
137 && time_before(jiffies, timeout)) {
138 set_current_state(TASK_UNINTERRUPTIBLE);
141 if (unlikely(*status & flag))
143 } else if (flag_set == OMAP_HDQ_FLAG_SET) {
144 /* wait for the flag set */
145 while (!((*status = hdq_reg_in(offset)) & flag)
146 && time_before(jiffies, timeout)) {
147 set_current_state(TASK_UNINTERRUPTIBLE);
150 if (unlikely(!(*status & flag)))
159 * write out a byte and fill *status with HDQ_INT_STATUS
162 hdq_write_byte(u8 val, u8 *status)
166 unsigned long irqflags;
170 spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
171 /* clear interrupt flags via a dummy read */
172 hdq_reg_in(OMAP_HDQ_INT_STATUS);
173 /* ISR loads it with new INT_STATUS */
174 hdq_data->hdq_irqstatus = 0;
175 spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
177 hdq_reg_out(OMAP_HDQ_TX_DATA, val);
180 hdq_reg_merge(OMAP_HDQ_CTRL_STATUS, OMAP_HDQ_CTRL_STATUS_GO,
181 OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO);
182 /* wait for the TXCOMPLETE bit */
183 ret = wait_event_interruptible_timeout(hdq_wait_queue,
184 hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT);
185 if (unlikely(ret < 0)) {
186 pr_debug("wait interrupted");
190 spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
191 *status = hdq_data->hdq_irqstatus;
192 spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
193 /* check irqstatus */
194 if (!(*status & OMAP_HDQ_INT_STATUS_TXCOMPLETE)) {
195 pr_debug("timeout waiting for TXCOMPLETE/RXCOMPLETE, %x",
200 /* wait for the GO bit return to zero */
201 ret = hdq_wait_for_flag(OMAP_HDQ_CTRL_STATUS, OMAP_HDQ_CTRL_STATUS_GO,
202 OMAP_HDQ_FLAG_CLEAR, &tmp_status);
204 pr_debug("timeout waiting GO bit return to zero, %x",
213 * HDQ Interrupt service routine.
216 hdq_isr(int irq, void *arg)
218 unsigned long irqflags;
220 spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
221 hdq_data->hdq_irqstatus = hdq_reg_in(OMAP_HDQ_INT_STATUS);
222 spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
223 pr_debug("hdq_isr: %x", hdq_data->hdq_irqstatus);
225 if (hdq_data->hdq_irqstatus &
226 (OMAP_HDQ_INT_STATUS_TXCOMPLETE | OMAP_HDQ_INT_STATUS_RXCOMPLETE
227 | OMAP_HDQ_INT_STATUS_TIMEOUT)) {
228 /* wake up sleeping process */
229 wake_up_interruptible(&hdq_wait_queue);
236 * HDQ Mode: always return success.
238 static u8 omap_w1_reset_bus(void *data)
244 * W1 search callback function.
246 static void omap_w1_search_bus(void *data, u8 search_type,
247 w1_slave_found_callback slave_found)
249 u64 module_id, rn_le, cs, id;
256 rn_le = cpu_to_le64(module_id);
258 * HDQ might not obey truly the 1-wire spec.
259 * So calculate CRC based on module parameter.
261 cs = w1_calc_crc8((u8 *)&rn_le, 7);
262 id = (cs << 56) | module_id;
264 slave_found(data, id);
268 _omap_hdq_reset(void)
273 hdq_reg_out(OMAP_HDQ_SYSCONFIG, OMAP_HDQ_SYSCONFIG_SOFTRESET);
275 * Select HDQ mode & enable clocks.
276 * It is observed that INT flags can't be cleared via a read and GO/INIT
277 * won't return to zero if interrupt is disabled. So we always enable
280 hdq_reg_out(OMAP_HDQ_CTRL_STATUS,
281 OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
282 OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
284 /* wait for reset to complete */
285 ret = hdq_wait_for_flag(OMAP_HDQ_SYSSTATUS,
286 OMAP_HDQ_SYSSTATUS_RESETDONE, OMAP_HDQ_FLAG_SET, &tmp_status);
288 pr_debug("timeout waiting HDQ reset, %x", tmp_status);
290 hdq_reg_out(OMAP_HDQ_CTRL_STATUS,
291 OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
292 OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
293 hdq_reg_out(OMAP_HDQ_SYSCONFIG, OMAP_HDQ_SYSCONFIG_AUTOIDLE);
300 * Issue break pulse to the device.
307 unsigned long irqflags;
309 ret = down_interruptible(&hdq_data->hdq_semlock);
313 if (!hdq_data->hdq_usecount) {
314 up(&hdq_data->hdq_semlock);
318 spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
319 /* clear interrupt flags via a dummy read */
320 hdq_reg_in(OMAP_HDQ_INT_STATUS);
321 /* ISR loads it with new INT_STATUS */
322 hdq_data->hdq_irqstatus = 0;
323 spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
325 /* set the INIT and GO bit */
326 hdq_reg_merge(OMAP_HDQ_CTRL_STATUS,
327 OMAP_HDQ_CTRL_STATUS_INITIALIZATION | OMAP_HDQ_CTRL_STATUS_GO,
328 OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_INITIALIZATION |
329 OMAP_HDQ_CTRL_STATUS_GO);
331 /* wait for the TIMEOUT bit */
332 ret = wait_event_interruptible_timeout(hdq_wait_queue,
333 hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT);
334 if (unlikely(ret < 0)) {
335 pr_debug("wait interrupted");
336 up(&hdq_data->hdq_semlock);
340 spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
341 tmp_status = hdq_data->hdq_irqstatus;
342 spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
343 /* check irqstatus */
344 if (!(tmp_status & OMAP_HDQ_INT_STATUS_TIMEOUT)) {
345 pr_debug("timeout waiting for TIMEOUT, %x", tmp_status);
346 up(&hdq_data->hdq_semlock);
350 * wait for both INIT and GO bits rerurn to zero.
351 * zero wait time expected for interrupt mode.
353 ret = hdq_wait_for_flag(OMAP_HDQ_CTRL_STATUS,
354 OMAP_HDQ_CTRL_STATUS_INITIALIZATION |
355 OMAP_HDQ_CTRL_STATUS_GO, OMAP_HDQ_FLAG_CLEAR,
358 pr_debug("timeout waiting INIT&GO bits return to zero, %x",
361 up(&hdq_data->hdq_semlock);
365 static int hdq_read_byte(u8 *val)
369 unsigned long irqflags;
371 ret = down_interruptible(&hdq_data->hdq_semlock);
375 if (!hdq_data->hdq_usecount) {
376 up(&hdq_data->hdq_semlock);
380 if (!(hdq_data->hdq_irqstatus & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) {
381 hdq_reg_merge(OMAP_HDQ_CTRL_STATUS,
382 OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO,
383 OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO);
385 * The RX comes immediately after TX. It
386 * triggers another interrupt before we
387 * sleep. So we have to wait for RXCOMPLETE bit.
390 unsigned long timeout = jiffies + OMAP_HDQ_TIMEOUT;
391 while (!(hdq_data->hdq_irqstatus
392 & OMAP_HDQ_INT_STATUS_RXCOMPLETE)
393 && time_before(jiffies, timeout)) {
394 set_current_state(TASK_UNINTERRUPTIBLE);
398 hdq_reg_merge(OMAP_HDQ_CTRL_STATUS, 0,
399 OMAP_HDQ_CTRL_STATUS_DIR);
400 spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
401 status = hdq_data->hdq_irqstatus;
402 spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
403 /* check irqstatus */
404 if (!(status & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) {
405 pr_debug("timeout waiting for RXCOMPLETE, %x", status);
406 up(&hdq_data->hdq_semlock);
410 /* the data is ready. Read it in! */
411 *val = hdq_reg_in(OMAP_HDQ_RX_DATA);
412 up(&hdq_data->hdq_semlock);
419 * Enable clocks and set the controller to HDQ mode.
426 ret = down_interruptible(&hdq_data->hdq_semlock);
430 if (OMAP_HDQ_MAX_USER == hdq_data->hdq_usecount) {
431 pr_debug("attempt to exceed the max use count");
432 up(&hdq_data->hdq_semlock);
435 hdq_data->hdq_usecount++;
436 try_module_get(THIS_MODULE);
437 if (1 == hdq_data->hdq_usecount) {
438 if (clk_enable(hdq_data->hdq_ick)) {
439 pr_debug("Can not enable ick\n");
440 clk_put(hdq_data->hdq_ick);
441 clk_put(hdq_data->hdq_fck);
442 up(&hdq_data->hdq_semlock);
445 if (clk_enable(hdq_data->hdq_fck)) {
446 pr_debug("Can not enable fck\n");
447 clk_put(hdq_data->hdq_ick);
448 clk_put(hdq_data->hdq_fck);
449 up(&hdq_data->hdq_semlock);
453 /* make sure HDQ is out of reset */
454 if (!(hdq_reg_in(OMAP_HDQ_SYSSTATUS) &
455 OMAP_HDQ_SYSSTATUS_RESETDONE)) {
456 ret = _omap_hdq_reset();
458 /* back up the count */
459 hdq_data->hdq_usecount--;
461 /* select HDQ mode & enable clocks */
462 hdq_reg_out(OMAP_HDQ_CTRL_STATUS,
463 OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
464 OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
465 hdq_reg_out(OMAP_HDQ_SYSCONFIG,
466 OMAP_HDQ_SYSCONFIG_AUTOIDLE);
467 hdq_reg_in(OMAP_HDQ_INT_STATUS);
471 up(&hdq_data->hdq_semlock);
476 * Disable clocks to the module.
483 ret = down_interruptible(&hdq_data->hdq_semlock);
487 if (0 == hdq_data->hdq_usecount) {
488 pr_debug("attempt to decrement use count when it is zero");
491 hdq_data->hdq_usecount--;
492 module_put(THIS_MODULE);
493 if (0 == hdq_data->hdq_usecount) {
494 clk_disable(hdq_data->hdq_ick);
495 clk_disable(hdq_data->hdq_fck);
498 up(&hdq_data->hdq_semlock);
503 * Used to control the call to omap_hdq_get and omap_hdq_put.
504 * HDQ Protocol: Write the CMD|REG_address first, followed by
505 * the data wrire or read.
507 static int init_trans;
510 * Read a byte of data from the device.
512 static u8 omap_w1_read_byte(void *data)
517 ret = hdq_read_byte(&val);
521 /* Write followed by a read, release the module */
531 * Write a byte of data to the device.
533 static void omap_w1_write_byte(void *data, u8 byte)
537 /* First write to initialize the transfer */
543 hdq_write_byte(byte, &status);
544 pr_debug("Ctrl status %x\n", status);
546 /* Second write, data transfered. Release the module */
547 if (init_trans > 1) {
555 static int __init omap_hdq_probe(struct platform_device *pdev)
557 struct resource *res;
564 hdq_data = kmalloc(sizeof(*hdq_data), GFP_KERNEL);
568 platform_set_drvdata(pdev, hdq_data);
570 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
572 platform_set_drvdata(pdev, NULL);
577 hdq_data->hdq_base = res->start;
579 /* get interface & functional clock objects */
580 hdq_data->hdq_ick = clk_get(&pdev->dev, "hdq_ick");
581 hdq_data->hdq_fck = clk_get(&pdev->dev, "hdq_fck");
583 if (IS_ERR(hdq_data->hdq_ick) || IS_ERR(hdq_data->hdq_fck)) {
584 pr_debug("Can't get HDQ clock objects\n");
585 if (IS_ERR(hdq_data->hdq_ick)) {
586 ret = PTR_ERR(hdq_data->hdq_ick);
587 platform_set_drvdata(pdev, NULL);
591 if (IS_ERR(hdq_data->hdq_fck)) {
592 ret = PTR_ERR(hdq_data->hdq_fck);
593 platform_set_drvdata(pdev, NULL);
599 hdq_data->hdq_usecount = 0;
600 sema_init(&hdq_data->hdq_semlock, 1);
602 if (clk_enable(hdq_data->hdq_ick)) {
603 pr_debug("Can not enable ick\n");
604 clk_put(hdq_data->hdq_ick);
605 clk_put(hdq_data->hdq_fck);
606 platform_set_drvdata(pdev, NULL);
611 if (clk_enable(hdq_data->hdq_fck)) {
612 pr_debug("Can not enable fck\n");
613 clk_disable(hdq_data->hdq_ick);
614 clk_put(hdq_data->hdq_ick);
615 clk_put(hdq_data->hdq_fck);
616 platform_set_drvdata(pdev, NULL);
621 rev = hdq_reg_in(OMAP_HDQ_REVISION);
622 pr_info("OMAP HDQ Hardware Revision %c.%c. Driver in %s mode.\n",
623 (rev >> 4) + '0', (rev & 0x0f) + '0', "Interrupt");
625 spin_lock_init(&hdq_data->hdq_spinlock);
628 irq = platform_get_irq(pdev, 0);
630 platform_set_drvdata(pdev, NULL);
635 if (request_irq(irq, hdq_isr, IRQF_DISABLED, "OMAP HDQ",
636 &hdq_data->hdq_semlock)) {
637 pr_debug("request_irq failed\n");
638 clk_disable(hdq_data->hdq_ick);
639 clk_put(hdq_data->hdq_ick);
640 clk_put(hdq_data->hdq_fck);
641 platform_set_drvdata(pdev, NULL);
646 /* don't clock the HDQ until it is needed */
647 clk_disable(hdq_data->hdq_ick);
648 clk_disable(hdq_data->hdq_fck);
650 ret = w1_add_master_device(&omap_w1_master);
652 pr_debug("Failure in registering w1 master\n");
653 clk_put(hdq_data->hdq_ick);
654 clk_put(hdq_data->hdq_fck);
655 platform_set_drvdata(pdev, NULL);
663 static int omap_hdq_remove(struct platform_device *pdev)
665 down_interruptible(&hdq_data->hdq_semlock);
666 if (0 != hdq_data->hdq_usecount) {
667 pr_debug("removed when use count is not zero\n");
670 up(&hdq_data->hdq_semlock);
672 /* remove module dependency */
673 clk_put(hdq_data->hdq_ick);
674 clk_put(hdq_data->hdq_fck);
675 free_irq(INT_24XX_HDQ_IRQ, &hdq_data->hdq_semlock);
676 platform_set_drvdata(pdev, NULL);
685 return platform_driver_register(&omap_hdq_driver);
691 platform_driver_unregister(&omap_hdq_driver);
694 module_init(omap_hdq_init);
695 module_exit(omap_hdq_exit);
697 module_param(W1_ID, int, S_IRUSR);
699 MODULE_AUTHOR("Texas Instruments");
700 MODULE_DESCRIPTION("HDQ driver Library");
701 MODULE_LICENSE("GPL");