drivers/w1/masters/omap_hdq.c

   1 /*
   2  * drivers/w1/masters/omap_hdq.c
   3  *
   4  * Copyright (C) 2007 Texas Instruments, Inc.
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2. This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  *
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/err.h>
  16 #include <linux/clk.h>
  17 #include <linux/io.h>
  18 #include <asm/irq.h>
  19 #include <mach/hardware.h>
  20
  21 #include "../w1.h"
  22 #include "../w1_int.h"
  23
  24 #define MOD_NAME        "OMAP_HDQ:"
  25
  26 #define OMAP_HDQ_REVISION                       0x00
  27 #define OMAP_HDQ_TX_DATA                        0x04
  28 #define OMAP_HDQ_RX_DATA                        0x08
  29 #define OMAP_HDQ_CTRL_STATUS                    0x0c
  30 #define OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK      (1<<6)
  31 #define OMAP_HDQ_CTRL_STATUS_CLOCKENABLE        (1<<5)
  32 #define OMAP_HDQ_CTRL_STATUS_GO                 (1<<4)
  33 #define OMAP_HDQ_CTRL_STATUS_INITIALIZATION     (1<<2)
  34 #define OMAP_HDQ_CTRL_STATUS_DIR                (1<<1)
  35 #define OMAP_HDQ_CTRL_STATUS_MODE               (1<<0)
  36 #define OMAP_HDQ_INT_STATUS                     0x10
  37 #define OMAP_HDQ_INT_STATUS_TXCOMPLETE          (1<<2)
  38 #define OMAP_HDQ_INT_STATUS_RXCOMPLETE          (1<<1)
  39 #define OMAP_HDQ_INT_STATUS_TIMEOUT             (1<<0)
  40 #define OMAP_HDQ_SYSCONFIG                      0x14
  41 #define OMAP_HDQ_SYSCONFIG_SOFTRESET            (1<<1)
  42 #define OMAP_HDQ_SYSCONFIG_AUTOIDLE             (1<<0)
  43 #define OMAP_HDQ_SYSSTATUS                      0x18
  44 #define OMAP_HDQ_SYSSTATUS_RESETDONE            (1<<0)
  45
  46 #define OMAP_HDQ_FLAG_CLEAR                     0
  47 #define OMAP_HDQ_FLAG_SET                       1
  48 #define OMAP_HDQ_TIMEOUT                        (HZ/5)
  49
  50 #define OMAP_HDQ_MAX_USER                       4
  51
  52 static DECLARE_WAIT_QUEUE_HEAD(hdq_wait_queue);
  53 static int w1_id;
  54
  55 struct hdq_data {
  56         struct device           *dev;
  57         void __iomem            *hdq_base;
  58         struct  mutex           hdq_mutex;
  59         int                     hdq_usecount;
  60         struct  clk             *hdq_ick;
  61         struct  clk             *hdq_fck;
  62         u8                      hdq_irqstatus;
  63         spinlock_t              hdq_spinlock;
  64         /*
  65          * Used to control the call to omap_hdq_get and omap_hdq_put.
  66          * HDQ Protocol: Write the CMD|REG_address first, followed by
  67          * the data wrire or read.
  68          */
  69         int                     init_trans;
  70 };
  71
  72 static int omap_hdq_get(struct hdq_data *hdq_data);
  73 static int omap_hdq_put(struct hdq_data *hdq_data);
  74 static int omap_hdq_break(struct hdq_data *hdq_data);
  75
  76 static int __init omap_hdq_probe(struct platform_device *pdev);
  77 static int omap_hdq_remove(struct platform_device *pdev);
  78
  79 static struct platform_driver omap_hdq_driver = {
  80         .probe =        omap_hdq_probe,
  81         .remove =       omap_hdq_remove,
  82         .suspend =      NULL,
  83         .resume =       NULL,
  84         .driver =       {
  85                 .name = "omap_hdq",
  86         },
  87 };
  88
  89 static u8 omap_w1_read_byte(void *_hdq);
  90 static void omap_w1_write_byte(void *_hdq, u8 byte);
  91 static u8 omap_w1_reset_bus(void *_hdq);
  92 static void omap_w1_search_bus(void *_hdq, u8 search_type,
  93         w1_slave_found_callback slave_found);
  94
  95
  96 static struct w1_bus_master omap_w1_master = {
  97         .read_byte      = omap_w1_read_byte,
  98         .write_byte     = omap_w1_write_byte,
  99         .reset_bus      = omap_w1_reset_bus,
 100         .search         = omap_w1_search_bus,
 101 };
 102
 103 /* HDQ register I/O routines */
 104 static inline u8 hdq_reg_in(struct hdq_data *hdq_data, u32 offset)
 105 {
 106         return __raw_readb(hdq_data->hdq_base + offset);
 107 }
 108
 109 static inline u8 hdq_reg_out(struct hdq_data *hdq_data, u32 offset, u8 val)
 110 {
 111         __raw_writeb(val, hdq_data->hdq_base + offset);
 112
 113         return val;
 114 }
 115
 116 static inline u8 hdq_reg_merge(struct hdq_data *hdq_data, u32 offset,
 117                         u8 val, u8 mask)
 118 {
 119         u8 new_val = (__raw_readb(hdq_data->hdq_base + offset) & ~mask)
 120                         | (val & mask);
 121         __raw_writeb(new_val, hdq_data->hdq_base + offset);
 122
 123         return new_val;
 124 }
 125
 126 /*
 127  * Wait for one or more bits in flag change.
 128  * HDQ_FLAG_SET: wait until any bit in the flag is set.
 129  * HDQ_FLAG_CLEAR: wait until all bits in the flag are cleared.
 130  * return 0 on success and -ETIMEDOUT in the case of timeout.
 131  */
 132 static int hdq_wait_for_flag(struct hdq_data *hdq_data, u32 offset,
 133                 u8 flag, u8 flag_set, u8 *status)
 134 {
 135         int ret = 0;
 136         unsigned long timeout = jiffies + OMAP_HDQ_TIMEOUT;
 137
 138         if (flag_set == OMAP_HDQ_FLAG_CLEAR) {
 139                 /* wait for the flag clear */
 140                 while (((*status = hdq_reg_in(hdq_data, offset)) & flag)
 141                         && time_before(jiffies, timeout)) {
 142                         set_current_state(TASK_UNINTERRUPTIBLE);
 143                         schedule_timeout(1);
 144                 }
 145                 if (*status & flag)
 146                         ret = -ETIMEDOUT;
 147         } else if (flag_set == OMAP_HDQ_FLAG_SET) {
 148                 /* wait for the flag set */
 149                 while (!((*status = hdq_reg_in(hdq_data, offset)) & flag)
 150                         && time_before(jiffies, timeout)) {
 151                         set_current_state(TASK_UNINTERRUPTIBLE);
 152                         schedule_timeout(1);
 153                 }
 154                 if (!(*status & flag))
 155                         ret = -ETIMEDOUT;
 156         } else
 157                 return -EINVAL;
 158
 159         return ret;
 160 }
 161
 162 /* write out a byte and fill *status with HDQ_INT_STATUS */
 163 static int hdq_write_byte(struct hdq_data *hdq_data, u8 val, u8 *status)
 164 {
 165         int ret;
 166         u8 tmp_status;
 167         unsigned long irqflags;
 168
 169         *status = 0;
 170
 171         spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
 172         /* clear interrupt flags via a dummy read */
 173         hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
 174         /* ISR loads it with new INT_STATUS */
 175         hdq_data->hdq_irqstatus = 0;
 176         spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
 177
 178         hdq_reg_out(hdq_data, OMAP_HDQ_TX_DATA, val);
 179
 180         /* set the GO bit */
 181         hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, OMAP_HDQ_CTRL_STATUS_GO,
 182                 OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO);
 183         /* wait for the TXCOMPLETE bit */
 184         ret = wait_event_interruptible_timeout(hdq_wait_queue,
 185                 hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT);
 186         if (ret < 0) {
 187                 dev_dbg(hdq_data->dev, "wait interrupted");
 188                 return -EINTR;
 189         }
 190
 191         spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
 192         *status = hdq_data->hdq_irqstatus;
 193         spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
 194         /* check irqstatus */
 195         if (!(*status & OMAP_HDQ_INT_STATUS_TXCOMPLETE)) {
 196                 dev_dbg(hdq_data->dev, "timeout waiting for"
 197                         "TXCOMPLETE/RXCOMPLETE, %x", *status);
 198                 return -ETIMEDOUT;
 199         }
 200
 201         /* wait for the GO bit return to zero */
 202         ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_CTRL_STATUS,
 203                         OMAP_HDQ_CTRL_STATUS_GO,
 204                         OMAP_HDQ_FLAG_CLEAR, &tmp_status);
 205         if (ret) {
 206                 dev_dbg(hdq_data->dev, "timeout waiting GO bit"
 207                         "return to zero, %x", tmp_status);
 208                 return ret;
 209         }
 210
 211         return ret;
 212 }
 213
 214 /* HDQ Interrupt service routine */
 215 static irqreturn_t hdq_isr(int irq, void *_hdq)
 216 {
 217         struct hdq_data *hdq_data = _hdq;
 218         unsigned long irqflags;
 219
 220         spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
 221         hdq_data->hdq_irqstatus = hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
 222         spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
 223         dev_dbg(hdq_data->dev, "hdq_isr: %x", hdq_data->hdq_irqstatus);
 224
 225         if (hdq_data->hdq_irqstatus &
 226                 (OMAP_HDQ_INT_STATUS_TXCOMPLETE | OMAP_HDQ_INT_STATUS_RXCOMPLETE
 227                 | OMAP_HDQ_INT_STATUS_TIMEOUT)) {
 228                 /* wake up sleeping process */
 229                 wake_up_interruptible(&hdq_wait_queue);
 230         }
 231
 232         return IRQ_HANDLED;
 233 }
 234
 235 /* HDQ Mode: always return success */
 236 static u8 omap_w1_reset_bus(void *_hdq)
 237 {
 238         return 0;
 239 }
 240
 241 /* W1 search callback function */
 242 static void omap_w1_search_bus(void *_hdq, u8 search_type,
 243         w1_slave_found_callback slave_found)
 244 {
 245         u64 module_id, rn_le, cs, id;
 246
 247         if (w1_id)
 248                 module_id = w1_id;
 249         else
 250                 module_id = 0x1;
 251
 252         rn_le = cpu_to_le64(module_id);
 253         /*
 254          * HDQ might not obey truly the 1-wire spec.
 255          * So calculate CRC based on module parameter.
 256          */
 257         cs = w1_calc_crc8((u8 *)&rn_le, 7);
 258         id = (cs << 56) | module_id;
 259
 260         slave_found(_hdq, id);
 261 }
 262
 263 static int _omap_hdq_reset(struct hdq_data *hdq_data)
 264 {
 265         int ret;
 266         u8 tmp_status;
 267
 268         hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG, OMAP_HDQ_SYSCONFIG_SOFTRESET);
 269         /*
 270          * Select HDQ mode & enable clocks.
 271          * It is observed that INT flags can't be cleared via a read and GO/INIT
 272          * won't return to zero if interrupt is disabled. So we always enable
 273          * interrupt.
 274          */
 275         hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
 276                 OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
 277                 OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
 278
 279         /* wait for reset to complete */
 280         ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_SYSSTATUS,
 281                 OMAP_HDQ_SYSSTATUS_RESETDONE, OMAP_HDQ_FLAG_SET, &tmp_status);
 282         if (ret)
 283                 dev_dbg(hdq_data->dev, "timeout waiting HDQ reset, %x",
 284                                 tmp_status);
 285         else {
 286                 hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
 287                         OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
 288                         OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
 289                 hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG,
 290                         OMAP_HDQ_SYSCONFIG_AUTOIDLE);
 291         }
 292
 293         return ret;
 294 }
 295
 296 /* Issue break pulse to the device */
 297 static int omap_hdq_break(struct hdq_data *hdq_data)
 298 {
 299         int ret;
 300         u8 tmp_status;
 301         unsigned long irqflags;
 302
 303         ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
 304         if (ret < 0)
 305                 return -EINTR;
 306
 307         if (!hdq_data->hdq_usecount) {
 308                 mutex_unlock(&hdq_data->hdq_mutex);
 309                 return -EINVAL;
 310         }
 311
 312         spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
 313         /* clear interrupt flags via a dummy read */
 314         hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
 315         /* ISR loads it with new INT_STATUS */
 316         hdq_data->hdq_irqstatus = 0;
 317         spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
 318
 319         /* set the INIT and GO bit */
 320         hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS,
 321                 OMAP_HDQ_CTRL_STATUS_INITIALIZATION | OMAP_HDQ_CTRL_STATUS_GO,
 322                 OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_INITIALIZATION |
 323                 OMAP_HDQ_CTRL_STATUS_GO);
 324
 325         /* wait for the TIMEOUT bit */
 326         ret = wait_event_interruptible_timeout(hdq_wait_queue,
 327                 hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT);
 328         if (ret < 0) {
 329                 dev_dbg(hdq_data->dev, "wait interrupted");
 330                 mutex_unlock(&hdq_data->hdq_mutex);
 331                 return -EINTR;
 332         }
 333
 334         spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
 335         tmp_status = hdq_data->hdq_irqstatus;
 336         spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
 337         /* check irqstatus */
 338         if (!(tmp_status & OMAP_HDQ_INT_STATUS_TIMEOUT)) {
 339                 dev_dbg(hdq_data->dev, "timeout waiting for TIMEOUT, %x",
 340                                 tmp_status);
 341                 mutex_unlock(&hdq_data->hdq_mutex);
 342                 return -ETIMEDOUT;
 343         }
 344         /*
 345          * wait for both INIT and GO bits rerurn to zero.
 346          * zero wait time expected for interrupt mode.
 347          */
 348         ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_CTRL_STATUS,
 349                         OMAP_HDQ_CTRL_STATUS_INITIALIZATION |
 350                         OMAP_HDQ_CTRL_STATUS_GO, OMAP_HDQ_FLAG_CLEAR,
 351                         &tmp_status);
 352         if (ret)
 353                 dev_dbg(hdq_data->dev, "timeout waiting INIT&GO bits"
 354                         "return to zero, %x", tmp_status);
 355
 356         mutex_unlock(&hdq_data->hdq_mutex);
 357
 358         return ret;
 359 }
 360
 361 static int hdq_read_byte(struct hdq_data *hdq_data, u8 *val)
 362 {
 363         int ret;
 364         u8 status;
 365         unsigned long irqflags;
 366         unsigned long timeout = jiffies + OMAP_HDQ_TIMEOUT;
 367
 368         ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
 369         if (ret < 0)
 370                 return -EINTR;
 371
 372         if (!hdq_data->hdq_usecount) {
 373                 mutex_unlock(&hdq_data->hdq_mutex);
 374                 return -EINVAL;
 375         }
 376
 377         if (!(hdq_data->hdq_irqstatus & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) {
 378                 hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS,
 379                         OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO,
 380                         OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO);
 381                 /*
 382                  * The RX comes immediately after TX. It
 383                  * triggers another interrupt before we
 384                  * sleep. So we have to wait for RXCOMPLETE bit.
 385                  */
 386                 while (!(hdq_data->hdq_irqstatus
 387                         & OMAP_HDQ_INT_STATUS_RXCOMPLETE)
 388                         && time_before(jiffies, timeout)) {
 389                         set_current_state(TASK_UNINTERRUPTIBLE);
 390                         schedule_timeout(1);
 391                 }
 392                 hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, 0,
 393                         OMAP_HDQ_CTRL_STATUS_DIR);
 394                 spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
 395                 status = hdq_data->hdq_irqstatus;
 396                 spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
 397                 /* check irqstatus */
 398                 if (!(status & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) {
 399                         dev_dbg(hdq_data->dev, "timeout waiting for"
 400                                 "RXCOMPLETE, %x", status);
 401                         mutex_unlock(&hdq_data->hdq_mutex);
 402                         return -ETIMEDOUT;
 403                 }
 404         }
 405         /* the data is ready. Read it in! */
 406         *val = hdq_reg_in(hdq_data, OMAP_HDQ_RX_DATA);
 407         mutex_unlock(&hdq_data->hdq_mutex);
 408
 409         return 0;
 410
 411 }
 412
 413 /* Enable clocks and set the controller to HDQ mode */
 414 static int omap_hdq_get(struct hdq_data *hdq_data)
 415 {
 416         int ret = 0;
 417
 418         ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
 419         if (ret < 0)
 420                 return -EINTR;
 421
 422         if (OMAP_HDQ_MAX_USER == hdq_data->hdq_usecount) {
 423                 dev_dbg(hdq_data->dev, "attempt to exceed the max use count");
 424                 mutex_unlock(&hdq_data->hdq_mutex);
 425                 ret = -EINVAL;
 426         } else {
 427                 hdq_data->hdq_usecount++;
 428                 try_module_get(THIS_MODULE);
 429                 if (1 == hdq_data->hdq_usecount) {
 430                         if (clk_enable(hdq_data->hdq_ick)) {
 431                                 dev_dbg(hdq_data->dev, "Can not enable ick\n");
 432                                 clk_put(hdq_data->hdq_ick);
 433                                 clk_put(hdq_data->hdq_fck);
 434                                 mutex_unlock(&hdq_data->hdq_mutex);
 435                                 return -ENODEV;
 436                         }
 437                         if (clk_enable(hdq_data->hdq_fck)) {
 438                                 dev_dbg(hdq_data->dev, "Can not enable fck\n");
 439                                 clk_put(hdq_data->hdq_ick);
 440                                 clk_put(hdq_data->hdq_fck);
 441                                 mutex_unlock(&hdq_data->hdq_mutex);
 442                                 return -ENODEV;
 443                         }
 444
 445                         /* make sure HDQ is out of reset */
 446                         if (!(hdq_reg_in(hdq_data, OMAP_HDQ_SYSSTATUS) &
 447                                 OMAP_HDQ_SYSSTATUS_RESETDONE)) {
 448                                 ret = _omap_hdq_reset(hdq_data);
 449                                 if (ret)
 450                                         /* back up the count */
 451                                         hdq_data->hdq_usecount--;
 452                         } else {
 453                                 /* select HDQ mode & enable clocks */
 454                                 hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
 455                                         OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
 456                                         OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
 457                                 hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG,
 458                                         OMAP_HDQ_SYSCONFIG_AUTOIDLE);
 459                                 hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
 460                         }
 461                 }
 462         }
 463         mutex_unlock(&hdq_data->hdq_mutex);
 464
 465         return ret;
 466 }
 467
 468 /* Disable clocks to the module */
 469 static int omap_hdq_put(struct hdq_data *hdq_data)
 470 {
 471         int ret = 0;
 472
 473         ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
 474         if (ret < 0)
 475                 return -EINTR;
 476
 477         if (0 == hdq_data->hdq_usecount) {
 478                 dev_dbg(hdq_data->dev, "attempt to decrement use count"
 479                         "when it is zero");
 480                 ret = -EINVAL;
 481         } else {
 482                 hdq_data->hdq_usecount--;
 483                 module_put(THIS_MODULE);
 484                 if (0 == hdq_data->hdq_usecount) {
 485                         clk_disable(hdq_data->hdq_ick);
 486                         clk_disable(hdq_data->hdq_fck);
 487                 }
 488         }
 489         mutex_unlock(&hdq_data->hdq_mutex);
 490
 491         return ret;
 492 }
 493
 494 /* Read a byte of data from the device */
 495 static u8 omap_w1_read_byte(void *_hdq)
 496 {
 497         struct hdq_data *hdq_data = _hdq;
 498         u8 val;
 499         int ret;
 500
 501         ret = hdq_read_byte(hdq_data, &val);
 502         if (ret) {
 503                 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
 504                 if (ret < 0) {
 505                         dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
 506                         return -EINTR;
 507                 }
 508                 hdq_data->init_trans = 0;
 509                 mutex_unlock(&hdq_data->hdq_mutex);
 510                 omap_hdq_put(hdq_data);
 511                 return -1;
 512         }
 513
 514         /* Write followed by a read, release the module */
 515         if (hdq_data->init_trans) {
 516                 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
 517                 if (ret < 0) {
 518                         dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
 519                         return -EINTR;
 520                 }
 521                 hdq_data->init_trans = 0;
 522                 mutex_unlock(&hdq_data->hdq_mutex);
 523                 omap_hdq_put(hdq_data);
 524         }
 525
 526         return val;
 527 }
 528
 529 /* Write a byte of data to the device */
 530 static void omap_w1_write_byte(void *_hdq, u8 byte)
 531 {
 532         struct hdq_data *hdq_data = _hdq;
 533         int ret;
 534         u8 status;
 535
 536         /* First write to initialize the transfer */
 537         if (hdq_data->init_trans == 0)
 538                 omap_hdq_get(hdq_data);
 539
 540         ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
 541         if (ret < 0) {
 542                 dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
 543                 return;
 544         }
 545         hdq_data->init_trans++;
 546         mutex_unlock(&hdq_data->hdq_mutex);
 547
 548         hdq_write_byte(hdq_data, byte, &status);
 549         dev_dbg(hdq_data->dev, "Ctrl status %x\n", status);
 550
 551         /* Second write, data transfered. Release the module */
 552         if (hdq_data->init_trans > 1) {
 553                 omap_hdq_put(hdq_data);
 554                 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
 555                 if (ret < 0) {
 556                         dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
 557                         return;
 558                 }
 559                 hdq_data->init_trans = 0;
 560                 mutex_unlock(&hdq_data->hdq_mutex);
 561         }
 562
 563         return;
 564 }
 565
 566 static int __init omap_hdq_probe(struct platform_device *pdev)
 567 {
 568         struct hdq_data *hdq_data;
 569         struct resource *res;
 570         int ret, irq;
 571         u8 rev;
 572
 573         if (!pdev)
 574                 return -ENODEV;
 575
 576         hdq_data = kmalloc(sizeof(*hdq_data), GFP_KERNEL);
 577         if (!hdq_data) {
 578                 dev_dbg(&pdev->dev, "unable to allocate memory\n");
 579                 ret = -ENODEV;
 580                 goto err_kmalloc;
 581         }
 582
 583         hdq_data->dev = &pdev->dev;
 584         platform_set_drvdata(pdev, hdq_data);
 585
 586         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 587         if (!res) {
 588                 dev_dbg(&pdev->dev, "unable to get resource\n");
 589                 ret = ENXIO;
 590                 goto err_resource;
 591         }
 592
 593         hdq_data->hdq_base = ioremap(res->start, SZ_4K);
 594         if (!hdq_data->hdq_base) {
 595                 dev_dbg(&pdev->dev, "ioremap failed\n");
 596                 ret = -EINVAL;
 597                 goto err_ioremap;
 598         }
 599
 600         /* get interface & functional clock objects */
 601         hdq_data->hdq_ick = clk_get(&pdev->dev, "hdq_ick");
 602         hdq_data->hdq_fck = clk_get(&pdev->dev, "hdq_fck");
 603
 604         if (IS_ERR(hdq_data->hdq_ick) || IS_ERR(hdq_data->hdq_fck)) {
 605                 dev_dbg(&pdev->dev, "Can't get HDQ clock objects\n");
 606                 if (IS_ERR(hdq_data->hdq_ick)) {
 607                         ret = PTR_ERR(hdq_data->hdq_ick);
 608                         goto err_clk;
 609                 }
 610                 if (IS_ERR(hdq_data->hdq_fck)) {
 611                         ret = PTR_ERR(hdq_data->hdq_fck);
 612                         clk_put(hdq_data->hdq_ick);
 613                         goto err_clk;
 614                 }
 615         }
 616
 617         hdq_data->hdq_usecount = 0;
 618         mutex_init(&hdq_data->hdq_mutex);
 619
 620         if (clk_enable(hdq_data->hdq_ick)) {
 621                 dev_dbg(&pdev->dev, "Can not enable ick\n");
 622                 ret = -ENODEV;
 623                 goto err_ick;
 624         }
 625
 626         if (clk_enable(hdq_data->hdq_fck)) {
 627                 dev_dbg(&pdev->dev, "Can not enable fck\n");
 628                 ret = -ENODEV;
 629                 goto err_fck;
 630         }
 631
 632         rev = hdq_reg_in(hdq_data, OMAP_HDQ_REVISION);
 633         dev_info(&pdev->dev, "OMAP HDQ Hardware Rev %c.%c. Driver in %s mode\n",
 634                 (rev >> 4) + '0', (rev & 0x0f) + '0', "Interrupt");
 635
 636         spin_lock_init(&hdq_data->hdq_spinlock);
 637         omap_hdq_break(hdq_data);
 638
 639         irq = platform_get_irq(pdev, 0);
 640         if (irq < 0) {
 641                 ret = -ENXIO;
 642                 goto err_irq;
 643         }
 644
 645         ret = request_irq(irq, hdq_isr, IRQF_DISABLED, "omap_hdq", hdq_data);
 646         if (ret < 0) {
 647                 dev_dbg(&pdev->dev, "could not request irq\n");
 648                 goto err_irq;
 649         }
 650
 651         /* don't clock the HDQ until it is needed */
 652         clk_disable(hdq_data->hdq_ick);
 653         clk_disable(hdq_data->hdq_fck);
 654
 655         omap_w1_master.data = hdq_data;
 656
 657         ret = w1_add_master_device(&omap_w1_master);
 658         if (ret) {
 659                 dev_dbg(&pdev->dev, "Failure in registering w1 master\n");
 660                 goto err_w1;
 661         }
 662
 663         return 0;
 664
 665 err_w1:
 666 err_irq:
 667         clk_disable(hdq_data->hdq_fck);
 668
 669 err_fck:
 670         clk_disable(hdq_data->hdq_ick);
 671
 672 err_ick:
 673         clk_put(hdq_data->hdq_ick);
 674         clk_put(hdq_data->hdq_fck);
 675
 676 err_clk:
 677         iounmap(hdq_data->hdq_base);
 678
 679 err_ioremap:
 680 err_resource:
 681         platform_set_drvdata(pdev, NULL);
 682         kfree(hdq_data);
 683
 684 err_kmalloc:
 685         return ret;
 686
 687 }
 688
 689 static int omap_hdq_remove(struct platform_device *pdev)
 690 {
 691         struct hdq_data *hdq_data = platform_get_drvdata(pdev);
 692
 693         mutex_lock(&hdq_data->hdq_mutex);
 694
 695         if (0 != hdq_data->hdq_usecount) {
 696                 dev_dbg(&pdev->dev, "removed when use count is not zero\n");
 697                 return -EBUSY;
 698         }
 699
 700         mutex_unlock(&hdq_data->hdq_mutex);
 701
 702         /* remove module dependency */
 703         clk_put(hdq_data->hdq_ick);
 704         clk_put(hdq_data->hdq_fck);
 705         free_irq(INT_24XX_HDQ_IRQ, hdq_data);
 706         platform_set_drvdata(pdev, NULL);
 707         iounmap(hdq_data->hdq_base);
 708         kfree(hdq_data);
 709
 710         return 0;
 711 }
 712
 713 static int __init
 714 omap_hdq_init(void)
 715 {
 716         return platform_driver_register(&omap_hdq_driver);
 717 }
 718
 719 static void __exit
 720 omap_hdq_exit(void)
 721 {
 722         platform_driver_unregister(&omap_hdq_driver);
 723 }
 724
 725 module_init(omap_hdq_init);
 726 module_exit(omap_hdq_exit);
 727
 728 module_param(w1_id, int, S_IRUSR);
 729
 730 MODULE_AUTHOR("Texas Instruments");
 731 MODULE_DESCRIPTION("HDQ driver Library");
 732 MODULE_LICENSE("GPL");