2 * Frame buffer driver for Trident TGUI, Blade and Image series
4 * Copyright 2001, 2002 - Jani Monoses <jani@iv.ro>
7 * CREDITS:(in order of appearance)
8 * skeletonfb.c by Geert Uytterhoeven and other fb code in drivers/video
9 * Special thanks ;) to Mattia Crivellini <tia@mclink.it>
10 * much inspired by the XFree86 4.x Trident driver sources
11 * by Alan Hourihane the FreeVGA project
12 * Francesco Salvestrini <salvestrini@users.sf.net> XP support,
15 * timing value tweaking so it looks good on every monitor in every mode
18 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/pci.h>
23 #include <linux/delay.h>
24 #include <video/vga.h>
25 #include <video/trident.h>
27 #define VERSION "0.7.9-NEWAPI"
29 struct tridentfb_par {
30 void __iomem *io_virt; /* iospace virtual memory address */
34 void (*init_accel) (struct tridentfb_par *, int, int);
35 void (*wait_engine) (struct tridentfb_par *);
37 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
39 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
42 static unsigned char eng_oper; /* engine operation... */
43 static struct fb_ops tridentfb_ops;
45 static struct fb_fix_screeninfo tridentfb_fix = {
47 .type = FB_TYPE_PACKED_PIXELS,
49 .visual = FB_VISUAL_PSEUDOCOLOR,
50 .accel = FB_ACCEL_NONE,
53 /* defaults which are normally overriden by user values */
56 static char *mode_option __devinitdata = "640x480";
57 static int bpp __devinitdata = 8;
59 static int noaccel __devinitdata;
64 static int fp __devinitdata;
65 static int crt __devinitdata;
67 static int memsize __devinitdata;
68 static int memdiff __devinitdata;
71 module_param(mode_option, charp, 0);
72 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
73 module_param_named(mode, mode_option, charp, 0);
74 MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)");
75 module_param(bpp, int, 0);
76 module_param(center, int, 0);
77 module_param(stretch, int, 0);
78 module_param(noaccel, int, 0);
79 module_param(memsize, int, 0);
80 module_param(memdiff, int, 0);
81 module_param(nativex, int, 0);
82 module_param(fp, int, 0);
83 MODULE_PARM_DESC(fp, "Define if flatpanel is connected");
84 module_param(crt, int, 0);
85 MODULE_PARM_DESC(crt, "Define if CRT is connected");
87 static int is_oldclock(int id)
89 return (id == TGUI9440) ||
94 static int is_oldprotect(int id)
96 return (id == TGUI9440) ||
98 (id == PROVIDIA9685) ||
104 static int is_blade(int id)
106 return (id == BLADE3D) ||
107 (id == CYBERBLADEE4) ||
108 (id == CYBERBLADEi7) ||
109 (id == CYBERBLADEi7D) ||
110 (id == CYBERBLADEi1) ||
111 (id == CYBERBLADEi1D) ||
112 (id == CYBERBLADEAi1) ||
113 (id == CYBERBLADEAi1D);
116 static int is_xp(int id)
118 return (id == CYBERBLADEXPAi1) ||
119 (id == CYBERBLADEXPm8) ||
120 (id == CYBERBLADEXPm16);
123 static int is3Dchip(int id)
125 return ((id == BLADE3D) || (id == CYBERBLADEE4) ||
126 (id == CYBERBLADEi7) || (id == CYBERBLADEi7D) ||
127 (id == CYBER9397) || (id == CYBER9397DVD) ||
128 (id == CYBER9520) || (id == CYBER9525DVD) ||
129 (id == IMAGE975) || (id == IMAGE985) ||
130 (id == CYBERBLADEi1) || (id == CYBERBLADEi1D) ||
131 (id == CYBERBLADEAi1) || (id == CYBERBLADEAi1D) ||
132 (id == CYBERBLADEXPm8) || (id == CYBERBLADEXPm16) ||
133 (id == CYBERBLADEXPAi1));
136 static int iscyber(int id)
152 case CYBERBLADEXPAi1:
161 case CYBERBLADEi7: /* VIA MPV4 integrated version */
164 /* case CYBERBLDAEXPm8: Strange */
165 /* case CYBERBLDAEXPm16: Strange */
170 static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg)
172 fb_writeb(val, p->io_virt + reg);
175 static inline u8 t_inb(struct tridentfb_par *p, u16 reg)
177 return fb_readb(p->io_virt + reg);
180 static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v)
182 fb_writel(v, par->io_virt + r);
185 static inline u32 readmmr(struct tridentfb_par *par, u16 r)
187 return fb_readl(par->io_virt + r);
191 * Blade specific acceleration.
194 #define point(x, y) ((y) << 16 | (x))
196 static void blade_init_accel(struct tridentfb_par *par, int pitch, int bpp)
198 int v1 = (pitch >> 3) << 20;
199 int tmp = bpp == 24 ? 2 : (bpp >> 4);
200 int v2 = v1 | (tmp << 29);
202 writemmr(par, 0x21C0, v2);
203 writemmr(par, 0x21C4, v2);
204 writemmr(par, 0x21B8, v2);
205 writemmr(par, 0x21BC, v2);
206 writemmr(par, 0x21D0, v1);
207 writemmr(par, 0x21D4, v1);
208 writemmr(par, 0x21C8, v1);
209 writemmr(par, 0x21CC, v1);
210 writemmr(par, 0x216C, 0);
213 static void blade_wait_engine(struct tridentfb_par *par)
215 while (readmmr(par, STATUS) & 0xFA800000)
219 static void blade_fill_rect(struct tridentfb_par *par,
220 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
222 writemmr(par, COLOR, c);
223 writemmr(par, ROP, rop ? ROP_X : ROP_S);
224 writemmr(par, CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2);
226 writemmr(par, DST1, point(x, y));
227 writemmr(par, DST2, point(x + w - 1, y + h - 1));
230 static void blade_copy_rect(struct tridentfb_par *par,
231 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
234 u32 s1 = point(x1, y1);
235 u32 s2 = point(x1 + w - 1, y1 + h - 1);
236 u32 d1 = point(x2, y2);
237 u32 d2 = point(x2 + w - 1, y2 + h - 1);
239 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
242 writemmr(par, ROP, ROP_S);
243 writemmr(par, CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction);
245 writemmr(par, SRC1, direction ? s2 : s1);
246 writemmr(par, SRC2, direction ? s1 : s2);
247 writemmr(par, DST1, direction ? d2 : d1);
248 writemmr(par, DST2, direction ? d1 : d2);
252 * BladeXP specific acceleration functions
255 static void xp_init_accel(struct tridentfb_par *par, int pitch, int bpp)
257 unsigned char x = bpp == 24 ? 3 : (bpp >> 4);
258 int v1 = pitch << (bpp == 24 ? 20 : (18 + x));
260 switch (pitch << (bpp >> 3)) {
276 t_outb(par, x, 0x2125);
280 writemmr(par, 0x2154, v1);
281 writemmr(par, 0x2150, v1);
282 t_outb(par, 3, 0x2126);
285 static void xp_wait_engine(struct tridentfb_par *par)
291 while (t_inb(par, STATUS) & 0x80) {
293 if (count == 10000000) {
299 t_outb(par, 0x00, STATUS);
307 static void xp_fill_rect(struct tridentfb_par *par,
308 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
310 writemmr(par, 0x2127, ROP_P);
311 writemmr(par, 0x2158, c);
312 writemmr(par, DRAWFL, 0x4000);
313 writemmr(par, OLDDIM, point(h, w));
314 writemmr(par, OLDDST, point(y, x));
315 t_outb(par, 0x01, OLDCMD);
316 t_outb(par, eng_oper, 0x2125);
319 static void xp_copy_rect(struct tridentfb_par *par,
320 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
323 u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
327 if ((x1 < x2) && (y1 == y2)) {
345 writemmr(par, DRAWFL, direction);
346 t_outb(par, ROP_S, 0x2127);
347 writemmr(par, OLDSRC, point(y1_tmp, x1_tmp));
348 writemmr(par, OLDDST, point(y2_tmp, x2_tmp));
349 writemmr(par, OLDDIM, point(h, w));
350 t_outb(par, 0x01, OLDCMD);
354 * Image specific acceleration functions
356 static void image_init_accel(struct tridentfb_par *par, int pitch, int bpp)
358 int tmp = bpp == 24 ? 2: (bpp >> 4);
360 writemmr(par, 0x2120, 0xF0000000);
361 writemmr(par, 0x2120, 0x40000000 | tmp);
362 writemmr(par, 0x2120, 0x80000000);
363 writemmr(par, 0x2144, 0x00000000);
364 writemmr(par, 0x2148, 0x00000000);
365 writemmr(par, 0x2150, 0x00000000);
366 writemmr(par, 0x2154, 0x00000000);
367 writemmr(par, 0x2120, 0x60000000 | (pitch << 16) | pitch);
368 writemmr(par, 0x216C, 0x00000000);
369 writemmr(par, 0x2170, 0x00000000);
370 writemmr(par, 0x217C, 0x00000000);
371 writemmr(par, 0x2120, 0x10000000);
372 writemmr(par, 0x2130, (2047 << 16) | 2047);
375 static void image_wait_engine(struct tridentfb_par *par)
377 while (readmmr(par, 0x2164) & 0xF0000000)
381 static void image_fill_rect(struct tridentfb_par *par,
382 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
384 writemmr(par, 0x2120, 0x80000000);
385 writemmr(par, 0x2120, 0x90000000 | ROP_S);
387 writemmr(par, 0x2144, c);
389 writemmr(par, DST1, point(x, y));
390 writemmr(par, DST2, point(x + w - 1, y + h - 1));
392 writemmr(par, 0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9);
395 static void image_copy_rect(struct tridentfb_par *par,
396 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
399 u32 s1 = point(x1, y1);
400 u32 s2 = point(x1 + w - 1, y1 + h - 1);
401 u32 d1 = point(x2, y2);
402 u32 d2 = point(x2 + w - 1, y2 + h - 1);
404 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
407 writemmr(par, 0x2120, 0x80000000);
408 writemmr(par, 0x2120, 0x90000000 | ROP_S);
410 writemmr(par, SRC1, direction ? s2 : s1);
411 writemmr(par, SRC2, direction ? s1 : s2);
412 writemmr(par, DST1, direction ? d2 : d1);
413 writemmr(par, DST2, direction ? d1 : d2);
414 writemmr(par, 0x2124,
415 0x80000000 | 1 << 22 | 1 << 10 | 1 << 7 | direction);
419 * TGUI 9440/96XX acceleration
422 static void tgui_init_accel(struct tridentfb_par *par, int pitch, int bpp)
424 unsigned char x = bpp == 24 ? 3 : (bpp >> 4);
426 /* disable clipping */
427 writemmr(par, 0x2148, 0);
428 writemmr(par, 0x214C, point(4095, 2047));
430 switch ((pitch * bpp) / 8) {
446 fb_writew(x, par->io_virt + 0x2122);
449 static void tgui_fill_rect(struct tridentfb_par *par,
450 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
452 t_outb(par, ROP_P, 0x2127);
453 writemmr(par, OLDCLR, c);
454 writemmr(par, DRAWFL, 0x4020);
455 writemmr(par, OLDDIM, point(w - 1, h - 1));
456 writemmr(par, OLDDST, point(x, y));
457 t_outb(par, 1, OLDCMD);
460 static void tgui_copy_rect(struct tridentfb_par *par,
461 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
464 u16 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
466 if ((x1 < x2) && (y1 == y2)) {
484 writemmr(par, DRAWFL, 0x4 | flags);
485 t_outb(par, ROP_S, 0x2127);
486 writemmr(par, OLDSRC, point(x1_tmp, y1_tmp));
487 writemmr(par, OLDDST, point(x2_tmp, y2_tmp));
488 writemmr(par, OLDDIM, point(w - 1, h - 1));
489 t_outb(par, 1, OLDCMD);
493 * Accel functions called by the upper layers
495 #ifdef CONFIG_FB_TRIDENT_ACCEL
496 static void tridentfb_fillrect(struct fb_info *info,
497 const struct fb_fillrect *fr)
499 struct tridentfb_par *par = info->par;
502 if (info->var.bits_per_pixel == 8) {
507 col = ((u32 *)(info->pseudo_palette))[fr->color];
509 par->wait_engine(par);
510 par->fill_rect(par, fr->dx, fr->dy, fr->width,
511 fr->height, col, fr->rop);
514 static void tridentfb_copyarea(struct fb_info *info,
515 const struct fb_copyarea *ca)
517 struct tridentfb_par *par = info->par;
519 par->wait_engine(par);
520 par->copy_rect(par, ca->sx, ca->sy, ca->dx, ca->dy,
521 ca->width, ca->height);
524 static int tridentfb_sync(struct fb_info *info)
526 struct tridentfb_par *par = info->par;
528 par->wait_engine(par);
532 #define tridentfb_fillrect cfb_fillrect
533 #define tridentfb_copyarea cfb_copyarea
534 #endif /* CONFIG_FB_TRIDENT_ACCEL */
537 * Hardware access functions
540 static inline unsigned char read3X4(struct tridentfb_par *par, int reg)
542 return vga_mm_rcrt(par->io_virt, reg);
545 static inline void write3X4(struct tridentfb_par *par, int reg,
548 vga_mm_wcrt(par->io_virt, reg, val);
551 static inline unsigned char read3CE(struct tridentfb_par *par,
554 return vga_mm_rgfx(par->io_virt, reg);
557 static inline void writeAttr(struct tridentfb_par *par, int reg,
560 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
561 vga_mm_wattr(par->io_virt, reg, val);
564 static inline void write3CE(struct tridentfb_par *par, int reg,
567 vga_mm_wgfx(par->io_virt, reg, val);
570 static void enable_mmio(void)
575 /* Unprotect registers */
576 vga_io_wseq(NewMode1, 0x80);
580 outb(inb(0x3D5) | 0x01, 0x3D5);
583 static void disable_mmio(struct tridentfb_par *par)
586 vga_mm_rseq(par->io_virt, 0x0B);
588 /* Unprotect registers */
589 vga_mm_wseq(par->io_virt, NewMode1, 0x80);
592 t_outb(par, PCIReg, 0x3D4);
593 t_outb(par, t_inb(par, 0x3D5) & ~0x01, 0x3D5);
596 static void crtc_unlock(struct tridentfb_par *par)
598 write3X4(par, VGA_CRTC_V_SYNC_END,
599 read3X4(par, VGA_CRTC_V_SYNC_END) & 0x7F);
602 /* Return flat panel's maximum x resolution */
603 static int __devinit get_nativex(struct tridentfb_par *par)
610 tmp = (read3CE(par, VertStretch) >> 4) & 3;
631 output("%dx%d flat panel found\n", x, y);
636 static void set_lwidth(struct tridentfb_par *par, int width)
638 write3X4(par, VGA_CRTC_OFFSET, width & 0xFF);
639 write3X4(par, AddColReg,
640 (read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4));
643 /* For resolutions smaller than FP resolution stretch */
644 static void screen_stretch(struct tridentfb_par *par)
646 if (par->chip_id != CYBERBLADEXPAi1)
647 write3CE(par, BiosReg, 0);
649 write3CE(par, BiosReg, 8);
650 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 1);
651 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 1);
654 /* For resolutions smaller than FP resolution center */
655 static void screen_center(struct tridentfb_par *par)
657 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 0x80);
658 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 0x80);
661 /* Address of first shown pixel in display memory */
662 static void set_screen_start(struct tridentfb_par *par, int base)
665 write3X4(par, VGA_CRTC_START_LO, base & 0xFF);
666 write3X4(par, VGA_CRTC_START_HI, (base & 0xFF00) >> 8);
667 tmp = read3X4(par, CRTCModuleTest) & 0xDF;
668 write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11));
669 tmp = read3X4(par, CRTHiOrd) & 0xF8;
670 write3X4(par, CRTHiOrd, tmp | ((base & 0xE0000) >> 17));
673 /* Set dotclock frequency */
674 static void set_vclk(struct tridentfb_par *par, unsigned long freq)
677 unsigned long fi, d, di;
678 unsigned char best_m = 0, best_n = 0, best_k = 0;
679 unsigned char hi, lo;
682 for (k = 1; k >= 0; k--)
683 for (m = 0; m < 32; m++) {
685 for (n = (n < 0 ? 0 : n); n < 122; n++) {
686 fi = ((14318l * (n + 8)) / (m + 2)) >> k;
699 if (is_oldclock(par->chip_id)) {
700 lo = best_n | (best_m << 7);
701 hi = (best_m >> 1) | (best_k << 4);
704 hi = best_m | (best_k << 6);
707 if (is3Dchip(par->chip_id)) {
708 vga_mm_wseq(par->io_virt, ClockHigh, hi);
709 vga_mm_wseq(par->io_virt, ClockLow, lo);
711 t_outb(par, lo, 0x43C8);
712 t_outb(par, hi, 0x43C9);
714 debug("VCLK = %X %X\n", hi, lo);
717 /* Set number of lines for flat panels*/
718 static void set_number_of_lines(struct tridentfb_par *par, int lines)
720 int tmp = read3CE(par, CyberEnhance) & 0x8F;
723 else if (lines > 768)
725 else if (lines > 600)
727 else if (lines > 480)
729 write3CE(par, CyberEnhance, tmp);
733 * If we see that FP is active we assume we have one.
734 * Otherwise we have a CRT display. User can override.
736 static int __devinit is_flatpanel(struct tridentfb_par *par)
740 if (crt || !iscyber(par->chip_id))
742 return (read3CE(par, FPConfig) & 0x10) ? 1 : 0;
745 /* Try detecting the video memory size */
746 static unsigned int __devinit get_memsize(struct tridentfb_par *par)
748 unsigned char tmp, tmp2;
751 /* If memory size provided by user */
755 switch (par->chip_id) {
760 tmp = read3X4(par, SPR) & 0x0F;
776 k = 10 * Mb; /* XP */
782 k = 12 * Mb; /* XP */
785 k = 14 * Mb; /* XP */
788 k = 16 * Mb; /* XP */
792 tmp2 = vga_mm_rseq(par->io_virt, 0xC1);
822 output("framebuffer size = %d Kb\n", k / Kb);
826 /* See if we can handle the video mode described in var */
827 static int tridentfb_check_var(struct fb_var_screeninfo *var,
828 struct fb_info *info)
830 struct tridentfb_par *par = info->par;
831 int bpp = var->bits_per_pixel;
833 int ramdac = 230000; /* 230MHz for most 3D chips */
836 /* check color depth */
838 bpp = var->bits_per_pixel = 32;
839 if (bpp != 8 && bpp != 16 && bpp != 32)
841 if (par->chip_id == TGUI9440 && bpp == 32)
843 /* check whether resolution fits on panel and in memory */
844 if (par->flatpanel && nativex && var->xres > nativex)
846 /* various resolution checks */
847 var->xres = (var->xres + 7) & ~0x7;
848 if (var->xres > var->xres_virtual)
849 var->xres_virtual = var->xres;
850 if (var->yres > var->yres_virtual)
851 var->yres_virtual = var->yres;
852 if (var->xres_virtual > 4095 || var->yres > 2048)
854 /* prevent from position overflow for acceleration */
855 if (var->yres_virtual > 0xffff)
857 line_length = var->xres_virtual * bpp / 8;
858 #ifdef CONFIG_FB_TRIDENT_ACCEL
859 if (!is3Dchip(par->chip_id)) {
860 /* acceleration requires line length to be power of 2 */
861 if (line_length <= 512)
862 var->xres_virtual = 512 * 8 / bpp;
863 else if (line_length <= 1024)
864 var->xres_virtual = 1024 * 8 / bpp;
865 else if (line_length <= 2048)
866 var->xres_virtual = 2048 * 8 / bpp;
867 else if (line_length <= 4096)
868 var->xres_virtual = 4096 * 8 / bpp;
869 else if (line_length <= 8192)
870 var->xres_virtual = 8192 * 8 / bpp;
874 line_length = var->xres_virtual * bpp / 8;
877 if (var->yres > var->yres_virtual)
878 var->yres_virtual = var->yres;
879 if (line_length * var->yres_virtual > info->fix.smem_len)
885 var->green.offset = 0;
886 var->blue.offset = 0;
888 var->green.length = 6;
889 var->blue.length = 6;
892 var->red.offset = 11;
893 var->green.offset = 5;
894 var->blue.offset = 0;
896 var->green.length = 6;
897 var->blue.length = 5;
900 var->red.offset = 16;
901 var->green.offset = 8;
902 var->blue.offset = 0;
904 var->green.length = 8;
905 var->blue.length = 8;
911 if (is_xp(par->chip_id))
914 switch (par->chip_id) {
916 ramdac = (bpp >= 16) ? 45000 : 90000;
930 /* The clock is doubled for 32 bpp */
934 if (PICOS2KHZ(var->pixclock) > ramdac)
943 /* Pan the display */
944 static int tridentfb_pan_display(struct fb_var_screeninfo *var,
945 struct fb_info *info)
947 struct tridentfb_par *par = info->par;
951 offset = (var->xoffset + (var->yoffset * var->xres_virtual))
952 * var->bits_per_pixel / 32;
953 info->var.xoffset = var->xoffset;
954 info->var.yoffset = var->yoffset;
955 set_screen_start(par, offset);
960 static void shadowmode_on(struct tridentfb_par *par)
962 write3CE(par, CyberControl, read3CE(par, CyberControl) | 0x81);
965 static void shadowmode_off(struct tridentfb_par *par)
967 write3CE(par, CyberControl, read3CE(par, CyberControl) & 0x7E);
970 /* Set the hardware to the requested video mode */
971 static int tridentfb_set_par(struct fb_info *info)
973 struct tridentfb_par *par = (struct tridentfb_par *)(info->par);
974 u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart, hblankend;
975 u32 vtotal, vdispend, vsyncstart, vsyncend, vblankstart, vblankend;
976 struct fb_var_screeninfo *var = &info->var;
977 int bpp = var->bits_per_pixel;
982 hdispend = var->xres / 8 - 1;
983 hsyncstart = (var->xres + var->right_margin) / 8;
984 hsyncend = (var->xres + var->right_margin + var->hsync_len) / 8;
985 htotal = (var->xres + var->left_margin + var->right_margin +
986 var->hsync_len) / 8 - 5;
987 hblankstart = hdispend + 1;
988 hblankend = htotal + 3;
990 vdispend = var->yres - 1;
991 vsyncstart = var->yres + var->lower_margin;
992 vsyncend = vsyncstart + var->vsync_len;
993 vtotal = var->upper_margin + vsyncend - 2;
994 vblankstart = vdispend + 1;
997 if (info->var.vmode & FB_VMODE_INTERLACED) {
1007 write3CE(par, CyberControl, 8);
1009 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
1011 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
1014 if (par->flatpanel && var->xres < nativex) {
1016 * on flat panels with native size larger
1017 * than requested resolution decide whether
1018 * we stretch or center
1020 t_outb(par, tmp | 0xC0, VGA_MIS_W);
1027 screen_stretch(par);
1030 t_outb(par, tmp, VGA_MIS_W);
1031 write3CE(par, CyberControl, 8);
1034 /* vertical timing values */
1035 write3X4(par, VGA_CRTC_V_TOTAL, vtotal & 0xFF);
1036 write3X4(par, VGA_CRTC_V_DISP_END, vdispend & 0xFF);
1037 write3X4(par, VGA_CRTC_V_SYNC_START, vsyncstart & 0xFF);
1038 write3X4(par, VGA_CRTC_V_SYNC_END, (vsyncend & 0x0F));
1039 write3X4(par, VGA_CRTC_V_BLANK_START, vblankstart & 0xFF);
1040 write3X4(par, VGA_CRTC_V_BLANK_END, vblankend & 0xFF);
1042 /* horizontal timing values */
1043 write3X4(par, VGA_CRTC_H_TOTAL, htotal & 0xFF);
1044 write3X4(par, VGA_CRTC_H_DISP, hdispend & 0xFF);
1045 write3X4(par, VGA_CRTC_H_SYNC_START, hsyncstart & 0xFF);
1046 write3X4(par, VGA_CRTC_H_SYNC_END,
1047 (hsyncend & 0x1F) | ((hblankend & 0x20) << 2));
1048 write3X4(par, VGA_CRTC_H_BLANK_START, hblankstart & 0xFF);
1049 write3X4(par, VGA_CRTC_H_BLANK_END, hblankend & 0x1F);
1051 /* higher bits of vertical timing values */
1053 if (vtotal & 0x100) tmp |= 0x01;
1054 if (vdispend & 0x100) tmp |= 0x02;
1055 if (vsyncstart & 0x100) tmp |= 0x04;
1056 if (vblankstart & 0x100) tmp |= 0x08;
1058 if (vtotal & 0x200) tmp |= 0x20;
1059 if (vdispend & 0x200) tmp |= 0x40;
1060 if (vsyncstart & 0x200) tmp |= 0x80;
1061 write3X4(par, VGA_CRTC_OVERFLOW, tmp);
1063 tmp = read3X4(par, CRTHiOrd) & 0x07;
1064 tmp |= 0x08; /* line compare bit 10 */
1065 if (vtotal & 0x400) tmp |= 0x80;
1066 if (vblankstart & 0x400) tmp |= 0x40;
1067 if (vsyncstart & 0x400) tmp |= 0x20;
1068 if (vdispend & 0x400) tmp |= 0x10;
1069 write3X4(par, CRTHiOrd, tmp);
1071 tmp = (htotal >> 8) & 0x01;
1072 tmp |= (hdispend >> 7) & 0x02;
1073 tmp |= (hsyncstart >> 5) & 0x08;
1074 tmp |= (hblankstart >> 4) & 0x10;
1075 write3X4(par, HorizOverflow, tmp);
1078 if (vblankstart & 0x200) tmp |= 0x20;
1079 //FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */
1080 write3X4(par, VGA_CRTC_MAX_SCAN, tmp);
1082 write3X4(par, VGA_CRTC_LINE_COMPARE, 0xFF);
1083 write3X4(par, VGA_CRTC_PRESET_ROW, 0);
1084 write3X4(par, VGA_CRTC_MODE, 0xC3);
1086 write3X4(par, LinearAddReg, 0x20); /* enable linear addressing */
1088 tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84 : 0x80;
1089 /* enable access extended memory */
1090 write3X4(par, CRTCModuleTest, tmp);
1091 tmp = read3CE(par, MiscIntContReg) & ~0x4;
1092 if (info->var.vmode & FB_VMODE_INTERLACED)
1094 write3CE(par, MiscIntContReg, tmp);
1096 /* enable GE for text acceleration */
1097 write3X4(par, GraphEngReg, 0x80);
1114 write3X4(par, PixelBusReg, tmp);
1116 tmp = read3X4(par, DRAMControl);
1117 if (!is_oldprotect(par->chip_id))
1119 if (iscyber(par->chip_id))
1121 write3X4(par, DRAMControl, tmp); /* both IO, linear enable */
1123 write3X4(par, InterfaceSel, read3X4(par, InterfaceSel) | 0x40);
1124 if (!is_xp(par->chip_id))
1125 write3X4(par, Performance, read3X4(par, Performance) | 0x10);
1126 /* MMIO & PCI read and write burst enable */
1127 if (par->chip_id != TGUI9440)
1128 write3X4(par, PCIReg, read3X4(par, PCIReg) | 0x06);
1130 vga_mm_wseq(par->io_virt, 0, 3);
1131 vga_mm_wseq(par->io_virt, 1, 1); /* set char clock 8 dots wide */
1132 /* enable 4 maps because needed in chain4 mode */
1133 vga_mm_wseq(par->io_virt, 2, 0x0F);
1134 vga_mm_wseq(par->io_virt, 3, 0);
1135 vga_mm_wseq(par->io_virt, 4, 0x0E); /* memory mode enable bitmaps ?? */
1137 /* convert from picoseconds to kHz */
1138 vclk = PICOS2KHZ(info->var.pixclock);
1140 /* divide clock by 2 if 32bpp chain4 mode display and CPU path */
1141 tmp = read3CE(par, MiscExtFunc) & 0xF0;
1142 if (bpp == 32 || (par->chip_id == TGUI9440 && bpp == 16)) {
1146 set_vclk(par, vclk);
1147 write3CE(par, MiscExtFunc, tmp | 0x12);
1148 write3CE(par, 0x5, 0x40); /* no CGA compat, allow 256 col */
1149 write3CE(par, 0x6, 0x05); /* graphics mode */
1150 write3CE(par, 0x7, 0x0F); /* planes? */
1152 if (par->chip_id == CYBERBLADEXPAi1) {
1153 /* This fixes snow-effect in 32 bpp */
1154 write3X4(par, VGA_CRTC_H_SYNC_START, 0x84);
1157 /* graphics mode and support 256 color modes */
1158 writeAttr(par, 0x10, 0x41);
1159 writeAttr(par, 0x12, 0x0F); /* planes */
1160 writeAttr(par, 0x13, 0); /* horizontal pel panning */
1163 for (tmp = 0; tmp < 0x10; tmp++)
1164 writeAttr(par, tmp, tmp);
1165 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
1166 t_outb(par, 0x20, VGA_ATT_W); /* enable attr */
1181 t_inb(par, VGA_PEL_IW);
1182 t_inb(par, VGA_PEL_MSK);
1183 t_inb(par, VGA_PEL_MSK);
1184 t_inb(par, VGA_PEL_MSK);
1185 t_inb(par, VGA_PEL_MSK);
1186 t_outb(par, tmp, VGA_PEL_MSK);
1187 t_inb(par, VGA_PEL_IW);
1190 set_number_of_lines(par, info->var.yres);
1191 info->fix.line_length = info->var.xres_virtual * bpp / 8;
1192 set_lwidth(par, info->fix.line_length / 8);
1193 #ifdef CONFIG_FB_TRIDENT_ACCEL
1194 par->init_accel(par, info->var.xres_virtual, bpp);
1197 info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1198 info->cmap.len = (bpp == 8) ? 256 : 16;
1203 /* Set one color register */
1204 static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1205 unsigned blue, unsigned transp,
1206 struct fb_info *info)
1208 int bpp = info->var.bits_per_pixel;
1209 struct tridentfb_par *par = info->par;
1211 if (regno >= info->cmap.len)
1215 t_outb(par, 0xFF, VGA_PEL_MSK);
1216 t_outb(par, regno, VGA_PEL_IW);
1218 t_outb(par, red >> 10, VGA_PEL_D);
1219 t_outb(par, green >> 10, VGA_PEL_D);
1220 t_outb(par, blue >> 10, VGA_PEL_D);
1222 } else if (regno < 16) {
1223 if (bpp == 16) { /* RGB 565 */
1226 col = (red & 0xF800) | ((green & 0xFC00) >> 5) |
1227 ((blue & 0xF800) >> 11);
1229 ((u32 *)(info->pseudo_palette))[regno] = col;
1230 } else if (bpp == 32) /* ARGB 8888 */
1231 ((u32*)info->pseudo_palette)[regno] =
1232 ((transp & 0xFF00) << 16) |
1233 ((red & 0xFF00) << 8) |
1234 ((green & 0xFF00)) |
1235 ((blue & 0xFF00) >> 8);
1238 /* debug("exit\n"); */
1242 /* Try blanking the screen.For flat panels it does nothing */
1243 static int tridentfb_blank(int blank_mode, struct fb_info *info)
1245 unsigned char PMCont, DPMSCont;
1246 struct tridentfb_par *par = info->par;
1251 t_outb(par, 0x04, 0x83C8); /* Read DPMS Control */
1252 PMCont = t_inb(par, 0x83C6) & 0xFC;
1253 DPMSCont = read3CE(par, PowerStatus) & 0xFC;
1254 switch (blank_mode) {
1255 case FB_BLANK_UNBLANK:
1256 /* Screen: On, HSync: On, VSync: On */
1257 case FB_BLANK_NORMAL:
1258 /* Screen: Off, HSync: On, VSync: On */
1262 case FB_BLANK_HSYNC_SUSPEND:
1263 /* Screen: Off, HSync: Off, VSync: On */
1267 case FB_BLANK_VSYNC_SUSPEND:
1268 /* Screen: Off, HSync: On, VSync: Off */
1272 case FB_BLANK_POWERDOWN:
1273 /* Screen: Off, HSync: Off, VSync: Off */
1279 write3CE(par, PowerStatus, DPMSCont);
1280 t_outb(par, 4, 0x83C8);
1281 t_outb(par, PMCont, 0x83C6);
1285 /* let fbcon do a softblank for us */
1286 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1289 static struct fb_ops tridentfb_ops = {
1290 .owner = THIS_MODULE,
1291 .fb_setcolreg = tridentfb_setcolreg,
1292 .fb_pan_display = tridentfb_pan_display,
1293 .fb_blank = tridentfb_blank,
1294 .fb_check_var = tridentfb_check_var,
1295 .fb_set_par = tridentfb_set_par,
1296 .fb_fillrect = tridentfb_fillrect,
1297 .fb_copyarea = tridentfb_copyarea,
1298 .fb_imageblit = cfb_imageblit,
1299 #ifdef CONFIG_FB_TRIDENT_ACCEL
1300 .fb_sync = tridentfb_sync,
1304 static int __devinit trident_pci_probe(struct pci_dev *dev,
1305 const struct pci_device_id *id)
1308 unsigned char revision;
1309 struct fb_info *info;
1310 struct tridentfb_par *default_par;
1314 err = pci_enable_device(dev);
1318 info = framebuffer_alloc(sizeof(struct tridentfb_par), &dev->dev);
1321 default_par = info->par;
1323 chip_id = id->device;
1325 if (chip_id == CYBERBLADEi1)
1326 output("*** Please do use cyblafb, Cyberblade/i1 support "
1327 "will soon be removed from tridentfb!\n");
1330 /* If PCI id is 0x9660 then further detect chip type */
1332 if (chip_id == TGUI9660) {
1333 revision = vga_io_rseq(RevisionID);
1337 chip_id = PROVIDIA9685;
1341 chip_id = CYBER9397;
1344 chip_id = CYBER9397DVD;
1353 chip_id = CYBER9385;
1356 chip_id = CYBER9382;
1359 chip_id = CYBER9388;
1366 chip3D = is3Dchip(chip_id);
1368 if (is_xp(chip_id)) {
1369 default_par->init_accel = xp_init_accel;
1370 default_par->wait_engine = xp_wait_engine;
1371 default_par->fill_rect = xp_fill_rect;
1372 default_par->copy_rect = xp_copy_rect;
1373 } else if (is_blade(chip_id)) {
1374 default_par->init_accel = blade_init_accel;
1375 default_par->wait_engine = blade_wait_engine;
1376 default_par->fill_rect = blade_fill_rect;
1377 default_par->copy_rect = blade_copy_rect;
1378 } else if (chip3D) { /* 3DImage family left */
1379 default_par->init_accel = image_init_accel;
1380 default_par->wait_engine = image_wait_engine;
1381 default_par->fill_rect = image_fill_rect;
1382 default_par->copy_rect = image_copy_rect;
1383 } else { /* TGUI 9440/96XX family */
1384 default_par->init_accel = tgui_init_accel;
1385 default_par->wait_engine = xp_wait_engine;
1386 default_par->fill_rect = tgui_fill_rect;
1387 default_par->copy_rect = tgui_copy_rect;
1390 default_par->chip_id = chip_id;
1392 /* setup MMIO region */
1393 tridentfb_fix.mmio_start = pci_resource_start(dev, 1);
1394 tridentfb_fix.mmio_len = chip3D ? 0x20000 : 0x10000;
1396 if (!request_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len, "tridentfb")) {
1397 debug("request_region failed!\n");
1398 framebuffer_release(info);
1402 default_par->io_virt = ioremap_nocache(tridentfb_fix.mmio_start,
1403 tridentfb_fix.mmio_len);
1405 if (!default_par->io_virt) {
1406 debug("ioremap failed\n");
1413 /* setup framebuffer memory */
1414 tridentfb_fix.smem_start = pci_resource_start(dev, 0);
1415 tridentfb_fix.smem_len = get_memsize(default_par);
1417 if (!request_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len, "tridentfb")) {
1418 debug("request_mem_region failed!\n");
1419 disable_mmio(info->par);
1424 info->screen_base = ioremap_nocache(tridentfb_fix.smem_start,
1425 tridentfb_fix.smem_len);
1427 if (!info->screen_base) {
1428 debug("ioremap failed\n");
1433 output("%s board found\n", pci_name(dev));
1434 default_par->flatpanel = is_flatpanel(default_par);
1436 if (default_par->flatpanel)
1437 nativex = get_nativex(default_par);
1439 info->fix = tridentfb_fix;
1440 info->fbops = &tridentfb_ops;
1441 info->pseudo_palette = default_par->pseudo_pal;
1443 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1444 #ifdef CONFIG_FB_TRIDENT_ACCEL
1445 info->flags |= FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT;
1447 if (!fb_find_mode(&info->var, info,
1448 mode_option, NULL, 0, NULL, bpp)) {
1452 err = fb_alloc_cmap(&info->cmap, 256, 0);
1456 if (!noaccel && default_par->init_accel)
1457 info->var.accel_flags |= FB_ACCELF_TEXT;
1459 info->var.accel_flags &= ~FB_ACCELF_TEXT;
1460 info->var.activate |= FB_ACTIVATE_NOW;
1461 info->device = &dev->dev;
1462 if (register_framebuffer(info) < 0) {
1463 printk(KERN_ERR "tridentfb: could not register Trident framebuffer\n");
1464 fb_dealloc_cmap(&info->cmap);
1468 output("fb%d: %s frame buffer device %dx%d-%dbpp\n",
1469 info->node, info->fix.id, info->var.xres,
1470 info->var.yres, info->var.bits_per_pixel);
1472 pci_set_drvdata(dev, info);
1476 if (info->screen_base)
1477 iounmap(info->screen_base);
1478 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1479 disable_mmio(info->par);
1481 if (default_par->io_virt)
1482 iounmap(default_par->io_virt);
1483 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1484 framebuffer_release(info);
1488 static void __devexit trident_pci_remove(struct pci_dev *dev)
1490 struct fb_info *info = pci_get_drvdata(dev);
1491 struct tridentfb_par *par = info->par;
1493 unregister_framebuffer(info);
1494 iounmap(par->io_virt);
1495 iounmap(info->screen_base);
1496 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1497 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1498 pci_set_drvdata(dev, NULL);
1499 framebuffer_release(info);
1502 /* List of boards that we are trying to support */
1503 static struct pci_device_id trident_devices[] = {
1504 {PCI_VENDOR_ID_TRIDENT, BLADE3D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1505 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1506 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1507 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1508 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1509 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1510 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1511 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEE4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1512 {PCI_VENDOR_ID_TRIDENT, TGUI9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1513 {PCI_VENDOR_ID_TRIDENT, TGUI9660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1514 {PCI_VENDOR_ID_TRIDENT, IMAGE975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1515 {PCI_VENDOR_ID_TRIDENT, IMAGE985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1516 {PCI_VENDOR_ID_TRIDENT, CYBER9320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1517 {PCI_VENDOR_ID_TRIDENT, CYBER9388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1518 {PCI_VENDOR_ID_TRIDENT, CYBER9520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1519 {PCI_VENDOR_ID_TRIDENT, CYBER9525DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1520 {PCI_VENDOR_ID_TRIDENT, CYBER9397, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1521 {PCI_VENDOR_ID_TRIDENT, CYBER9397DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1522 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1523 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1524 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm16, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1528 MODULE_DEVICE_TABLE(pci, trident_devices);
1530 static struct pci_driver tridentfb_pci_driver = {
1531 .name = "tridentfb",
1532 .id_table = trident_devices,
1533 .probe = trident_pci_probe,
1534 .remove = __devexit_p(trident_pci_remove)
1538 * Parse user specified options (`video=trident:')
1540 * video=trident:800x600,bpp=16,noaccel
1543 static int __init tridentfb_setup(char *options)
1546 if (!options || !*options)
1548 while ((opt = strsep(&options, ",")) != NULL) {
1551 if (!strncmp(opt, "noaccel", 7))
1553 else if (!strncmp(opt, "fp", 2))
1555 else if (!strncmp(opt, "crt", 3))
1557 else if (!strncmp(opt, "bpp=", 4))
1558 bpp = simple_strtoul(opt + 4, NULL, 0);
1559 else if (!strncmp(opt, "center", 6))
1561 else if (!strncmp(opt, "stretch", 7))
1563 else if (!strncmp(opt, "memsize=", 8))
1564 memsize = simple_strtoul(opt + 8, NULL, 0);
1565 else if (!strncmp(opt, "memdiff=", 8))
1566 memdiff = simple_strtoul(opt + 8, NULL, 0);
1567 else if (!strncmp(opt, "nativex=", 8))
1568 nativex = simple_strtoul(opt + 8, NULL, 0);
1576 static int __init tridentfb_init(void)
1579 char *option = NULL;
1581 if (fb_get_options("tridentfb", &option))
1583 tridentfb_setup(option);
1585 output("Trident framebuffer %s initializing\n", VERSION);
1586 return pci_register_driver(&tridentfb_pci_driver);
1589 static void __exit tridentfb_exit(void)
1591 pci_unregister_driver(&tridentfb_pci_driver);
1594 module_init(tridentfb_init);
1595 module_exit(tridentfb_exit);
1597 MODULE_AUTHOR("Jani Monoses <jani@iv.ro>");
1598 MODULE_DESCRIPTION("Framebuffer driver for Trident cards");
1599 MODULE_LICENSE("GPL");