2 * Frame buffer driver for Trident Blade and Image series
4 * Copyright 2001, 2002 - Jani Monoses <jani@iv.ro>
7 * CREDITS:(in order of appearance)
8 * skeletonfb.c by Geert Uytterhoeven and other fb code in drivers/video
9 * Special thanks ;) to Mattia Crivellini <tia@mclink.it>
10 * much inspired by the XFree86 4.x Trident driver sources
11 * by Alan Hourihane the FreeVGA project
12 * Francesco Salvestrini <salvestrini@users.sf.net> XP support,
15 * timing value tweaking so it looks good on every monitor in every mode
19 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/pci.h>
24 #include <linux/delay.h>
25 #include <video/vga.h>
26 #include <video/trident.h>
28 #define VERSION "0.7.9-NEWAPI"
30 struct tridentfb_par {
31 void __iomem *io_virt; /* iospace virtual memory address */
35 void (*init_accel) (struct tridentfb_par *, int, int);
36 void (*wait_engine) (struct tridentfb_par *);
38 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
40 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
43 static unsigned char eng_oper; /* engine operation... */
44 static struct fb_ops tridentfb_ops;
46 static struct fb_fix_screeninfo tridentfb_fix = {
48 .type = FB_TYPE_PACKED_PIXELS,
50 .visual = FB_VISUAL_PSEUDOCOLOR,
51 .accel = FB_ACCEL_NONE,
54 /* defaults which are normally overriden by user values */
57 static char *mode_option __devinitdata = "640x480";
58 static int bpp __devinitdata = 8;
60 static int noaccel __devinitdata;
65 static int fp __devinitdata;
66 static int crt __devinitdata;
68 static int memsize __devinitdata;
69 static int memdiff __devinitdata;
72 module_param(mode_option, charp, 0);
73 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
74 module_param_named(mode, mode_option, charp, 0);
75 MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)");
76 module_param(bpp, int, 0);
77 module_param(center, int, 0);
78 module_param(stretch, int, 0);
79 module_param(noaccel, int, 0);
80 module_param(memsize, int, 0);
81 module_param(memdiff, int, 0);
82 module_param(nativex, int, 0);
83 module_param(fp, int, 0);
84 MODULE_PARM_DESC(fp, "Define if flatpanel is connected");
85 module_param(crt, int, 0);
86 MODULE_PARM_DESC(crt, "Define if CRT is connected");
88 static int is_oldclock(int id)
90 return (id == TGUI9440) ||
95 static int is_oldprotect(int id)
97 return (id == TGUI9440) ||
99 (id == PROVIDIA9685) ||
105 static int is_blade(int id)
107 return (id == BLADE3D) ||
108 (id == CYBERBLADEE4) ||
109 (id == CYBERBLADEi7) ||
110 (id == CYBERBLADEi7D) ||
111 (id == CYBERBLADEi1) ||
112 (id == CYBERBLADEi1D) ||
113 (id == CYBERBLADEAi1) ||
114 (id == CYBERBLADEAi1D);
117 static int is_xp(int id)
119 return (id == CYBERBLADEXPAi1) ||
120 (id == CYBERBLADEXPm8) ||
121 (id == CYBERBLADEXPm16);
124 static int is3Dchip(int id)
126 return ((id == BLADE3D) || (id == CYBERBLADEE4) ||
127 (id == CYBERBLADEi7) || (id == CYBERBLADEi7D) ||
128 (id == CYBER9397) || (id == CYBER9397DVD) ||
129 (id == CYBER9520) || (id == CYBER9525DVD) ||
130 (id == IMAGE975) || (id == IMAGE985) ||
131 (id == CYBERBLADEi1) || (id == CYBERBLADEi1D) ||
132 (id == CYBERBLADEAi1) || (id == CYBERBLADEAi1D) ||
133 (id == CYBERBLADEXPm8) || (id == CYBERBLADEXPm16) ||
134 (id == CYBERBLADEXPAi1));
137 static int iscyber(int id)
153 case CYBERBLADEXPAi1:
162 case CYBERBLADEi7: /* VIA MPV4 integrated version */
165 /* case CYBERBLDAEXPm8: Strange */
166 /* case CYBERBLDAEXPm16: Strange */
171 static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg)
173 fb_writeb(val, p->io_virt + reg);
176 static inline u8 t_inb(struct tridentfb_par *p, u16 reg)
178 return fb_readb(p->io_virt + reg);
181 static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v)
183 fb_writel(v, par->io_virt + r);
186 static inline u32 readmmr(struct tridentfb_par *par, u16 r)
188 return fb_readl(par->io_virt + r);
192 * Blade specific acceleration.
195 #define point(x, y) ((y) << 16 | (x))
207 static void blade_init_accel(struct tridentfb_par *par, int pitch, int bpp)
209 int v1 = (pitch >> 3) << 20;
226 v2 = v1 | (tmp << 29);
227 writemmr(par, 0x21C0, v2);
228 writemmr(par, 0x21C4, v2);
229 writemmr(par, 0x21B8, v2);
230 writemmr(par, 0x21BC, v2);
231 writemmr(par, 0x21D0, v1);
232 writemmr(par, 0x21D4, v1);
233 writemmr(par, 0x21C8, v1);
234 writemmr(par, 0x21CC, v1);
235 writemmr(par, 0x216C, 0);
238 static void blade_wait_engine(struct tridentfb_par *par)
240 while (readmmr(par, STA) & 0xFA800000) ;
243 static void blade_fill_rect(struct tridentfb_par *par,
244 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
246 writemmr(par, CLR, c);
247 writemmr(par, ROP, rop ? 0x66 : ROP_S);
248 writemmr(par, CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2);
250 writemmr(par, DR1, point(x, y));
251 writemmr(par, DR2, point(x + w - 1, y + h - 1));
254 static void blade_copy_rect(struct tridentfb_par *par,
255 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
260 s2 = point(x1 + w - 1, y1 + h - 1);
262 d2 = point(x2 + w - 1, y2 + h - 1);
264 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
267 writemmr(par, ROP, ROP_S);
268 writemmr(par, CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction);
270 writemmr(par, SR1, direction ? s2 : s1);
271 writemmr(par, SR2, direction ? s1 : s2);
272 writemmr(par, DR1, direction ? d2 : d1);
273 writemmr(par, DR2, direction ? d1 : d2);
277 * BladeXP specific acceleration functions
281 #define masked_point(x, y) ((y & 0xffff)<<16|(x & 0xffff))
283 static void xp_init_accel(struct tridentfb_par *par, int pitch, int bpp)
303 switch (pitch << (bpp >> 3)) {
319 t_outb(par, x, 0x2125);
339 writemmr(par, 0x2154, v1);
340 writemmr(par, 0x2150, v1);
341 t_outb(par, 3, 0x2126);
344 static void xp_wait_engine(struct tridentfb_par *par)
352 busy = t_inb(par, STA) & 0x80;
356 if (count == 10000000) {
362 t_outb(par, 0x00, 0x2120);
369 static void xp_fill_rect(struct tridentfb_par *par,
370 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
372 writemmr(par, 0x2127, ROP_P);
373 writemmr(par, 0x2158, c);
374 writemmr(par, 0x2128, 0x4000);
375 writemmr(par, 0x2140, masked_point(h, w));
376 writemmr(par, 0x2138, masked_point(y, x));
377 t_outb(par, 0x01, 0x2124);
378 t_outb(par, eng_oper, 0x2125);
381 static void xp_copy_rect(struct tridentfb_par *par,
382 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
385 u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
389 if ((x1 < x2) && (y1 == y2)) {
407 writemmr(par, 0x2128, direction);
408 t_outb(par, ROP_S, 0x2127);
409 writemmr(par, 0x213C, masked_point(y1_tmp, x1_tmp));
410 writemmr(par, 0x2138, masked_point(y2_tmp, x2_tmp));
411 writemmr(par, 0x2140, masked_point(h, w));
412 t_outb(par, 0x01, 0x2124);
416 * Image specific acceleration functions
418 static void image_init_accel(struct tridentfb_par *par, int pitch, int bpp)
436 writemmr(par, 0x2120, 0xF0000000);
437 writemmr(par, 0x2120, 0x40000000 | tmp);
438 writemmr(par, 0x2120, 0x80000000);
439 writemmr(par, 0x2144, 0x00000000);
440 writemmr(par, 0x2148, 0x00000000);
441 writemmr(par, 0x2150, 0x00000000);
442 writemmr(par, 0x2154, 0x00000000);
443 writemmr(par, 0x2120, 0x60000000 | (pitch << 16) | pitch);
444 writemmr(par, 0x216C, 0x00000000);
445 writemmr(par, 0x2170, 0x00000000);
446 writemmr(par, 0x217C, 0x00000000);
447 writemmr(par, 0x2120, 0x10000000);
448 writemmr(par, 0x2130, (2047 << 16) | 2047);
451 static void image_wait_engine(struct tridentfb_par *par)
453 while (readmmr(par, 0x2164) & 0xF0000000) ;
456 static void image_fill_rect(struct tridentfb_par *par,
457 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
459 writemmr(par, 0x2120, 0x80000000);
460 writemmr(par, 0x2120, 0x90000000 | ROP_S);
462 writemmr(par, 0x2144, c);
464 writemmr(par, DR1, point(x, y));
465 writemmr(par, DR2, point(x + w - 1, y + h - 1));
467 writemmr(par, 0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9);
470 static void image_copy_rect(struct tridentfb_par *par,
471 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
476 s2 = point(x1 + w - 1, y1 + h - 1);
478 d2 = point(x2 + w - 1, y2 + h - 1);
480 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
483 writemmr(par, 0x2120, 0x80000000);
484 writemmr(par, 0x2120, 0x90000000 | ROP_S);
486 writemmr(par, SR1, direction ? s2 : s1);
487 writemmr(par, SR2, direction ? s1 : s2);
488 writemmr(par, DR1, direction ? d2 : d1);
489 writemmr(par, DR2, direction ? d1 : d2);
490 writemmr(par, 0x2124,
491 0x80000000 | 1 << 22 | 1 << 10 | 1 << 7 | direction);
495 * Accel functions called by the upper layers
497 #ifdef CONFIG_FB_TRIDENT_ACCEL
498 static void tridentfb_fillrect(struct fb_info *info,
499 const struct fb_fillrect *fr)
501 struct tridentfb_par *par = info->par;
502 int bpp = info->var.bits_per_pixel;
513 col = ((u32 *)(info->pseudo_palette))[fr->color];
516 col = ((u32 *)(info->pseudo_palette))[fr->color];
520 par->fill_rect(par, fr->dx, fr->dy, fr->width,
521 fr->height, col, fr->rop);
522 par->wait_engine(par);
524 static void tridentfb_copyarea(struct fb_info *info,
525 const struct fb_copyarea *ca)
527 struct tridentfb_par *par = info->par;
529 par->copy_rect(par, ca->sx, ca->sy, ca->dx, ca->dy,
530 ca->width, ca->height);
531 par->wait_engine(par);
533 #else /* !CONFIG_FB_TRIDENT_ACCEL */
534 #define tridentfb_fillrect cfb_fillrect
535 #define tridentfb_copyarea cfb_copyarea
536 #endif /* CONFIG_FB_TRIDENT_ACCEL */
540 * Hardware access functions
543 static inline unsigned char read3X4(struct tridentfb_par *par, int reg)
545 return vga_mm_rcrt(par->io_virt, reg);
548 static inline void write3X4(struct tridentfb_par *par, int reg,
551 vga_mm_wcrt(par->io_virt, reg, val);
554 static inline unsigned char read3CE(struct tridentfb_par *par,
557 return vga_mm_rgfx(par->io_virt, reg);
560 static inline void writeAttr(struct tridentfb_par *par, int reg,
563 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
564 vga_mm_wattr(par->io_virt, reg, val);
567 static inline void write3CE(struct tridentfb_par *par, int reg,
570 vga_mm_wgfx(par->io_virt, reg, val);
573 static void enable_mmio(void)
578 /* Unprotect registers */
579 vga_io_wseq(NewMode1, 0x80);
583 outb(inb(0x3D5) | 0x01, 0x3D5);
586 static void disable_mmio(struct tridentfb_par *par)
589 vga_mm_rseq(par->io_virt, 0x0B);
591 /* Unprotect registers */
592 vga_mm_wseq(par->io_virt, NewMode1, 0x80);
595 t_outb(par, PCIReg, 0x3D4);
596 t_outb(par, t_inb(par, 0x3D5) & ~0x01, 0x3D5);
599 static void crtc_unlock(struct tridentfb_par *par)
601 write3X4(par, VGA_CRTC_V_SYNC_END,
602 read3X4(par, VGA_CRTC_V_SYNC_END) & 0x7F);
605 /* Return flat panel's maximum x resolution */
606 static int __devinit get_nativex(struct tridentfb_par *par)
613 tmp = (read3CE(par, VertStretch) >> 4) & 3;
634 output("%dx%d flat panel found\n", x, y);
639 static void set_lwidth(struct tridentfb_par *par, int width)
641 write3X4(par, VGA_CRTC_OFFSET, width & 0xFF);
642 write3X4(par, AddColReg,
643 (read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4));
646 /* For resolutions smaller than FP resolution stretch */
647 static void screen_stretch(struct tridentfb_par *par)
649 if (par->chip_id != CYBERBLADEXPAi1)
650 write3CE(par, BiosReg, 0);
652 write3CE(par, BiosReg, 8);
653 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 1);
654 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 1);
657 /* For resolutions smaller than FP resolution center */
658 static void screen_center(struct tridentfb_par *par)
660 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 0x80);
661 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 0x80);
664 /* Address of first shown pixel in display memory */
665 static void set_screen_start(struct tridentfb_par *par, int base)
668 write3X4(par, VGA_CRTC_START_LO, base & 0xFF);
669 write3X4(par, VGA_CRTC_START_HI, (base & 0xFF00) >> 8);
670 tmp = read3X4(par, CRTCModuleTest) & 0xDF;
671 write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11));
672 tmp = read3X4(par, CRTHiOrd) & 0xF8;
673 write3X4(par, CRTHiOrd, tmp | ((base & 0xE0000) >> 17));
676 /* Set dotclock frequency */
677 static void set_vclk(struct tridentfb_par *par, unsigned long freq)
680 unsigned long fi, d, di;
681 unsigned char best_m = 0, best_n = 0, best_k = 0;
682 unsigned char hi, lo;
685 for (k = 1; k >= 0; k--)
686 for (m = 0; m < 32; m++)
687 for (n = 0; n < 122; n++) {
688 fi = ((14318l * (n + 8)) / (m + 2)) >> k;
689 if ((di = abs(fi - freq)) < d) {
699 if (is_oldclock(par->chip_id)) {
700 lo = best_n | (best_m << 7);
701 hi = (best_m >> 1) | (best_k << 4);
704 hi = best_m | (best_k << 6);
707 if (is3Dchip(par->chip_id)) {
708 vga_mm_wseq(par->io_virt, ClockHigh, hi);
709 vga_mm_wseq(par->io_virt, ClockLow, lo);
711 t_outb(par, lo, 0x43C8);
712 t_outb(par, hi, 0x43C9);
714 debug("VCLK = %X %X\n", hi, lo);
717 /* Set number of lines for flat panels*/
718 static void set_number_of_lines(struct tridentfb_par *par, int lines)
720 int tmp = read3CE(par, CyberEnhance) & 0x8F;
723 else if (lines > 768)
725 else if (lines > 600)
727 else if (lines > 480)
729 write3CE(par, CyberEnhance, tmp);
733 * If we see that FP is active we assume we have one.
734 * Otherwise we have a CRT display. User can override.
736 static int __devinit is_flatpanel(struct tridentfb_par *par)
740 if (crt || !iscyber(par->chip_id))
742 return (read3CE(par, FPConfig) & 0x10) ? 1 : 0;
745 /* Try detecting the video memory size */
746 static unsigned int __devinit get_memsize(struct tridentfb_par *par)
748 unsigned char tmp, tmp2;
751 /* If memory size provided by user */
755 switch (par->chip_id) {
760 tmp = read3X4(par, SPR) & 0x0F;
776 k = 10 * Mb; /* XP */
782 k = 12 * Mb; /* XP */
785 k = 14 * Mb; /* XP */
788 k = 16 * Mb; /* XP */
792 tmp2 = vga_mm_rseq(par->io_virt, 0xC1);
822 output("framebuffer size = %d Kb\n", k / Kb);
826 /* See if we can handle the video mode described in var */
827 static int tridentfb_check_var(struct fb_var_screeninfo *var,
828 struct fb_info *info)
830 struct tridentfb_par *par = info->par;
831 int bpp = var->bits_per_pixel;
832 int ramdac = 230000; /* 230MHz for most 3D chips */
835 /* check color depth */
837 bpp = var->bits_per_pixel = 32;
838 if (par->chip_id == TGUI9440 && bpp == 32)
840 /* check whether resolution fits on panel and in memory */
841 if (par->flatpanel && nativex && var->xres > nativex)
843 /* various resolution checks */
844 var->xres = (var->xres + 7) & ~0x7;
845 if (var->xres != var->xres_virtual)
846 var->xres_virtual = var->xres;
847 if (var->yres > var->yres_virtual)
848 var->yres_virtual = var->yres;
849 if (var->xres * var->yres_virtual * bpp / 8 > info->fix.smem_len)
855 var->green.offset = 0;
856 var->blue.offset = 0;
858 var->green.length = 6;
859 var->blue.length = 6;
862 var->red.offset = 11;
863 var->green.offset = 5;
864 var->blue.offset = 0;
866 var->green.length = 6;
867 var->blue.length = 5;
870 var->red.offset = 16;
871 var->green.offset = 8;
872 var->blue.offset = 0;
874 var->green.length = 8;
875 var->blue.length = 8;
881 if (is_xp(par->chip_id))
884 switch (par->chip_id) {
886 ramdac = (bpp >= 16) ? 45000 : 90000;
900 /* The clock is doubled for 32 bpp */
904 if (PICOS2KHZ(var->pixclock) > ramdac)
913 /* Pan the display */
914 static int tridentfb_pan_display(struct fb_var_screeninfo *var,
915 struct fb_info *info)
917 struct tridentfb_par *par = info->par;
921 offset = (var->xoffset + (var->yoffset * var->xres))
922 * var->bits_per_pixel / 32;
923 info->var.xoffset = var->xoffset;
924 info->var.yoffset = var->yoffset;
925 set_screen_start(par, offset);
930 static void shadowmode_on(struct tridentfb_par *par)
932 write3CE(par, CyberControl, read3CE(par, CyberControl) | 0x81);
935 static void shadowmode_off(struct tridentfb_par *par)
937 write3CE(par, CyberControl, read3CE(par, CyberControl) & 0x7E);
940 /* Set the hardware to the requested video mode */
941 static int tridentfb_set_par(struct fb_info *info)
943 struct tridentfb_par *par = (struct tridentfb_par *)(info->par);
944 u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart, hblankend;
945 u32 vtotal, vdispend, vsyncstart, vsyncend, vblankstart, vblankend;
946 struct fb_var_screeninfo *var = &info->var;
947 int bpp = var->bits_per_pixel;
952 hdispend = var->xres / 8 - 1;
953 hsyncstart = (var->xres + var->right_margin) / 8 - 1;
954 hsyncend = (var->xres + var->right_margin + var->hsync_len) / 8 - 1;
955 htotal = (var->xres + var->left_margin + var->right_margin +
956 var->hsync_len) / 8 - 5;
957 hblankstart = hdispend + 1;
958 hblankend = htotal + 3;
960 vdispend = var->yres - 1;
961 vsyncstart = var->yres + var->lower_margin;
962 vsyncend = vsyncstart + var->vsync_len;
963 vtotal = var->upper_margin + vsyncend - 2;
964 vblankstart = vdispend + 1;
968 write3CE(par, CyberControl, 8);
970 if (par->flatpanel && var->xres < nativex) {
972 * on flat panels with native size larger
973 * than requested resolution decide whether
974 * we stretch or center
976 t_outb(par, 0xEB, VGA_MIS_W);
986 t_outb(par, 0x2B, VGA_MIS_W);
987 write3CE(par, CyberControl, 8);
990 /* vertical timing values */
991 write3X4(par, VGA_CRTC_V_TOTAL, vtotal & 0xFF);
992 write3X4(par, VGA_CRTC_V_DISP_END, vdispend & 0xFF);
993 write3X4(par, VGA_CRTC_V_SYNC_START, vsyncstart & 0xFF);
994 write3X4(par, VGA_CRTC_V_SYNC_END, (vsyncend & 0x0F));
995 write3X4(par, VGA_CRTC_V_BLANK_START, vblankstart & 0xFF);
996 write3X4(par, VGA_CRTC_V_BLANK_END, vblankend & 0xFF);
998 /* horizontal timing values */
999 write3X4(par, VGA_CRTC_H_TOTAL, htotal & 0xFF);
1000 write3X4(par, VGA_CRTC_H_DISP, hdispend & 0xFF);
1001 write3X4(par, VGA_CRTC_H_SYNC_START, hsyncstart & 0xFF);
1002 write3X4(par, VGA_CRTC_H_SYNC_END,
1003 (hsyncend & 0x1F) | ((hblankend & 0x20) << 2));
1004 write3X4(par, VGA_CRTC_H_BLANK_START, hblankstart & 0xFF);
1005 write3X4(par, VGA_CRTC_H_BLANK_END, hblankend & 0x1F);
1007 /* higher bits of vertical timing values */
1009 if (vtotal & 0x100) tmp |= 0x01;
1010 if (vdispend & 0x100) tmp |= 0x02;
1011 if (vsyncstart & 0x100) tmp |= 0x04;
1012 if (vblankstart & 0x100) tmp |= 0x08;
1014 if (vtotal & 0x200) tmp |= 0x20;
1015 if (vdispend & 0x200) tmp |= 0x40;
1016 if (vsyncstart & 0x200) tmp |= 0x80;
1017 write3X4(par, VGA_CRTC_OVERFLOW, tmp);
1019 tmp = read3X4(par, CRTHiOrd) & 0x07;
1020 tmp |= 0x08; /* line compare bit 10 */
1021 if (vtotal & 0x400) tmp |= 0x80;
1022 if (vblankstart & 0x400) tmp |= 0x40;
1023 if (vsyncstart & 0x400) tmp |= 0x20;
1024 if (vdispend & 0x400) tmp |= 0x10;
1025 write3X4(par, CRTHiOrd, tmp);
1027 tmp = (htotal >> 8) & 0x01;
1028 tmp |= (hdispend >> 7) & 0x02;
1029 tmp |= (hsyncstart >> 5) & 0x08;
1030 tmp |= (hblankstart >> 4) & 0x10;
1031 write3X4(par, HorizOverflow, tmp);
1034 if (vblankstart & 0x200) tmp |= 0x20;
1035 //FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */
1036 write3X4(par, VGA_CRTC_MAX_SCAN, tmp);
1038 write3X4(par, VGA_CRTC_LINE_COMPARE, 0xFF);
1039 write3X4(par, VGA_CRTC_PRESET_ROW, 0);
1040 write3X4(par, VGA_CRTC_MODE, 0xC3);
1042 write3X4(par, LinearAddReg, 0x20); /* enable linear addressing */
1044 tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84 : 0x80;
1045 /* enable access extended memory */
1046 write3X4(par, CRTCModuleTest, tmp);
1048 /* enable GE for text acceleration */
1049 write3X4(par, GraphEngReg, 0x80);
1051 #ifdef CONFIG_FB_TRIDENT_ACCEL
1052 par->init_accel(par, info->var.xres, bpp);
1070 write3X4(par, PixelBusReg, tmp);
1072 tmp = read3X4(par, DRAMControl);
1073 if (!is_oldprotect(par->chip_id))
1075 if (iscyber(par->chip_id))
1077 write3X4(par, DRAMControl, tmp); /* both IO, linear enable */
1079 write3X4(par, InterfaceSel, read3X4(par, InterfaceSel) | 0x40);
1080 if (!is_xp(par->chip_id))
1081 write3X4(par, Performance, read3X4(par, Performance) | 0x10);
1082 /* MMIO & PCI read and write burst enable */
1083 if (par->chip_id != TGUI9440)
1084 write3X4(par, PCIReg, read3X4(par, PCIReg) | 0x06);
1086 vga_mm_wseq(par->io_virt, 0, 3);
1087 vga_mm_wseq(par->io_virt, 1, 1); /* set char clock 8 dots wide */
1088 /* enable 4 maps because needed in chain4 mode */
1089 vga_mm_wseq(par->io_virt, 2, 0x0F);
1090 vga_mm_wseq(par->io_virt, 3, 0);
1091 vga_mm_wseq(par->io_virt, 4, 0x0E); /* memory mode enable bitmaps ?? */
1093 /* convert from picoseconds to kHz */
1094 vclk = PICOS2KHZ(info->var.pixclock);
1096 /* divide clock by 2 if 32bpp chain4 mode display and CPU path */
1097 tmp = read3CE(par, MiscExtFunc) & 0xF0;
1098 if (bpp == 32 || (par->chip_id == TGUI9440 && bpp == 16)) {
1102 set_vclk(par, vclk);
1103 write3CE(par, MiscExtFunc, tmp | 0x12);
1104 write3CE(par, 0x5, 0x40); /* no CGA compat, allow 256 col */
1105 write3CE(par, 0x6, 0x05); /* graphics mode */
1106 write3CE(par, 0x7, 0x0F); /* planes? */
1108 if (par->chip_id == CYBERBLADEXPAi1) {
1109 /* This fixes snow-effect in 32 bpp */
1110 write3X4(par, VGA_CRTC_H_SYNC_START, 0x84);
1113 /* graphics mode and support 256 color modes */
1114 writeAttr(par, 0x10, 0x41);
1115 writeAttr(par, 0x12, 0x0F); /* planes */
1116 writeAttr(par, 0x13, 0); /* horizontal pel panning */
1119 for (tmp = 0; tmp < 0x10; tmp++)
1120 writeAttr(par, tmp, tmp);
1121 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
1122 t_outb(par, 0x20, VGA_ATT_W); /* enable attr */
1140 t_inb(par, VGA_PEL_IW);
1141 t_inb(par, VGA_PEL_MSK);
1142 t_inb(par, VGA_PEL_MSK);
1143 t_inb(par, VGA_PEL_MSK);
1144 t_inb(par, VGA_PEL_MSK);
1145 t_outb(par, tmp, VGA_PEL_MSK);
1146 t_inb(par, VGA_PEL_IW);
1149 set_number_of_lines(par, info->var.yres);
1150 set_lwidth(par, info->var.xres * bpp / (4 * 16));
1151 info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1152 info->fix.line_length = info->var.xres * (bpp >> 3);
1153 info->cmap.len = (bpp == 8) ? 256 : 16;
1158 /* Set one color register */
1159 static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1160 unsigned blue, unsigned transp,
1161 struct fb_info *info)
1163 int bpp = info->var.bits_per_pixel;
1164 struct tridentfb_par *par = info->par;
1166 if (regno >= info->cmap.len)
1170 t_outb(par, 0xFF, VGA_PEL_MSK);
1171 t_outb(par, regno, VGA_PEL_IW);
1173 t_outb(par, red >> 10, VGA_PEL_D);
1174 t_outb(par, green >> 10, VGA_PEL_D);
1175 t_outb(par, blue >> 10, VGA_PEL_D);
1177 } else if (regno < 16) {
1178 if (bpp == 16) { /* RGB 565 */
1181 col = (red & 0xF800) | ((green & 0xFC00) >> 5) |
1182 ((blue & 0xF800) >> 11);
1184 ((u32 *)(info->pseudo_palette))[regno] = col;
1185 } else if (bpp == 32) /* ARGB 8888 */
1186 ((u32*)info->pseudo_palette)[regno] =
1187 ((transp & 0xFF00) << 16) |
1188 ((red & 0xFF00) << 8) |
1189 ((green & 0xFF00)) |
1190 ((blue & 0xFF00) >> 8);
1193 /* debug("exit\n"); */
1197 /* Try blanking the screen.For flat panels it does nothing */
1198 static int tridentfb_blank(int blank_mode, struct fb_info *info)
1200 unsigned char PMCont, DPMSCont;
1201 struct tridentfb_par *par = info->par;
1206 t_outb(par, 0x04, 0x83C8); /* Read DPMS Control */
1207 PMCont = t_inb(par, 0x83C6) & 0xFC;
1208 DPMSCont = read3CE(par, PowerStatus) & 0xFC;
1209 switch (blank_mode) {
1210 case FB_BLANK_UNBLANK:
1211 /* Screen: On, HSync: On, VSync: On */
1212 case FB_BLANK_NORMAL:
1213 /* Screen: Off, HSync: On, VSync: On */
1217 case FB_BLANK_HSYNC_SUSPEND:
1218 /* Screen: Off, HSync: Off, VSync: On */
1222 case FB_BLANK_VSYNC_SUSPEND:
1223 /* Screen: Off, HSync: On, VSync: Off */
1227 case FB_BLANK_POWERDOWN:
1228 /* Screen: Off, HSync: Off, VSync: Off */
1234 write3CE(par, PowerStatus, DPMSCont);
1235 t_outb(par, 4, 0x83C8);
1236 t_outb(par, PMCont, 0x83C6);
1240 /* let fbcon do a softblank for us */
1241 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1244 static struct fb_ops tridentfb_ops = {
1245 .owner = THIS_MODULE,
1246 .fb_setcolreg = tridentfb_setcolreg,
1247 .fb_pan_display = tridentfb_pan_display,
1248 .fb_blank = tridentfb_blank,
1249 .fb_check_var = tridentfb_check_var,
1250 .fb_set_par = tridentfb_set_par,
1251 .fb_fillrect = tridentfb_fillrect,
1252 .fb_copyarea = tridentfb_copyarea,
1253 .fb_imageblit = cfb_imageblit,
1256 static int __devinit trident_pci_probe(struct pci_dev *dev,
1257 const struct pci_device_id *id)
1260 unsigned char revision;
1261 struct fb_info *info;
1262 struct tridentfb_par *default_par;
1267 err = pci_enable_device(dev);
1271 info = framebuffer_alloc(sizeof(struct tridentfb_par), &dev->dev);
1274 default_par = info->par;
1276 chip_id = id->device;
1278 if (chip_id == CYBERBLADEi1)
1279 output("*** Please do use cyblafb, Cyberblade/i1 support "
1280 "will soon be removed from tridentfb!\n");
1283 /* If PCI id is 0x9660 then further detect chip type */
1285 if (chip_id == TGUI9660) {
1286 revision = vga_io_rseq(RevisionID);
1290 chip_id = PROVIDIA9685;
1294 chip_id = CYBER9397;
1297 chip_id = CYBER9397DVD;
1306 chip_id = CYBER9385;
1309 chip_id = CYBER9382;
1312 chip_id = CYBER9388;
1319 chip3D = is3Dchip(chip_id);
1321 if (is_xp(chip_id)) {
1322 default_par->init_accel = xp_init_accel;
1323 default_par->wait_engine = xp_wait_engine;
1324 default_par->fill_rect = xp_fill_rect;
1325 default_par->copy_rect = xp_copy_rect;
1326 } else if (is_blade(chip_id)) {
1327 default_par->init_accel = blade_init_accel;
1328 default_par->wait_engine = blade_wait_engine;
1329 default_par->fill_rect = blade_fill_rect;
1330 default_par->copy_rect = blade_copy_rect;
1332 default_par->init_accel = image_init_accel;
1333 default_par->wait_engine = image_wait_engine;
1334 default_par->fill_rect = image_fill_rect;
1335 default_par->copy_rect = image_copy_rect;
1338 default_par->chip_id = chip_id;
1340 /* acceleration is on by default for 3D chips */
1341 defaultaccel = chip3D && !noaccel;
1343 /* setup MMIO region */
1344 tridentfb_fix.mmio_start = pci_resource_start(dev, 1);
1345 tridentfb_fix.mmio_len = chip3D ? 0x20000 : 0x10000;
1347 if (!request_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len, "tridentfb")) {
1348 debug("request_region failed!\n");
1349 framebuffer_release(info);
1353 default_par->io_virt = ioremap_nocache(tridentfb_fix.mmio_start,
1354 tridentfb_fix.mmio_len);
1356 if (!default_par->io_virt) {
1357 debug("ioremap failed\n");
1362 /* setup framebuffer memory */
1363 tridentfb_fix.smem_start = pci_resource_start(dev, 0);
1364 tridentfb_fix.smem_len = get_memsize(default_par);
1368 if (!request_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len, "tridentfb")) {
1369 debug("request_mem_region failed!\n");
1370 disable_mmio(info->par);
1375 info->screen_base = ioremap_nocache(tridentfb_fix.smem_start,
1376 tridentfb_fix.smem_len);
1378 if (!info->screen_base) {
1379 debug("ioremap failed\n");
1384 output("%s board found\n", pci_name(dev));
1385 default_par->flatpanel = is_flatpanel(default_par);
1387 if (default_par->flatpanel)
1388 nativex = get_nativex(default_par);
1390 info->fix = tridentfb_fix;
1391 info->fbops = &tridentfb_ops;
1392 info->pseudo_palette = default_par->pseudo_pal;
1394 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1395 #ifdef CONFIG_FB_TRIDENT_ACCEL
1396 info->flags |= FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT;
1398 if (!fb_find_mode(&info->var, info,
1399 mode_option, NULL, 0, NULL, bpp)) {
1403 err = fb_alloc_cmap(&info->cmap, 256, 0);
1407 if (defaultaccel && default_par->init_accel)
1408 info->var.accel_flags |= FB_ACCELF_TEXT;
1410 info->var.accel_flags &= ~FB_ACCELF_TEXT;
1411 info->var.activate |= FB_ACTIVATE_NOW;
1412 info->device = &dev->dev;
1413 if (register_framebuffer(info) < 0) {
1414 printk(KERN_ERR "tridentfb: could not register Trident framebuffer\n");
1415 fb_dealloc_cmap(&info->cmap);
1419 output("fb%d: %s frame buffer device %dx%d-%dbpp\n",
1420 info->node, info->fix.id, info->var.xres,
1421 info->var.yres, info->var.bits_per_pixel);
1423 pci_set_drvdata(dev, info);
1427 if (info->screen_base)
1428 iounmap(info->screen_base);
1429 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1430 disable_mmio(info->par);
1432 if (default_par->io_virt)
1433 iounmap(default_par->io_virt);
1434 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1435 framebuffer_release(info);
1439 static void __devexit trident_pci_remove(struct pci_dev *dev)
1441 struct fb_info *info = pci_get_drvdata(dev);
1442 struct tridentfb_par *par = info->par;
1444 unregister_framebuffer(info);
1445 iounmap(par->io_virt);
1446 iounmap(info->screen_base);
1447 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1448 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1449 pci_set_drvdata(dev, NULL);
1450 framebuffer_release(info);
1453 /* List of boards that we are trying to support */
1454 static struct pci_device_id trident_devices[] = {
1455 {PCI_VENDOR_ID_TRIDENT, BLADE3D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1456 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1457 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1458 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1459 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1460 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1461 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1462 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEE4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1463 {PCI_VENDOR_ID_TRIDENT, TGUI9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1464 {PCI_VENDOR_ID_TRIDENT, TGUI9660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1465 {PCI_VENDOR_ID_TRIDENT, IMAGE975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1466 {PCI_VENDOR_ID_TRIDENT, IMAGE985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1467 {PCI_VENDOR_ID_TRIDENT, CYBER9320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1468 {PCI_VENDOR_ID_TRIDENT, CYBER9388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1469 {PCI_VENDOR_ID_TRIDENT, CYBER9520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1470 {PCI_VENDOR_ID_TRIDENT, CYBER9525DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1471 {PCI_VENDOR_ID_TRIDENT, CYBER9397, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1472 {PCI_VENDOR_ID_TRIDENT, CYBER9397DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1473 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1474 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1475 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm16, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1479 MODULE_DEVICE_TABLE(pci, trident_devices);
1481 static struct pci_driver tridentfb_pci_driver = {
1482 .name = "tridentfb",
1483 .id_table = trident_devices,
1484 .probe = trident_pci_probe,
1485 .remove = __devexit_p(trident_pci_remove)
1489 * Parse user specified options (`video=trident:')
1491 * video=trident:800x600,bpp=16,noaccel
1494 static int __init tridentfb_setup(char *options)
1497 if (!options || !*options)
1499 while ((opt = strsep(&options, ",")) != NULL) {
1502 if (!strncmp(opt, "noaccel", 7))
1504 else if (!strncmp(opt, "fp", 2))
1506 else if (!strncmp(opt, "crt", 3))
1508 else if (!strncmp(opt, "bpp=", 4))
1509 bpp = simple_strtoul(opt + 4, NULL, 0);
1510 else if (!strncmp(opt, "center", 6))
1512 else if (!strncmp(opt, "stretch", 7))
1514 else if (!strncmp(opt, "memsize=", 8))
1515 memsize = simple_strtoul(opt + 8, NULL, 0);
1516 else if (!strncmp(opt, "memdiff=", 8))
1517 memdiff = simple_strtoul(opt + 8, NULL, 0);
1518 else if (!strncmp(opt, "nativex=", 8))
1519 nativex = simple_strtoul(opt + 8, NULL, 0);
1527 static int __init tridentfb_init(void)
1530 char *option = NULL;
1532 if (fb_get_options("tridentfb", &option))
1534 tridentfb_setup(option);
1536 output("Trident framebuffer %s initializing\n", VERSION);
1537 return pci_register_driver(&tridentfb_pci_driver);
1540 static void __exit tridentfb_exit(void)
1542 pci_unregister_driver(&tridentfb_pci_driver);
1545 module_init(tridentfb_init);
1546 module_exit(tridentfb_exit);
1548 MODULE_AUTHOR("Jani Monoses <jani@iv.ro>");
1549 MODULE_DESCRIPTION("Framebuffer driver for Trident cards");
1550 MODULE_LICENSE("GPL");