2 * Frame buffer driver for Trident Blade and Image series
4 * Copyright 2001, 2002 - Jani Monoses <jani@iv.ro>
7 * CREDITS:(in order of appearance)
8 * skeletonfb.c by Geert Uytterhoeven and other fb code in drivers/video
9 * Special thanks ;) to Mattia Crivellini <tia@mclink.it>
10 * much inspired by the XFree86 4.x Trident driver sources
11 * by Alan Hourihane the FreeVGA project
12 * Francesco Salvestrini <salvestrini@users.sf.net> XP support,
15 * timing value tweaking so it looks good on every monitor in every mode
19 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/pci.h>
24 #include <linux/delay.h>
25 #include <video/trident.h>
27 #define VERSION "0.7.8-NEWAPI"
29 struct tridentfb_par {
30 void __iomem *io_virt; /* iospace virtual memory address */
33 static unsigned char eng_oper; /* engine operation... */
34 static struct fb_ops tridentfb_ops;
36 static struct tridentfb_par default_par;
38 /* FIXME:kmalloc these 3 instead */
39 static struct fb_info fb_info;
40 static u32 pseudo_pal[16];
42 static struct fb_var_screeninfo default_var;
44 static struct fb_fix_screeninfo tridentfb_fix = {
46 .type = FB_TYPE_PACKED_PIXELS,
48 .visual = FB_VISUAL_PSEUDOCOLOR,
49 .accel = FB_ACCEL_NONE,
54 static int defaultaccel;
55 static int displaytype;
57 /* defaults which are normally overriden by user values */
60 static char *mode_option __devinitdata = "640x480";
75 module_param(mode_option, charp, 0);
76 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
77 module_param_named(mode, mode_option, charp, 0);
78 MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)");
79 module_param(bpp, int, 0);
80 module_param(center, int, 0);
81 module_param(stretch, int, 0);
82 module_param(noaccel, int, 0);
83 module_param(memsize, int, 0);
84 module_param(memdiff, int, 0);
85 module_param(nativex, int, 0);
86 module_param(fp, int, 0);
87 module_param(crt, int, 0);
92 static int is3Dchip(int id)
94 return ((id == BLADE3D) || (id == CYBERBLADEE4) ||
95 (id == CYBERBLADEi7) || (id == CYBERBLADEi7D) ||
96 (id == CYBER9397) || (id == CYBER9397DVD) ||
97 (id == CYBER9520) || (id == CYBER9525DVD) ||
98 (id == IMAGE975) || (id == IMAGE985) ||
99 (id == CYBERBLADEi1) || (id == CYBERBLADEi1D) ||
100 (id == CYBERBLADEAi1) || (id == CYBERBLADEAi1D) ||
101 (id == CYBERBLADEXPm8) || (id == CYBERBLADEXPm16) ||
102 (id == CYBERBLADEXPAi1));
105 static int iscyber(int id)
121 case CYBERBLADEXPAi1:
129 case CYBERBLADEi7: /* VIA MPV4 integrated version */
132 /* case CYBERBLDAEXPm8: Strange */
133 /* case CYBERBLDAEXPm16: Strange */
138 #define CRT 0x3D0 /* CRTC registers offset for color display */
140 static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg)
142 fb_writeb(val, p->io_virt + reg);
145 static inline u8 t_inb(struct tridentfb_par *p, u16 reg)
147 return fb_readb(p->io_virt + reg);
150 static struct accel_switch {
151 void (*init_accel) (struct tridentfb_par *, int, int);
152 void (*wait_engine) (struct tridentfb_par *);
154 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
156 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
159 static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v)
161 fb_writel(v, par->io_virt + r);
164 static inline u32 readmmr(struct tridentfb_par *par, u16 r)
166 return fb_readl(par->io_virt + r);
170 * Blade specific acceleration.
173 #define point(x, y) ((y) << 16 | (x))
185 static void blade_init_accel(struct tridentfb_par *par, int pitch, int bpp)
187 int v1 = (pitch >> 3) << 20;
204 v2 = v1 | (tmp << 29);
205 writemmr(par, 0x21C0, v2);
206 writemmr(par, 0x21C4, v2);
207 writemmr(par, 0x21B8, v2);
208 writemmr(par, 0x21BC, v2);
209 writemmr(par, 0x21D0, v1);
210 writemmr(par, 0x21D4, v1);
211 writemmr(par, 0x21C8, v1);
212 writemmr(par, 0x21CC, v1);
213 writemmr(par, 0x216C, 0);
216 static void blade_wait_engine(struct tridentfb_par *par)
218 while (readmmr(par, STA) & 0xFA800000) ;
221 static void blade_fill_rect(struct tridentfb_par *par,
222 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
224 writemmr(par, CLR, c);
225 writemmr(par, ROP, rop ? 0x66 : ROP_S);
226 writemmr(par, CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2);
228 writemmr(par, DR1, point(x, y));
229 writemmr(par, DR2, point(x + w - 1, y + h - 1));
232 static void blade_copy_rect(struct tridentfb_par *par,
233 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
238 s2 = point(x1 + w - 1, y1 + h - 1);
240 d2 = point(x2 + w - 1, y2 + h - 1);
242 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
245 writemmr(par, ROP, ROP_S);
246 writemmr(par, CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction);
248 writemmr(par, SR1, direction ? s2 : s1);
249 writemmr(par, SR2, direction ? s1 : s2);
250 writemmr(par, DR1, direction ? d2 : d1);
251 writemmr(par, DR2, direction ? d1 : d2);
254 static struct accel_switch accel_blade = {
262 * BladeXP specific acceleration functions
266 #define masked_point(x, y) ((y & 0xffff)<<16|(x & 0xffff))
268 static void xp_init_accel(struct tridentfb_par *par, int pitch, int bpp)
288 switch (pitch << (bpp >> 3)) {
304 t_outb(par, x, 0x2125);
324 writemmr(par, 0x2154, v1);
325 writemmr(par, 0x2150, v1);
326 t_outb(par, 3, 0x2126);
329 static void xp_wait_engine(struct tridentfb_par *par)
337 busy = t_inb(par, STA) & 0x80;
341 if (count == 10000000) {
347 t_outb(par, 0x00, 0x2120);
354 static void xp_fill_rect(struct tridentfb_par *par,
355 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
357 writemmr(par, 0x2127, ROP_P);
358 writemmr(par, 0x2158, c);
359 writemmr(par, 0x2128, 0x4000);
360 writemmr(par, 0x2140, masked_point(h, w));
361 writemmr(par, 0x2138, masked_point(y, x));
362 t_outb(par, 0x01, 0x2124);
363 t_outb(par, eng_oper, 0x2125);
366 static void xp_copy_rect(struct tridentfb_par *par,
367 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
370 u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
374 if ((x1 < x2) && (y1 == y2)) {
392 writemmr(par, 0x2128, direction);
393 t_outb(par, ROP_S, 0x2127);
394 writemmr(par, 0x213C, masked_point(y1_tmp, x1_tmp));
395 writemmr(par, 0x2138, masked_point(y2_tmp, x2_tmp));
396 writemmr(par, 0x2140, masked_point(h, w));
397 t_outb(par, 0x01, 0x2124);
400 static struct accel_switch accel_xp = {
408 * Image specific acceleration functions
410 static void image_init_accel(struct tridentfb_par *par, int pitch, int bpp)
428 writemmr(par, 0x2120, 0xF0000000);
429 writemmr(par, 0x2120, 0x40000000 | tmp);
430 writemmr(par, 0x2120, 0x80000000);
431 writemmr(par, 0x2144, 0x00000000);
432 writemmr(par, 0x2148, 0x00000000);
433 writemmr(par, 0x2150, 0x00000000);
434 writemmr(par, 0x2154, 0x00000000);
435 writemmr(par, 0x2120, 0x60000000 | (pitch << 16) | pitch);
436 writemmr(par, 0x216C, 0x00000000);
437 writemmr(par, 0x2170, 0x00000000);
438 writemmr(par, 0x217C, 0x00000000);
439 writemmr(par, 0x2120, 0x10000000);
440 writemmr(par, 0x2130, (2047 << 16) | 2047);
443 static void image_wait_engine(struct tridentfb_par *par)
445 while (readmmr(par, 0x2164) & 0xF0000000) ;
448 static void image_fill_rect(struct tridentfb_par *par,
449 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
451 writemmr(par, 0x2120, 0x80000000);
452 writemmr(par, 0x2120, 0x90000000 | ROP_S);
454 writemmr(par, 0x2144, c);
456 writemmr(par, DR1, point(x, y));
457 writemmr(par, DR2, point(x + w - 1, y + h - 1));
459 writemmr(par, 0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9);
462 static void image_copy_rect(struct tridentfb_par *par,
463 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
468 s2 = point(x1 + w - 1, y1 + h - 1);
470 d2 = point(x2 + w - 1, y2 + h - 1);
472 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
475 writemmr(par, 0x2120, 0x80000000);
476 writemmr(par, 0x2120, 0x90000000 | ROP_S);
478 writemmr(par, SR1, direction ? s2 : s1);
479 writemmr(par, SR2, direction ? s1 : s2);
480 writemmr(par, DR1, direction ? d2 : d1);
481 writemmr(par, DR2, direction ? d1 : d2);
482 writemmr(par, 0x2124,
483 0x80000000 | 1 << 22 | 1 << 10 | 1 << 7 | direction);
486 static struct accel_switch accel_image = {
494 * Accel functions called by the upper layers
496 #ifdef CONFIG_FB_TRIDENT_ACCEL
497 static void tridentfb_fillrect(struct fb_info *info,
498 const struct fb_fillrect *fr)
500 struct tridentfb_par *par = info->par;
501 int bpp = info->var.bits_per_pixel;
512 col = ((u32 *)(info->pseudo_palette))[fr->color];
515 col = ((u32 *)(info->pseudo_palette))[fr->color];
519 acc->fill_rect(par, fr->dx, fr->dy, fr->width,
520 fr->height, col, fr->rop);
521 acc->wait_engine(par);
523 static void tridentfb_copyarea(struct fb_info *info,
524 const struct fb_copyarea *ca)
526 struct tridentfb_par *par = info->par;
528 acc->copy_rect(par, ca->sx, ca->sy, ca->dx, ca->dy,
529 ca->width, ca->height);
530 acc->wait_engine(par);
532 #else /* !CONFIG_FB_TRIDENT_ACCEL */
533 #define tridentfb_fillrect cfb_fillrect
534 #define tridentfb_copyarea cfb_copyarea
535 #endif /* CONFIG_FB_TRIDENT_ACCEL */
539 * Hardware access functions
542 static inline unsigned char read3X4(struct tridentfb_par *par, int reg)
544 writeb(reg, par->io_virt + CRT + 4);
545 return readb(par->io_virt + CRT + 5);
548 static inline void write3X4(struct tridentfb_par *par, int reg,
551 writeb(reg, par->io_virt + CRT + 4);
552 writeb(val, par->io_virt + CRT + 5);
555 static inline unsigned char read3C4(struct tridentfb_par *par, int reg)
557 t_outb(par, reg, 0x3C4);
558 return t_inb(par, 0x3C5);
561 static inline void write3C4(struct tridentfb_par *par, int reg,
564 t_outb(par, reg, 0x3C4);
565 t_outb(par, val, 0x3C5);
568 static inline unsigned char read3CE(struct tridentfb_par *par, int reg)
570 t_outb(par, reg, 0x3CE);
571 return t_inb(par, 0x3CF);
574 static inline void writeAttr(struct tridentfb_par *par, int reg,
577 fb_readb(par->io_virt + CRT + 0x0A); /* flip-flop to index */
578 t_outb(par, reg, 0x3C0);
579 t_outb(par, val, 0x3C0);
582 static inline void write3CE(struct tridentfb_par *par, int reg,
585 t_outb(par, reg, 0x3CE);
586 t_outb(par, val, 0x3CF);
589 static void enable_mmio(void)
595 /* Unprotect registers */
596 outb(NewMode1, 0x3C4);
601 outb(inb(0x3D5) | 0x01, 0x3D5);
604 static void disable_mmio(struct tridentfb_par *par)
607 t_outb(par, 0x0B, 0x3C4);
610 /* Unprotect registers */
611 t_outb(par, NewMode1, 0x3C4);
612 t_outb(par, 0x80, 0x3C5);
615 t_outb(par, PCIReg, 0x3D4);
616 t_outb(par, t_inb(par, 0x3D5) & ~0x01, 0x3D5);
619 static void crtc_unlock(struct tridentfb_par *par)
621 write3X4(par, CRTVSyncEnd, read3X4(par, CRTVSyncEnd) & 0x7F);
624 /* Return flat panel's maximum x resolution */
625 static int __devinit get_nativex(struct tridentfb_par *par)
632 tmp = (read3CE(par, VertStretch) >> 4) & 3;
653 output("%dx%d flat panel found\n", x, y);
658 static void set_lwidth(struct tridentfb_par *par, int width)
660 write3X4(par, Offset, width & 0xFF);
661 write3X4(par, AddColReg,
662 (read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4));
665 /* For resolutions smaller than FP resolution stretch */
666 static void screen_stretch(struct tridentfb_par *par)
668 if (chip_id != CYBERBLADEXPAi1)
669 write3CE(par, BiosReg, 0);
671 write3CE(par, BiosReg, 8);
672 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 1);
673 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 1);
676 /* For resolutions smaller than FP resolution center */
677 static void screen_center(struct tridentfb_par *par)
679 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 0x80);
680 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 0x80);
683 /* Address of first shown pixel in display memory */
684 static void set_screen_start(struct tridentfb_par *par, int base)
687 write3X4(par, StartAddrLow, base & 0xFF);
688 write3X4(par, StartAddrHigh, (base & 0xFF00) >> 8);
689 tmp = read3X4(par, CRTCModuleTest) & 0xDF;
690 write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11));
691 tmp = read3X4(par, CRTHiOrd) & 0xF8;
692 write3X4(par, CRTHiOrd, tmp | ((base & 0xE0000) >> 17));
695 /* Set dotclock frequency */
696 static void set_vclk(struct tridentfb_par *par, unsigned long freq)
699 unsigned long f, fi, d, di;
700 unsigned char lo = 0, hi = 0;
703 for (k = 2; k >= 0; k--)
704 for (m = 0; m < 63; m++)
705 for (n = 0; n < 128; n++) {
706 fi = ((14318l * (n + 8)) / (m + 2)) >> k;
707 if ((di = abs(fi - freq)) < d) {
717 write3C4(par, ClockHigh, hi);
718 write3C4(par, ClockLow, lo);
723 debug("VCLK = %X %X\n", hi, lo);
726 /* Set number of lines for flat panels*/
727 static void set_number_of_lines(struct tridentfb_par *par, int lines)
729 int tmp = read3CE(par, CyberEnhance) & 0x8F;
732 else if (lines > 768)
734 else if (lines > 600)
736 else if (lines > 480)
738 write3CE(par, CyberEnhance, tmp);
742 * If we see that FP is active we assume we have one.
743 * Otherwise we have a CRT display.User can override.
745 static unsigned int __devinit get_displaytype(struct tridentfb_par *par)
749 if (crt || !chipcyber)
751 return (read3CE(par, FPConfig) & 0x10) ? DISPLAY_FP : DISPLAY_CRT;
754 /* Try detecting the video memory size */
755 static unsigned int __devinit get_memsize(struct tridentfb_par *par)
757 unsigned char tmp, tmp2;
760 /* If memory size provided by user */
769 tmp = read3X4(par, SPR) & 0x0F;
785 k = 10 * Mb; /* XP */
791 k = 12 * Mb; /* XP */
794 k = 14 * Mb; /* XP */
797 k = 16 * Mb; /* XP */
801 tmp2 = read3C4(par, 0xC1);
831 output("framebuffer size = %d Kb\n", k / Kb);
835 /* See if we can handle the video mode described in var */
836 static int tridentfb_check_var(struct fb_var_screeninfo *var,
837 struct fb_info *info)
839 int bpp = var->bits_per_pixel;
842 /* check color depth */
844 bpp = var->bits_per_pixel = 32;
845 /* check whether resolution fits on panel and in memory */
846 if (flatpanel && nativex && var->xres > nativex)
848 if (var->xres * var->yres_virtual * bpp / 8 > info->fix.smem_len)
854 var->green.offset = 0;
855 var->blue.offset = 0;
857 var->green.length = 6;
858 var->blue.length = 6;
861 var->red.offset = 11;
862 var->green.offset = 5;
863 var->blue.offset = 0;
865 var->green.length = 6;
866 var->blue.length = 5;
869 var->red.offset = 16;
870 var->green.offset = 8;
871 var->blue.offset = 0;
873 var->green.length = 8;
874 var->blue.length = 8;
885 /* Pan the display */
886 static int tridentfb_pan_display(struct fb_var_screeninfo *var,
887 struct fb_info *info)
889 struct tridentfb_par *par = info->par;
893 offset = (var->xoffset + (var->yoffset * var->xres))
894 * var->bits_per_pixel / 32;
895 info->var.xoffset = var->xoffset;
896 info->var.yoffset = var->yoffset;
897 set_screen_start(par, offset);
902 static void shadowmode_on(struct tridentfb_par *par)
904 write3CE(par, CyberControl, read3CE(par, CyberControl) | 0x81);
907 static void shadowmode_off(struct tridentfb_par *par)
909 write3CE(par, CyberControl, read3CE(par, CyberControl) & 0x7E);
912 /* Set the hardware to the requested video mode */
913 static int tridentfb_set_par(struct fb_info *info)
915 struct tridentfb_par *par = (struct tridentfb_par *)(info->par);
916 u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart, hblankend;
917 u32 vtotal, vdispend, vsyncstart, vsyncend, vblankstart, vblankend;
918 struct fb_var_screeninfo *var = &info->var;
919 int bpp = var->bits_per_pixel;
924 hdispend = var->xres / 8 - 1;
925 hsyncstart = (var->xres + var->right_margin) / 8;
926 hsyncend = var->hsync_len / 8;
928 (var->xres + var->left_margin + var->right_margin +
929 var->hsync_len) / 8 - 10;
930 hblankstart = hdispend + 1;
931 hblankend = htotal + 5;
933 vdispend = var->yres - 1;
934 vsyncstart = var->yres + var->lower_margin;
935 vsyncend = var->vsync_len;
936 vtotal = var->upper_margin + vsyncstart + vsyncend - 2;
937 vblankstart = var->yres;
938 vblankend = vtotal + 2;
941 write3CE(par, CyberControl, 8);
943 if (flatpanel && var->xres < nativex) {
945 * on flat panels with native size larger
946 * than requested resolution decide whether
947 * we stretch or center
949 t_outb(par, 0xEB, 0x3C2);
959 t_outb(par, 0x2B, 0x3C2);
960 write3CE(par, CyberControl, 8);
963 /* vertical timing values */
964 write3X4(par, CRTVTotal, vtotal & 0xFF);
965 write3X4(par, CRTVDispEnd, vdispend & 0xFF);
966 write3X4(par, CRTVSyncStart, vsyncstart & 0xFF);
967 write3X4(par, CRTVSyncEnd, (vsyncend & 0x0F));
968 write3X4(par, CRTVBlankStart, vblankstart & 0xFF);
969 write3X4(par, CRTVBlankEnd, 0 /* p->vblankend & 0xFF */);
971 /* horizontal timing values */
972 write3X4(par, CRTHTotal, htotal & 0xFF);
973 write3X4(par, CRTHDispEnd, hdispend & 0xFF);
974 write3X4(par, CRTHSyncStart, hsyncstart & 0xFF);
975 write3X4(par, CRTHSyncEnd,
976 (hsyncend & 0x1F) | ((hblankend & 0x20) << 2));
977 write3X4(par, CRTHBlankStart, hblankstart & 0xFF);
978 write3X4(par, CRTHBlankEnd, 0 /* (p->hblankend & 0x1F) */);
980 /* higher bits of vertical timing values */
982 if (vtotal & 0x100) tmp |= 0x01;
983 if (vdispend & 0x100) tmp |= 0x02;
984 if (vsyncstart & 0x100) tmp |= 0x04;
985 if (vblankstart & 0x100) tmp |= 0x08;
987 if (vtotal & 0x200) tmp |= 0x20;
988 if (vdispend & 0x200) tmp |= 0x40;
989 if (vsyncstart & 0x200) tmp |= 0x80;
990 write3X4(par, CRTOverflow, tmp);
992 tmp = read3X4(par, CRTHiOrd) | 0x08; /* line compare bit 10 */
993 if (vtotal & 0x400) tmp |= 0x80;
994 if (vblankstart & 0x400) tmp |= 0x40;
995 if (vsyncstart & 0x400) tmp |= 0x20;
996 if (vdispend & 0x400) tmp |= 0x10;
997 write3X4(par, CRTHiOrd, tmp);
1000 if (htotal & 0x800) tmp |= 0x800 >> 11;
1001 if (hblankstart & 0x800) tmp |= 0x800 >> 7;
1002 write3X4(par, HorizOverflow, tmp);
1005 if (vblankstart & 0x200) tmp |= 0x20;
1006 //FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */
1007 write3X4(par, CRTMaxScanLine, tmp);
1009 write3X4(par, CRTLineCompare, 0xFF);
1010 write3X4(par, CRTPRowScan, 0);
1011 write3X4(par, CRTModeControl, 0xC3);
1013 write3X4(par, LinearAddReg, 0x20); /* enable linear addressing */
1015 tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84 : 0x80;
1016 /* enable access extended memory */
1017 write3X4(par, CRTCModuleTest, tmp);
1019 /* enable GE for text acceleration */
1020 write3X4(par, GraphEngReg, 0x80);
1022 #ifdef CONFIG_FB_TRIDENT_ACCEL
1023 acc->init_accel(par, info->var.xres, bpp);
1041 write3X4(par, PixelBusReg, tmp);
1046 write3X4(par, DRAMControl, tmp); /* both IO, linear enable */
1048 write3X4(par, InterfaceSel, read3X4(par, InterfaceSel) | 0x40);
1049 write3X4(par, Performance, 0x92);
1050 /* MMIO & PCI read and write burst enable */
1051 write3X4(par, PCIReg, 0x07);
1053 /* convert from picoseconds to kHz */
1054 vclk = PICOS2KHZ(info->var.pixclock);
1057 set_vclk(par, vclk);
1059 write3C4(par, 0, 3);
1060 write3C4(par, 1, 1); /* set char clock 8 dots wide */
1061 /* enable 4 maps because needed in chain4 mode */
1062 write3C4(par, 2, 0x0F);
1063 write3C4(par, 3, 0);
1064 write3C4(par, 4, 0x0E); /* memory mode enable bitmaps ?? */
1066 /* divide clock by 2 if 32bpp chain4 mode display and CPU path */
1067 write3CE(par, MiscExtFunc, (bpp == 32) ? 0x1A : 0x12);
1068 write3CE(par, 0x5, 0x40); /* no CGA compat, allow 256 col */
1069 write3CE(par, 0x6, 0x05); /* graphics mode */
1070 write3CE(par, 0x7, 0x0F); /* planes? */
1072 if (chip_id == CYBERBLADEXPAi1) {
1073 /* This fixes snow-effect in 32 bpp */
1074 write3X4(par, CRTHSyncStart, 0x84);
1077 /* graphics mode and support 256 color modes */
1078 writeAttr(par, 0x10, 0x41);
1079 writeAttr(par, 0x12, 0x0F); /* planes */
1080 writeAttr(par, 0x13, 0); /* horizontal pel panning */
1083 for (tmp = 0; tmp < 0x10; tmp++)
1084 writeAttr(par, tmp, tmp);
1085 fb_readb(par->io_virt + CRT + 0x0A); /* flip-flop to index */
1086 t_outb(par, 0x20, 0x3C0); /* enable attr */
1109 t_outb(par, tmp, 0x3C6);
1113 set_number_of_lines(par, info->var.yres);
1114 set_lwidth(par, info->var.xres * bpp / (4 * 16));
1115 info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1116 info->fix.line_length = info->var.xres * (bpp >> 3);
1117 info->cmap.len = (bpp == 8) ? 256 : 16;
1122 /* Set one color register */
1123 static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1124 unsigned blue, unsigned transp,
1125 struct fb_info *info)
1127 int bpp = info->var.bits_per_pixel;
1128 struct tridentfb_par *par = info->par;
1130 if (regno >= info->cmap.len)
1134 t_outb(par, 0xFF, 0x3C6);
1135 t_outb(par, regno, 0x3C8);
1137 t_outb(par, red >> 10, 0x3C9);
1138 t_outb(par, green >> 10, 0x3C9);
1139 t_outb(par, blue >> 10, 0x3C9);
1141 } else if (regno < 16) {
1142 if (bpp == 16) { /* RGB 565 */
1145 col = (red & 0xF800) | ((green & 0xFC00) >> 5) |
1146 ((blue & 0xF800) >> 11);
1148 ((u32 *)(info->pseudo_palette))[regno] = col;
1149 } else if (bpp == 32) /* ARGB 8888 */
1150 ((u32*)info->pseudo_palette)[regno] =
1151 ((transp & 0xFF00) << 16) |
1152 ((red & 0xFF00) << 8) |
1153 ((green & 0xFF00)) |
1154 ((blue & 0xFF00) >> 8);
1157 /* debug("exit\n"); */
1161 /* Try blanking the screen.For flat panels it does nothing */
1162 static int tridentfb_blank(int blank_mode, struct fb_info *info)
1164 unsigned char PMCont, DPMSCont;
1165 struct tridentfb_par *par = info->par;
1170 t_outb(par, 0x04, 0x83C8); /* Read DPMS Control */
1171 PMCont = t_inb(par, 0x83C6) & 0xFC;
1172 DPMSCont = read3CE(par, PowerStatus) & 0xFC;
1173 switch (blank_mode) {
1174 case FB_BLANK_UNBLANK:
1175 /* Screen: On, HSync: On, VSync: On */
1176 case FB_BLANK_NORMAL:
1177 /* Screen: Off, HSync: On, VSync: On */
1181 case FB_BLANK_HSYNC_SUSPEND:
1182 /* Screen: Off, HSync: Off, VSync: On */
1186 case FB_BLANK_VSYNC_SUSPEND:
1187 /* Screen: Off, HSync: On, VSync: Off */
1191 case FB_BLANK_POWERDOWN:
1192 /* Screen: Off, HSync: Off, VSync: Off */
1198 write3CE(par, PowerStatus, DPMSCont);
1199 t_outb(par, 4, 0x83C8);
1200 t_outb(par, PMCont, 0x83C6);
1204 /* let fbcon do a softblank for us */
1205 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1208 static struct fb_ops tridentfb_ops = {
1209 .owner = THIS_MODULE,
1210 .fb_setcolreg = tridentfb_setcolreg,
1211 .fb_pan_display = tridentfb_pan_display,
1212 .fb_blank = tridentfb_blank,
1213 .fb_check_var = tridentfb_check_var,
1214 .fb_set_par = tridentfb_set_par,
1215 .fb_fillrect = tridentfb_fillrect,
1216 .fb_copyarea = tridentfb_copyarea,
1217 .fb_imageblit = cfb_imageblit,
1220 static int __devinit trident_pci_probe(struct pci_dev * dev,
1221 const struct pci_device_id * id)
1224 unsigned char revision;
1226 err = pci_enable_device(dev);
1230 chip_id = id->device;
1232 if (chip_id == CYBERBLADEi1)
1233 output("*** Please do use cyblafb, Cyberblade/i1 support "
1234 "will soon be removed from tridentfb!\n");
1237 /* If PCI id is 0x9660 then further detect chip type */
1239 if (chip_id == TGUI9660) {
1240 outb(RevisionID, 0x3C4);
1241 revision = inb(0x3C5);
1246 chip_id = CYBER9397;
1249 chip_id = CYBER9397DVD;
1258 chip_id = CYBER9385;
1261 chip_id = CYBER9382;
1264 chip_id = CYBER9388;
1271 chip3D = is3Dchip(chip_id);
1272 chipcyber = iscyber(chip_id);
1274 if (is_xp(chip_id)) {
1276 } else if (is_blade(chip_id)) {
1282 /* acceleration is on by default for 3D chips */
1283 defaultaccel = chip3D && !noaccel;
1285 fb_info.par = &default_par;
1287 /* setup MMIO region */
1288 tridentfb_fix.mmio_start = pci_resource_start(dev, 1);
1289 tridentfb_fix.mmio_len = chip3D ? 0x20000 : 0x10000;
1291 if (!request_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len, "tridentfb")) {
1292 debug("request_region failed!\n");
1296 default_par.io_virt = ioremap_nocache(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1298 if (!default_par.io_virt) {
1299 debug("ioremap failed\n");
1306 /* setup framebuffer memory */
1307 tridentfb_fix.smem_start = pci_resource_start(dev, 0);
1308 tridentfb_fix.smem_len = get_memsize(&default_par);
1310 if (!request_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len, "tridentfb")) {
1311 debug("request_mem_region failed!\n");
1312 disable_mmio(fb_info.par);
1317 fb_info.screen_base = ioremap_nocache(tridentfb_fix.smem_start,
1318 tridentfb_fix.smem_len);
1320 if (!fb_info.screen_base) {
1321 debug("ioremap failed\n");
1326 output("%s board found\n", pci_name(dev));
1327 displaytype = get_displaytype(&default_par);
1330 nativex = get_nativex(&default_par);
1332 fb_info.fix = tridentfb_fix;
1333 fb_info.fbops = &tridentfb_ops;
1336 fb_info.flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1337 #ifdef CONFIG_FB_TRIDENT_ACCEL
1338 fb_info.flags |= FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT;
1340 fb_info.pseudo_palette = pseudo_pal;
1342 if (!fb_find_mode(&default_var, &fb_info,
1343 mode_option, NULL, 0, NULL, bpp)) {
1347 err = fb_alloc_cmap(&fb_info.cmap, 256, 0);
1351 if (defaultaccel && acc)
1352 default_var.accel_flags |= FB_ACCELF_TEXT;
1354 default_var.accel_flags &= ~FB_ACCELF_TEXT;
1355 default_var.activate |= FB_ACTIVATE_NOW;
1356 fb_info.var = default_var;
1357 fb_info.device = &dev->dev;
1358 if (register_framebuffer(&fb_info) < 0) {
1359 printk(KERN_ERR "tridentfb: could not register Trident framebuffer\n");
1360 fb_dealloc_cmap(&fb_info.cmap);
1364 output("fb%d: %s frame buffer device %dx%d-%dbpp\n",
1365 fb_info.node, fb_info.fix.id, default_var.xres,
1366 default_var.yres, default_var.bits_per_pixel);
1370 if (fb_info.screen_base)
1371 iounmap(fb_info.screen_base);
1372 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1373 disable_mmio(fb_info.par);
1375 if (default_par.io_virt)
1376 iounmap(default_par.io_virt);
1377 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1381 static void __devexit trident_pci_remove(struct pci_dev *dev)
1383 struct tridentfb_par *par = (struct tridentfb_par*)fb_info.par;
1384 unregister_framebuffer(&fb_info);
1385 iounmap(par->io_virt);
1386 iounmap(fb_info.screen_base);
1387 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1388 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1391 /* List of boards that we are trying to support */
1392 static struct pci_device_id trident_devices[] = {
1393 {PCI_VENDOR_ID_TRIDENT, BLADE3D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1394 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1395 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1396 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1397 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1398 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1399 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1400 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEE4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1401 {PCI_VENDOR_ID_TRIDENT, TGUI9660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1402 {PCI_VENDOR_ID_TRIDENT, IMAGE975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1403 {PCI_VENDOR_ID_TRIDENT, IMAGE985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1404 {PCI_VENDOR_ID_TRIDENT, CYBER9320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1405 {PCI_VENDOR_ID_TRIDENT, CYBER9388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1406 {PCI_VENDOR_ID_TRIDENT, CYBER9520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1407 {PCI_VENDOR_ID_TRIDENT, CYBER9525DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1408 {PCI_VENDOR_ID_TRIDENT, CYBER9397, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1409 {PCI_VENDOR_ID_TRIDENT, CYBER9397DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1410 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1411 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1412 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm16, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1416 MODULE_DEVICE_TABLE(pci, trident_devices);
1418 static struct pci_driver tridentfb_pci_driver = {
1419 .name = "tridentfb",
1420 .id_table = trident_devices,
1421 .probe = trident_pci_probe,
1422 .remove = __devexit_p(trident_pci_remove)
1426 * Parse user specified options (`video=trident:')
1428 * video=trident:800x600,bpp=16,noaccel
1431 static int __init tridentfb_setup(char *options)
1434 if (!options || !*options)
1436 while ((opt = strsep(&options, ",")) != NULL) {
1439 if (!strncmp(opt, "noaccel", 7))
1441 else if (!strncmp(opt, "fp", 2))
1442 displaytype = DISPLAY_FP;
1443 else if (!strncmp(opt, "crt", 3))
1444 displaytype = DISPLAY_CRT;
1445 else if (!strncmp(opt, "bpp=", 4))
1446 bpp = simple_strtoul(opt + 4, NULL, 0);
1447 else if (!strncmp(opt, "center", 6))
1449 else if (!strncmp(opt, "stretch", 7))
1451 else if (!strncmp(opt, "memsize=", 8))
1452 memsize = simple_strtoul(opt + 8, NULL, 0);
1453 else if (!strncmp(opt, "memdiff=", 8))
1454 memdiff = simple_strtoul(opt + 8, NULL, 0);
1455 else if (!strncmp(opt, "nativex=", 8))
1456 nativex = simple_strtoul(opt + 8, NULL, 0);
1464 static int __init tridentfb_init(void)
1467 char *option = NULL;
1469 if (fb_get_options("tridentfb", &option))
1471 tridentfb_setup(option);
1473 output("Trident framebuffer %s initializing\n", VERSION);
1474 return pci_register_driver(&tridentfb_pci_driver);
1477 static void __exit tridentfb_exit(void)
1479 pci_unregister_driver(&tridentfb_pci_driver);
1482 module_init(tridentfb_init);
1483 module_exit(tridentfb_exit);
1485 MODULE_AUTHOR("Jani Monoses <jani@iv.ro>");
1486 MODULE_DESCRIPTION("Framebuffer driver for Trident cards");
1487 MODULE_LICENSE("GPL");