2 * File: drivers/video/omap/omap1/sossi.c
4 * OMAP1 Special OptimiSed Screen Interface support
6 * Copyright (C) 2004-2005 Nokia Corporation
7 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 #include <linux/config.h>
25 #include <linux/module.h>
27 #include <linux/clk.h>
31 #include <asm/arch/dma.h>
32 #include <asm/arch/omapfb.h>
36 /* #define OMAPFB_DBG 1 */
40 #define MODULE_NAME "omapfb-sossi"
42 #define OMAP_SOSSI_BASE 0xfffbac00
43 #define SOSSI_ID_REG 0x00
44 #define SOSSI_INIT1_REG 0x04
45 #define SOSSI_INIT2_REG 0x08
46 #define SOSSI_INIT3_REG 0x0c
47 #define SOSSI_FIFO_REG 0x10
48 #define SOSSI_REOTABLE_REG 0x14
49 #define SOSSI_TEARING_REG 0x18
50 #define SOSSI_INIT1B_REG 0x1c
51 #define SOSSI_FIFOB_REG 0x20
53 #define DMA_GSCR 0xfffedc04
54 #define DMA_LCD_CCR 0xfffee3c2
55 #define DMA_LCD_CTRL 0xfffee3c4
56 #define DMA_LCD_LCH_CTRL 0xfffee3ea
61 #define SOSSI_MAX_XMIT_BYTES (512 * 1024)
63 #define pr_err(fmt, args...) printk(KERN_ERR MODULE_NAME ": " fmt, ## args)
67 unsigned long dpll_khz;
69 void (*lcdc_callback)(void *data);
70 void *lcdc_callback_data;
71 /* timing for read and write access */
75 /* if last_access is the same as current we don't have to change
81 struct lcd_ctrl_extif sossi_extif;
83 static inline u32 sossi_read_reg(int reg)
85 return readl(sossi.base + reg);
88 static inline u16 sossi_read_reg16(int reg)
90 return readw(sossi.base + reg);
93 static inline u8 sossi_read_reg8(int reg)
95 return readb(sossi.base + reg);
98 static inline void sossi_write_reg(int reg, u32 value)
100 writel(value, sossi.base + reg);
103 static inline void sossi_write_reg16(int reg, u16 value)
105 writew(value, sossi.base + reg);
108 static inline void sossi_write_reg8(int reg, u8 value)
110 writeb(value, sossi.base + reg);
113 static void sossi_set_bits(int reg, u32 bits)
115 sossi_write_reg(reg, sossi_read_reg(reg) | bits);
118 static void sossi_clear_bits(int reg, u32 bits)
120 sossi_write_reg(reg, sossi_read_reg(reg) & ~bits);
123 #define MOD_CONF_CTRL_1 0xfffe1110
124 #define CONF_SOSSI_RESET_R (1 << 23)
125 #define CONF_MOD_SOSSI_CLK_EN_R (1 << 16)
127 static void sossi_dma_callback(void *data);
129 static int sossi_init(void)
132 struct clk *dpll_clk;
135 sossi.base = IO_ADDRESS(OMAP_SOSSI_BASE);
137 dpll_clk = clk_get(NULL, "ck_dpll1");
138 if (IS_ERR(dpll_clk)) {
139 pr_err("can't get dpll1 clock\n");
140 return PTR_ERR(dpll_clk);
143 sossi.dpll_khz = clk_get_rate(dpll_clk) / 1000;
146 sossi_extif.max_transmit_size = SOSSI_MAX_XMIT_BYTES;
148 /* Reset and enable the SoSSI module */
149 l = omap_readl(MOD_CONF_CTRL_1);
150 l |= CONF_SOSSI_RESET_R;
151 omap_writel(l, MOD_CONF_CTRL_1);
152 l &= ~CONF_SOSSI_RESET_R;
153 omap_writel(l, MOD_CONF_CTRL_1);
155 l |= CONF_MOD_SOSSI_CLK_EN_R;
156 omap_writel(l, MOD_CONF_CTRL_1);
158 omap_writel(omap_readl(ARM_IDLECT2) | (1 << 11), ARM_IDLECT2);
159 omap_writel(omap_readl(ARM_IDLECT1) | (1 << 6), ARM_IDLECT1);
161 l = sossi_read_reg(SOSSI_INIT2_REG);
162 /* Enable and reset the SoSSI block */
163 l |= (1 << 0) | (1 << 1);
164 sossi_write_reg(SOSSI_INIT2_REG, l);
165 /* Take SoSSI out of reset */
167 sossi_write_reg(SOSSI_INIT2_REG, l);
169 sossi_write_reg(SOSSI_ID_REG, 0);
170 l = sossi_read_reg(SOSSI_ID_REG);
171 k = sossi_read_reg(SOSSI_ID_REG);
173 if (l != 0x55555555 || k != 0xaaaaaaaa) {
174 pr_err("Invalid SoSSI sync pattern: %08x, %08x\n", l, k);
178 if ((r = omap_lcdc_set_dma_callback(sossi_dma_callback, NULL)) < 0) {
179 pr_err("can't get LCDC IRQ\n");
183 l = sossi_read_reg(SOSSI_ID_REG); /* Component code */
184 l = sossi_read_reg(SOSSI_ID_REG);
185 pr_info(KERN_INFO MODULE_NAME ": version %d.%d initialized\n",
186 l >> 16, l & 0xffff);
188 l = sossi_read_reg(SOSSI_INIT1_REG);
189 l |= (1 << 19); /* DMA_MODE */
190 l &= ~(1 << 31); /* REORDERING */
191 sossi_write_reg(SOSSI_INIT1_REG, l);
196 static void sossi_cleanup(void)
198 omap_lcdc_free_dma_callback();
201 #define KHZ_TO_PS(x) (1000000000 / (x))
203 static void sossi_get_clk_info(u32 *clk_period, u32 *max_clk_div)
205 *clk_period = KHZ_TO_PS(sossi.dpll_khz);
209 static u32 ps_to_sossi_ticks(u32 ps, int div)
211 u32 clk_period = KHZ_TO_PS(sossi.dpll_khz) * div;
212 return (clk_period + ps - 1) / clk_period;
215 static int calc_rd_timings(struct extif_timings *t)
218 int reon, reoff, recyc, actim;
219 int div = t->clk_div;
221 /* Make sure that after conversion it still holds that:
222 * reoff > reon, recyc >= reoff, actim > reon
224 reon = ps_to_sossi_ticks(t->re_on_time, div);
225 /* reon will be exactly one sossi tick */
229 reoff = ps_to_sossi_ticks(t->re_off_time, div);
238 recyc = ps_to_sossi_ticks(t->re_cycle_time, div);
246 actim = ps_to_sossi_ticks(t->access_time, div);
249 /* access time (data hold time) will be exactly one sossi
252 if (actim - reoff > 1)
261 static int calc_wr_timings(struct extif_timings *t)
264 int weon, weoff, wecyc;
265 int div = t->clk_div;
267 /* Make sure that after conversion it still holds that:
268 * weoff > weon, wecyc >= weoff
270 weon = ps_to_sossi_ticks(t->we_on_time, div);
271 /* weon will be exactly one sossi tick */
275 weoff = ps_to_sossi_ticks(t->we_off_time, div);
282 wecyc = ps_to_sossi_ticks(t->we_cycle_time, div);
296 static int sossi_convert_timings(struct extif_timings *t)
299 int div = t->clk_div;
303 if (div <= 0 || div > 8)
306 /* no CS on SOSSI, so ignore cson, csoff, cs_pulsewidth */
307 if ((r = calc_rd_timings(t)) < 0)
310 if ((r = calc_wr_timings(t)) < 0)
320 static void sossi_set_timings(const struct extif_timings *t)
322 BUG_ON(!t->converted);
324 sossi.clk_tw0[RD_ACCESS] = t->tim[0];
325 sossi.clk_tw1[RD_ACCESS] = t->tim[1];
327 sossi.clk_tw0[WR_ACCESS] = t->tim[2];
328 sossi.clk_tw1[WR_ACCESS] = t->tim[3];
330 sossi.clk_div = t->tim[4];
333 static void _set_timing(int div, int tw0, int tw1)
337 DBGPRINT(2, "Using TW0 = %d, TW1 = %d, div = %d\n",
338 tw0 + 1, tw1 + 1, div + 1);
340 l = omap_readl(MOD_CONF_CTRL_1);
343 omap_writel(l, MOD_CONF_CTRL_1);
345 l = sossi_read_reg(SOSSI_INIT1_REG);
346 l &= ~((0x0f << 20) | (0x3f << 24));
347 l |= (tw0 << 20) | (tw1 << 24);
348 sossi_write_reg(SOSSI_INIT1_REG, l);
351 static inline void set_timing(int access)
353 if (access != sossi.last_access) {
354 sossi.last_access = access;
355 _set_timing(sossi.clk_div,
356 sossi.clk_tw0[access], sossi.clk_tw1[access]);
360 static void sossi_set_bits_per_cycle(int bpc)
363 int bus_pick_count, bus_pick_width;
365 DBGPRINT(2, "bits_per_cycle %d\n", bpc);
366 /* We set explicitly the the bus_pick_count as well, although
367 * with remapping/reordering disabled it will be calculated by HW
368 * as (32 / bus_pick_width).
383 l = sossi_read_reg(SOSSI_INIT3_REG);
384 sossi.bus_pick_width = bus_pick_width;
386 l |= ((bus_pick_count - 1) << 5) | ((bus_pick_width - 1) & 0x1f);
387 sossi_write_reg(SOSSI_INIT3_REG, l);
390 static void sossi_start_transfer(void)
393 sossi_clear_bits(SOSSI_INIT2_REG, 1 << 4);
395 sossi_clear_bits(SOSSI_INIT1_REG, 1 << 30);
396 /* FIXME: locking? */
399 static void sossi_stop_transfer(void)
402 sossi_set_bits(SOSSI_INIT2_REG, 1 << 4);
404 sossi_set_bits(SOSSI_INIT1_REG, 1 << 30);
405 /* FIXME: locking? */
408 static void wait_end_of_write(void)
410 /* Before reading we must check if some writings are going on */
411 while (!(sossi_read_reg(SOSSI_INIT2_REG) & (1 << 3)));
414 static void send_data(const void *data, unsigned int len)
417 sossi_write_reg(SOSSI_FIFO_REG, *(const u32 *) data);
422 sossi_write_reg16(SOSSI_FIFO_REG, *(const u16 *) data);
427 sossi_write_reg8(SOSSI_FIFO_REG, *(const u8 *) data);
433 static void set_cycles(unsigned int len)
435 unsigned long nr_cycles = len / (sossi.bus_pick_width / 8);
437 BUG_ON((nr_cycles - 1) & ~0x3ffff);
439 sossi_clear_bits(SOSSI_INIT1_REG, 0x3ffff);
440 sossi_set_bits(SOSSI_INIT1_REG, (nr_cycles - 1) & 0x3ffff);
443 static void sossi_write_command(const void *data, unsigned int len)
445 set_timing(WR_ACCESS);
447 sossi_clear_bits(SOSSI_INIT1_REG, 1 << 18);
449 sossi_start_transfer();
450 send_data(data, len);
451 sossi_stop_transfer();
455 static void sossi_write_data(const void *data, unsigned int len)
457 set_timing(WR_ACCESS);
459 sossi_set_bits(SOSSI_INIT1_REG, 1 << 18);
461 sossi_start_transfer();
462 send_data(data, len);
463 sossi_stop_transfer();
467 static void sossi_transfer_area(int width, int height,
468 void (callback)(void *data), void *data)
470 BUG_ON(callback == NULL);
472 sossi.lcdc_callback = callback;
473 sossi.lcdc_callback_data = data;
475 set_timing(WR_ACCESS);
477 sossi_set_bits(SOSSI_INIT1_REG, 1 << 18);
478 set_cycles(width * height * sossi.bus_pick_width / 8);
480 DBGPRINT(2, "SOSSI_INIT1_REG %08x\n", sossi_read_reg(SOSSI_INIT1_REG));
482 sossi_start_transfer();
483 omap_enable_lcd_dma();
486 static void sossi_dma_callback(void *data)
489 sossi_stop_transfer();
490 sossi.lcdc_callback(sossi.lcdc_callback_data);
493 static void sossi_read_data(void *data, unsigned int len)
495 set_timing(RD_ACCESS);
497 sossi_set_bits(SOSSI_INIT1_REG, 1 << 18);
499 sossi_start_transfer();
501 *(u32 *) data = sossi_read_reg(SOSSI_FIFO_REG);
506 *(u16 *) data = sossi_read_reg16(SOSSI_FIFO_REG);
511 *(u8 *) data = sossi_read_reg8(SOSSI_FIFO_REG);
515 sossi_stop_transfer();
518 struct lcd_ctrl_extif sossi_extif = {
520 .cleanup = sossi_cleanup,
521 .get_clk_info = sossi_get_clk_info,
522 .convert_timings = sossi_convert_timings,
523 .set_timings = sossi_set_timings,
524 .set_bits_per_cycle = sossi_set_bits_per_cycle,
525 .write_command = sossi_write_command,
526 .read_data = sossi_read_data,
527 .write_data = sossi_write_data,
528 .transfer_area = sossi_transfer_area,