2 * File: drivers/video/omap/omap1/sossi.c
4 * OMAP1 Special OptimiSed Screen Interface support
6 * Copyright (C) 2004-2005 Nokia Corporation
7 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 #include <linux/module.h>
25 #include <linux/clk.h>
26 #include <linux/irq.h>
30 #include <asm/arch/dma.h>
31 #include <asm/arch/omapfb.h>
35 #define MODULE_NAME "omapfb-sossi"
37 #define OMAP_SOSSI_BASE 0xfffbac00
38 #define SOSSI_ID_REG 0x00
39 #define SOSSI_INIT1_REG 0x04
40 #define SOSSI_INIT2_REG 0x08
41 #define SOSSI_INIT3_REG 0x0c
42 #define SOSSI_FIFO_REG 0x10
43 #define SOSSI_REOTABLE_REG 0x14
44 #define SOSSI_TEARING_REG 0x18
45 #define SOSSI_INIT1B_REG 0x1c
46 #define SOSSI_FIFOB_REG 0x20
48 #define DMA_GSCR 0xfffedc04
49 #define DMA_LCD_CCR 0xfffee3c2
50 #define DMA_LCD_CTRL 0xfffee3c4
51 #define DMA_LCD_LCH_CTRL 0xfffee3ea
53 #define CONF_SOSSI_RESET_R (1 << 23)
58 #define SOSSI_MAX_XMIT_BYTES (512 * 1024)
69 void (*lcdc_callback)(void *data);
70 void *lcdc_callback_data;
71 int vsync_dma_pending;
72 /* timing for read and write access */
76 /* if last_access is the same as current we don't have to change
81 struct omapfb_device *fbdev;
84 static inline u32 sossi_read_reg(int reg)
86 return readl(sossi.base + reg);
89 static inline u16 sossi_read_reg16(int reg)
91 return readw(sossi.base + reg);
94 static inline u8 sossi_read_reg8(int reg)
96 return readb(sossi.base + reg);
99 static inline void sossi_write_reg(int reg, u32 value)
101 writel(value, sossi.base + reg);
104 static inline void sossi_write_reg16(int reg, u16 value)
106 writew(value, sossi.base + reg);
109 static inline void sossi_write_reg8(int reg, u8 value)
111 writeb(value, sossi.base + reg);
114 static void sossi_set_bits(int reg, u32 bits)
116 sossi_write_reg(reg, sossi_read_reg(reg) | bits);
119 static void sossi_clear_bits(int reg, u32 bits)
121 sossi_write_reg(reg, sossi_read_reg(reg) & ~bits);
124 #define HZ_TO_PS(x) (1000000000 / (x / 1000))
126 static u32 ps_to_sossi_ticks(u32 ps, int div)
128 u32 clk_period = HZ_TO_PS(sossi.fck_hz) * div;
129 return (clk_period + ps - 1) / clk_period;
132 static int calc_rd_timings(struct extif_timings *t)
135 int reon, reoff, recyc, actim;
136 int div = t->clk_div;
138 /* Make sure that after conversion it still holds that:
139 * reoff > reon, recyc >= reoff, actim > reon
141 reon = ps_to_sossi_ticks(t->re_on_time, div);
142 /* reon will be exactly one sossi tick */
146 reoff = ps_to_sossi_ticks(t->re_off_time, div);
155 recyc = ps_to_sossi_ticks(t->re_cycle_time, div);
160 /* values less then 3 result in the SOSSI block resetting itself */
166 actim = ps_to_sossi_ticks(t->access_time, div);
169 /* access time (data hold time) will be exactly one sossi
172 if (actim - reoff > 1)
181 static int calc_wr_timings(struct extif_timings *t)
184 int weon, weoff, wecyc;
185 int div = t->clk_div;
187 /* Make sure that after conversion it still holds that:
188 * weoff > weon, wecyc >= weoff
190 weon = ps_to_sossi_ticks(t->we_on_time, div);
191 /* weon will be exactly one sossi tick */
195 weoff = ps_to_sossi_ticks(t->we_off_time, div);
202 wecyc = ps_to_sossi_ticks(t->we_cycle_time, div);
207 /* values less then 3 result in the SOSSI block resetting itself */
219 static void _set_timing(int div, int tw0, int tw1)
224 dev_dbg(sossi.fbdev->dev, "Using TW0 = %d, TW1 = %d, div = %d\n",
225 tw0 + 1, tw1 + 1, div);
228 clk_set_rate(sossi.fck, sossi.fck_hz / div);
229 clk_enable(sossi.fck);
230 l = sossi_read_reg(SOSSI_INIT1_REG);
231 l &= ~((0x0f << 20) | (0x3f << 24));
232 l |= (tw0 << 20) | (tw1 << 24);
233 sossi_write_reg(SOSSI_INIT1_REG, l);
234 clk_disable(sossi.fck);
237 static void _set_bits_per_cycle(int bus_pick_count, int bus_pick_width)
241 l = sossi_read_reg(SOSSI_INIT3_REG);
243 l |= ((bus_pick_count - 1) << 5) | ((bus_pick_width - 1) & 0x1f);
244 sossi_write_reg(SOSSI_INIT3_REG, l);
247 static void _set_tearsync_mode(int mode, unsigned line)
251 l = sossi_read_reg(SOSSI_TEARING_REG);
252 l &= ~(((1 << 11) - 1) << 15);
256 sossi_write_reg(SOSSI_TEARING_REG, l);
258 sossi_set_bits(SOSSI_INIT2_REG, 1 << 6); /* TE logic */
260 sossi_clear_bits(SOSSI_INIT2_REG, 1 << 6);
263 static inline void set_timing(int access)
265 if (access != sossi.last_access) {
266 sossi.last_access = access;
267 _set_timing(sossi.clk_div,
268 sossi.clk_tw0[access], sossi.clk_tw1[access]);
272 static void sossi_start_transfer(void)
275 sossi_clear_bits(SOSSI_INIT2_REG, 1 << 4);
277 sossi_clear_bits(SOSSI_INIT1_REG, 1 << 30);
280 static void sossi_stop_transfer(void)
283 sossi_set_bits(SOSSI_INIT2_REG, 1 << 4);
285 sossi_set_bits(SOSSI_INIT1_REG, 1 << 30);
288 static void wait_end_of_write(void)
290 /* Before reading we must check if some writings are going on */
291 while (!(sossi_read_reg(SOSSI_INIT2_REG) & (1 << 3)));
294 static void send_data(const void *data, unsigned int len)
297 sossi_write_reg(SOSSI_FIFO_REG, *(const u32 *) data);
302 sossi_write_reg16(SOSSI_FIFO_REG, *(const u16 *) data);
307 sossi_write_reg8(SOSSI_FIFO_REG, *(const u8 *) data);
313 static void set_cycles(unsigned int len)
315 unsigned long nr_cycles = len / (sossi.bus_pick_width / 8);
317 BUG_ON((nr_cycles - 1) & ~0x3ffff);
319 sossi_clear_bits(SOSSI_INIT1_REG, 0x3ffff);
320 sossi_set_bits(SOSSI_INIT1_REG, (nr_cycles - 1) & 0x3ffff);
323 static int sossi_convert_timings(struct extif_timings *t)
326 int div = t->clk_div;
330 if (div <= 0 || div > 8)
333 /* no CS on SOSSI, so ignore cson, csoff, cs_pulsewidth */
334 if ((r = calc_rd_timings(t)) < 0)
337 if ((r = calc_wr_timings(t)) < 0)
347 static void sossi_set_timings(const struct extif_timings *t)
349 BUG_ON(!t->converted);
351 sossi.clk_tw0[RD_ACCESS] = t->tim[0];
352 sossi.clk_tw1[RD_ACCESS] = t->tim[1];
354 sossi.clk_tw0[WR_ACCESS] = t->tim[2];
355 sossi.clk_tw1[WR_ACCESS] = t->tim[3];
357 sossi.clk_div = t->tim[4];
360 static void sossi_get_clk_info(u32 *clk_period, u32 *max_clk_div)
362 *clk_period = HZ_TO_PS(sossi.fck_hz);
366 static void sossi_set_bits_per_cycle(int bpc)
368 int bus_pick_count, bus_pick_width;
370 /* We set explicitly the the bus_pick_count as well, although
371 * with remapping/reordering disabled it will be calculated by HW
372 * as (32 / bus_pick_width).
387 sossi.bus_pick_width = bus_pick_width;
388 sossi.bus_pick_count = bus_pick_count;
391 static int sossi_setup_tearsync(unsigned pin_cnt,
392 unsigned hs_pulse_time, unsigned vs_pulse_time,
393 int hs_pol_inv, int vs_pol_inv, int div)
398 if (pin_cnt != 1 || div < 1 || div > 8)
401 hs = ps_to_sossi_ticks(hs_pulse_time, div);
402 vs = ps_to_sossi_ticks(vs_pulse_time, div);
403 if (vs < 8 || vs <= hs || vs >= (1 << 12))
412 dev_dbg(sossi.fbdev->dev,
413 "setup_tearsync: hs %d vs %d hs_inv %d vs_inv %d\n",
414 hs, vs, hs_pol_inv, vs_pol_inv);
416 clk_enable(sossi.fck);
417 l = sossi_read_reg(SOSSI_TEARING_REG);
418 l &= ~((1 << 15) - 1);
429 sossi_write_reg(SOSSI_TEARING_REG, l);
430 clk_disable(sossi.fck);
435 static int sossi_enable_tearsync(int enable, unsigned line)
439 dev_dbg(sossi.fbdev->dev, "tearsync %d line %d\n", enable, line);
444 mode = 2; /* HS or VS */
446 mode = 3; /* VS only */
449 sossi.tearsync_line = line;
450 sossi.tearsync_mode = mode;
455 static void sossi_write_command(const void *data, unsigned int len)
457 clk_enable(sossi.fck);
458 set_timing(WR_ACCESS);
459 _set_bits_per_cycle(sossi.bus_pick_count, sossi.bus_pick_width);
461 sossi_clear_bits(SOSSI_INIT1_REG, 1 << 18);
463 sossi_start_transfer();
464 send_data(data, len);
465 sossi_stop_transfer();
467 clk_disable(sossi.fck);
470 static void sossi_write_data(const void *data, unsigned int len)
472 clk_enable(sossi.fck);
473 set_timing(WR_ACCESS);
474 _set_bits_per_cycle(sossi.bus_pick_count, sossi.bus_pick_width);
476 sossi_set_bits(SOSSI_INIT1_REG, 1 << 18);
478 sossi_start_transfer();
479 send_data(data, len);
480 sossi_stop_transfer();
482 clk_disable(sossi.fck);
485 static void sossi_transfer_area(int width, int height,
486 void (callback)(void *data), void *data)
488 BUG_ON(callback == NULL);
490 sossi.lcdc_callback = callback;
491 sossi.lcdc_callback_data = data;
493 clk_enable(sossi.fck);
494 set_timing(WR_ACCESS);
495 _set_bits_per_cycle(sossi.bus_pick_count, sossi.bus_pick_width);
496 _set_tearsync_mode(sossi.tearsync_mode, sossi.tearsync_line);
498 sossi_set_bits(SOSSI_INIT1_REG, 1 << 18);
499 set_cycles(width * height * sossi.bus_pick_width / 8);
501 sossi_start_transfer();
502 if (sossi.tearsync_mode) {
503 /* Wait for the sync signal and start the transfer only
504 * then. We can't seem to be able to use HW sync DMA for
505 * this since LCD DMA shows huge latencies, as if it
506 * would ignore some of the DMA requests from SoSSI.
510 spin_lock_irqsave(&sossi.lock, flags);
511 sossi.vsync_dma_pending++;
512 spin_unlock_irqrestore(&sossi.lock, flags);
514 /* Just start the transfer right away. */
515 omap_enable_lcd_dma();
518 static void sossi_dma_callback(void *data)
521 sossi_stop_transfer();
522 clk_disable(sossi.fck);
523 sossi.lcdc_callback(sossi.lcdc_callback_data);
526 static void sossi_read_data(void *data, unsigned int len)
528 clk_enable(sossi.fck);
529 set_timing(RD_ACCESS);
530 _set_bits_per_cycle(sossi.bus_pick_count, sossi.bus_pick_width);
532 sossi_set_bits(SOSSI_INIT1_REG, 1 << 18);
534 sossi_start_transfer();
536 *(u32 *) data = sossi_read_reg(SOSSI_FIFO_REG);
541 *(u16 *) data = sossi_read_reg16(SOSSI_FIFO_REG);
546 *(u8 *) data = sossi_read_reg8(SOSSI_FIFO_REG);
550 sossi_stop_transfer();
551 clk_disable(sossi.fck);
554 static irqreturn_t sossi_match_irq(int irq, void *data)
558 spin_lock_irqsave(&sossi.lock, flags);
559 if (sossi.vsync_dma_pending) {
560 sossi.vsync_dma_pending--;
561 omap_enable_lcd_dma();
563 spin_unlock_irqrestore(&sossi.lock, flags);
567 static int sossi_init(struct omapfb_device *fbdev)
571 struct clk *dpll1out_ck;
574 sossi.base = (void __iomem *)IO_ADDRESS(OMAP_SOSSI_BASE);
576 spin_lock_init(&sossi.lock);
578 dpll1out_ck = clk_get(fbdev->dev, "ck_dpll1out");
579 if (IS_ERR(dpll1out_ck)) {
580 dev_err(fbdev->dev, "can't get DPLL1OUT clock\n");
581 return PTR_ERR(dpll1out_ck);
583 /* We need the parent clock rate, which we might divide further
584 * depending on the timing requirements of the controller. See
587 sossi.fck_hz = clk_get_rate(dpll1out_ck);
588 clk_put(dpll1out_ck);
590 fck = clk_get(fbdev->dev, "ck_sossi");
592 dev_err(fbdev->dev, "can't get SoSSI functional clock\n");
597 /* Reset and enable the SoSSI module */
598 l = omap_readl(MOD_CONF_CTRL_1);
599 l |= CONF_SOSSI_RESET_R;
600 omap_writel(l, MOD_CONF_CTRL_1);
601 l &= ~CONF_SOSSI_RESET_R;
602 omap_writel(l, MOD_CONF_CTRL_1);
604 clk_enable(sossi.fck);
605 l = omap_readl(ARM_IDLECT2);
606 l &= ~(1 << 8); /* DMACK_REQ */
607 omap_writel(l, ARM_IDLECT2);
609 l = sossi_read_reg(SOSSI_INIT2_REG);
610 /* Enable and reset the SoSSI block */
611 l |= (1 << 0) | (1 << 1);
612 sossi_write_reg(SOSSI_INIT2_REG, l);
613 /* Take SoSSI out of reset */
615 sossi_write_reg(SOSSI_INIT2_REG, l);
617 sossi_write_reg(SOSSI_ID_REG, 0);
618 l = sossi_read_reg(SOSSI_ID_REG);
619 k = sossi_read_reg(SOSSI_ID_REG);
621 if (l != 0x55555555 || k != 0xaaaaaaaa) {
623 "invalid SoSSI sync pattern: %08x, %08x\n", l, k);
628 if ((r = omap_lcdc_set_dma_callback(sossi_dma_callback, NULL)) < 0) {
629 dev_err(fbdev->dev, "can't get LCDC IRQ\n");
634 l = sossi_read_reg(SOSSI_ID_REG); /* Component code */
635 l = sossi_read_reg(SOSSI_ID_REG);
636 dev_info(fbdev->dev, "SoSSI version %d.%d initialized\n",
637 l >> 16, l & 0xffff);
639 l = sossi_read_reg(SOSSI_INIT1_REG);
640 l |= (1 << 19); /* DMA_MODE */
641 l &= ~(1 << 31); /* REORDERING */
642 sossi_write_reg(SOSSI_INIT1_REG, l);
644 if ((r = request_irq(INT_1610_SoSSI_MATCH, sossi_match_irq,
646 "sossi_match", sossi.fbdev->dev)) < 0) {
647 dev_err(sossi.fbdev->dev, "can't get SoSSI match IRQ\n");
651 clk_disable(sossi.fck);
655 clk_disable(sossi.fck);
660 static void sossi_cleanup(void)
662 omap_lcdc_free_dma_callback();
666 struct lcd_ctrl_extif omap1_ext_if = {
668 .cleanup = sossi_cleanup,
669 .get_clk_info = sossi_get_clk_info,
670 .convert_timings = sossi_convert_timings,
671 .set_timings = sossi_set_timings,
672 .set_bits_per_cycle = sossi_set_bits_per_cycle,
673 .setup_tearsync = sossi_setup_tearsync,
674 .enable_tearsync = sossi_enable_tearsync,
675 .write_command = sossi_write_command,
676 .read_data = sossi_read_data,
677 .write_data = sossi_write_data,
678 .transfer_area = sossi_transfer_area,
680 .max_transmit_size = SOSSI_MAX_XMIT_BYTES,