drivers/video/omap/lcdc.c

   1 /*
   2  * File: drivers/video/omap/omap1/lcdc.c
   3  *
   4  * OMAP1 internal LCD controller
   5  *
   6  * Copyright (C) 2004 Nokia Corporation
   7  * Author: Imre Deak <imre.deak@nokia.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of the GNU General Public License as published by the
  11  * Free Software Foundation; either version 2 of the License, or (at your
  12  * option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along
  20  * with this program; if not, write to the Free Software Foundation, Inc.,
  21  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  22  */
  23 #include <linux/config.h>
  24 #include <linux/module.h>
  25 #include <linux/device.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/spinlock.h>
  28 #include <linux/err.h>
  29 #include <linux/mm.h>
  30 #include <linux/fb.h>
  31 #include <linux/dma-mapping.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/clk.h>
  34
  35 #include <asm/arch/dma.h>
  36 #include <asm/arch/omapfb.h>
  37
  38 #include <asm/mach-types.h>
  39
  40 #define MODULE_NAME                     "lcdc"
  41
  42 #define OMAP_LCDC_BASE                  0xfffec000
  43 #define OMAP_LCDC_SIZE                  256
  44 #define OMAP_LCDC_IRQ                   INT_LCD_CTRL
  45
  46 #define OMAP_LCDC_CONTROL               (OMAP_LCDC_BASE + 0x00)
  47 #define OMAP_LCDC_TIMING0               (OMAP_LCDC_BASE + 0x04)
  48 #define OMAP_LCDC_TIMING1               (OMAP_LCDC_BASE + 0x08)
  49 #define OMAP_LCDC_TIMING2               (OMAP_LCDC_BASE + 0x0c)
  50 #define OMAP_LCDC_STATUS                (OMAP_LCDC_BASE + 0x10)
  51 #define OMAP_LCDC_SUBPANEL              (OMAP_LCDC_BASE + 0x14)
  52 #define OMAP_LCDC_LINE_INT              (OMAP_LCDC_BASE + 0x18)
  53 #define OMAP_LCDC_DISPLAY_STATUS        (OMAP_LCDC_BASE + 0x1c)
  54
  55 #define OMAP_LCDC_STAT_DONE             (1 << 0)
  56 #define OMAP_LCDC_STAT_VSYNC            (1 << 1)
  57 #define OMAP_LCDC_STAT_SYNC_LOST        (1 << 2)
  58 #define OMAP_LCDC_STAT_ABC              (1 << 3)
  59 #define OMAP_LCDC_STAT_LINE_INT         (1 << 4)
  60 #define OMAP_LCDC_STAT_FUF              (1 << 5)
  61 #define OMAP_LCDC_STAT_LOADED_PALETTE   (1 << 6)
  62
  63 #define OMAP_LCDC_CTRL_LCD_EN           (1 << 0)
  64 #define OMAP_LCDC_CTRL_LCD_TFT          (1 << 7)
  65 #define OMAP_LCDC_CTRL_LINE_IRQ_CLR_SEL (1 << 10)
  66
  67 #define OMAP_LCDC_IRQ_VSYNC             (1 << 2)
  68 #define OMAP_LCDC_IRQ_DONE              (1 << 3)
  69 #define OMAP_LCDC_IRQ_LOADED_PALETTE    (1 << 4)
  70 #define OMAP_LCDC_IRQ_LINE_NIRQ         (1 << 5)
  71 #define OMAP_LCDC_IRQ_LINE              (1 << 6)
  72 #define OMAP_LCDC_IRQ_MASK              (((1 << 5) - 1) << 2)
  73
  74 #define MAX_PALETTE_SIZE                PAGE_SIZE
  75
  76 enum lcdc_load_mode {
  77         OMAP_LCDC_LOAD_PALETTE,
  78         OMAP_LCDC_LOAD_FRAME,
  79         OMAP_LCDC_LOAD_PALETTE_AND_FRAME
  80 };
  81
  82 static struct omap_lcd_controller {
  83         enum omapfb_update_mode update_mode;
  84         int                     ext_mode;
  85
  86         unsigned long           frame_offset;
  87         int                     screen_width;
  88         int                     xres;
  89         int                     yres;
  90
  91         enum omapfb_color_format        color_mode;
  92         int                     bpp;
  93         void                    *palette_virt;
  94         dma_addr_t              palette_phys;
  95         int                     palette_code;
  96         int                     palette_size;
  97
  98         unsigned int            irq_mask;
  99         struct completion       last_frame_complete;
 100         struct completion       palette_load_complete;
 101         struct clk              *lcd_ck;
 102         struct omapfb_device    *fbdev;
 103
 104         void                    (*dma_callback)(void *data);
 105         void                    *dma_callback_data;
 106
 107         int                     fbmem_allocated;
 108         dma_addr_t              vram_phys;
 109         void                    *vram_virt;
 110         unsigned long           vram_size;
 111 } lcdc;
 112
 113 static void inline enable_irqs(int mask)
 114 {
 115         lcdc.irq_mask |= mask;
 116 }
 117
 118 static void inline disable_irqs(int mask)
 119 {
 120         lcdc.irq_mask &= ~mask;
 121 }
 122
 123 static void set_load_mode(enum lcdc_load_mode mode)
 124 {
 125         u32 l;
 126
 127         l = omap_readl(OMAP_LCDC_CONTROL);
 128         l &= ~(3 << 20);
 129         switch (mode) {
 130         case OMAP_LCDC_LOAD_PALETTE:
 131                 l |= 1 << 20;
 132                 break;
 133         case OMAP_LCDC_LOAD_FRAME:
 134                 l |= 2 << 20;
 135                 break;
 136         case OMAP_LCDC_LOAD_PALETTE_AND_FRAME:
 137                 break;
 138         default:
 139                 BUG();
 140         }
 141         omap_writel(l, OMAP_LCDC_CONTROL);
 142 }
 143
 144 static void enable_controller(void)
 145 {
 146         u32 l;
 147
 148         l = omap_readl(OMAP_LCDC_CONTROL);
 149         l |= OMAP_LCDC_CTRL_LCD_EN;
 150         l &= ~OMAP_LCDC_IRQ_MASK;
 151         l |= lcdc.irq_mask | OMAP_LCDC_IRQ_DONE;        /* enabled IRQs */
 152         omap_writel(l, OMAP_LCDC_CONTROL);
 153 }
 154
 155 static void disable_controller_async(void)
 156 {
 157         u32 l;
 158         u32 mask;
 159
 160         l = omap_readl(OMAP_LCDC_CONTROL);
 161         mask = OMAP_LCDC_CTRL_LCD_EN | OMAP_LCDC_IRQ_MASK;
 162         /* Preserve the DONE mask, since we still want to get the
 163          * final DONE irq. It will be disabled in the IRQ handler.
 164          */
 165         mask &= ~OMAP_LCDC_IRQ_DONE;
 166         l &= ~mask;
 167         omap_writel(l, OMAP_LCDC_CONTROL);
 168 }
 169
 170 static void disable_controller(void)
 171 {
 172         init_completion(&lcdc.last_frame_complete);
 173         disable_controller_async();
 174         if (!wait_for_completion_timeout(&lcdc.last_frame_complete,
 175                                 msecs_to_jiffies(500)))
 176                 dev_err(lcdc.fbdev->dev, "timeout waiting for FRAME DONE\n");
 177 }
 178
 179 static void reset_controller(u32 status)
 180 {
 181         static unsigned long reset_count = 0;
 182         static unsigned long last_jiffies = 0;
 183
 184         disable_controller_async();
 185         reset_count++;
 186         if (reset_count == 1 || time_after(jiffies, last_jiffies + HZ)) {
 187                 dev_err(lcdc.fbdev->dev,
 188                           "resetting (status %#010x,reset count %lu)\n",
 189                           status, reset_count);
 190                 last_jiffies = jiffies;
 191         }
 192         if (reset_count < 100) {
 193                 enable_controller();
 194         } else {
 195                 reset_count = 0;
 196                 dev_err(lcdc.fbdev->dev,
 197                         "too many reset attempts, giving up.\n");
 198         }
 199 }
 200
 201 /* Configure the LCD DMA according to the current mode specified by parameters
 202  * in lcdc.fbdev and fbdev->var.
 203  */
 204 static void setup_lcd_dma(void)
 205 {
 206         static const int dma_elem_type[] = {
 207                 0,
 208                 OMAP_DMA_DATA_TYPE_S8,
 209                 OMAP_DMA_DATA_TYPE_S16,
 210                 0,
 211                 OMAP_DMA_DATA_TYPE_S32,
 212         };
 213         struct omapfb_plane_struct *plane = lcdc.fbdev->fb_info[0]->par;
 214         struct fb_var_screeninfo *var = &lcdc.fbdev->fb_info[0]->var;
 215         unsigned long   src;
 216         int             esize, xelem, yelem;
 217
 218         src = lcdc.vram_phys + lcdc.frame_offset;
 219
 220         switch (var->rotate) {
 221         case 0:
 222                 if (plane->info.mirror || (src & 3) ||
 223                     lcdc.color_mode == OMAPFB_COLOR_YUV420 ||
 224                     (lcdc.xres & 1))
 225                         esize = 2;
 226                 else
 227                         esize = 4;
 228                 xelem = lcdc.xres * lcdc.bpp / 8 / esize;
 229                 yelem = lcdc.yres;
 230                 break;
 231         case 90:
 232         case 180:
 233         case 270:
 234                 if (cpu_is_omap15xx()) {
 235                         BUG();
 236                 }
 237                 esize = 2;
 238                 xelem = lcdc.yres * lcdc.bpp / 16;
 239                 yelem = lcdc.xres;
 240                 break;
 241         default:
 242                 BUG();
 243                 return;
 244         }
 245 #ifdef VERBOSE
 246         dev_dbg(lcdc.fbdev->dev,
 247                  "setup_dma: src %#010lx esize %d xelem %d yelem %d\n",
 248                  src, esize, xelem, yelem);
 249 #endif
 250         omap_set_lcd_dma_b1(src, xelem, yelem, dma_elem_type[esize]);
 251         if (!cpu_is_omap15xx()) {
 252                 int bpp = lcdc.bpp;
 253
 254                 /* YUV support is only for external mode when we have the
 255                  * YUV window embedded in a 16bpp frame buffer.
 256                  */
 257                 if (lcdc.color_mode == OMAPFB_COLOR_YUV420)
 258                         bpp = 16;
 259                 /* Set virtual xres elem size */
 260                 omap_set_lcd_dma_b1_vxres(
 261                         lcdc.screen_width * bpp / 8 / esize);
 262                 /* Setup transformations */
 263                 omap_set_lcd_dma_b1_rotation(var->rotate);
 264                 omap_set_lcd_dma_b1_mirror(plane->info.mirror);
 265         }
 266         omap_setup_lcd_dma();
 267 }
 268
 269 static irqreturn_t lcdc_irq_handler(int irq, void *dev_id, struct pt_regs *fp)
 270 {
 271         u32 status;
 272
 273         status = omap_readl(OMAP_LCDC_STATUS);
 274
 275         if (status & (OMAP_LCDC_STAT_FUF | OMAP_LCDC_STAT_SYNC_LOST))
 276                 reset_controller(status);
 277         else {
 278                 if (status & OMAP_LCDC_STAT_DONE) {
 279                         u32 l;
 280
 281                         /* Disable IRQ_DONE. The status bit will be cleared
 282                          * only when the controller is reenabled and we don't
 283                          * want to get more interrupts.
 284                          */
 285                         l = omap_readl(OMAP_LCDC_CONTROL);
 286                         l &= ~OMAP_LCDC_IRQ_DONE;
 287                         omap_writel(l, OMAP_LCDC_CONTROL);
 288                         complete(&lcdc.last_frame_complete);
 289                 }
 290                 if (status & OMAP_LCDC_STAT_LOADED_PALETTE) {
 291                         disable_controller_async();
 292                         complete(&lcdc.palette_load_complete);
 293                 }
 294         }
 295
 296         /* Clear these interrupt status bits.
 297          * Sync_lost, FUF bits were cleared by disabling the LCD controller
 298          * LOADED_PALETTE can be cleared this way only in palette only
 299          * load mode. In other load modes it's cleared by disabling the
 300          * controller.
 301          */
 302         status &= ~(OMAP_LCDC_STAT_VSYNC |
 303                     OMAP_LCDC_STAT_LOADED_PALETTE |
 304                     OMAP_LCDC_STAT_ABC |
 305                     OMAP_LCDC_STAT_LINE_INT);
 306         omap_writel(status, OMAP_LCDC_STATUS);
 307         return IRQ_HANDLED;
 308 }
 309
 310 /* Change to a new video mode. We defer this to a later time to avoid any
 311  * flicker and not to mess up the current LCD DMA context. For this we disable
 312  * the LCD controler, which will generate a DONE irq after the last frame has
 313  * been transferred. Then it'll be safe to reconfigure both the LCD controller
 314  * as well as the LCD DMA.
 315  */
 316 static int omap_lcdc_setup_plane(int plane, int channel_out,
 317                                  unsigned long offset, int screen_width,
 318                                  int pos_x, int pos_y, int width, int height,
 319                                  int color_mode)
 320 {
 321         struct fb_var_screeninfo *var = &lcdc.fbdev->fb_info[0]->var;
 322         struct lcd_panel *panel = lcdc.fbdev->panel;
 323         int rot_x, rot_y;
 324
 325         if (var->rotate == 0) {
 326                 rot_x = panel->x_res;
 327                 rot_y = panel->y_res;
 328         } else {
 329                 rot_x = panel->y_res;
 330                 rot_y = panel->x_res;
 331         }
 332         if (plane != 0 || channel_out != 0 || pos_x != 0 || pos_y != 0 ||
 333             width > rot_x || height > rot_y) {
 334 #ifdef VERBOSE
 335                 dev_dbg(lcdc.fbdev->dev,
 336                         "invalid plane params plane %d pos_x %d pos_y %d "
 337                         "w %d h %d\n", plane, pos_x, pos_y, width, height);
 338 #endif
 339                 return -EINVAL;
 340         }
 341
 342         lcdc.frame_offset = offset;
 343         lcdc.xres = width;
 344         lcdc.yres = height;
 345         lcdc.screen_width = screen_width;
 346         lcdc.color_mode = color_mode;
 347
 348         switch (color_mode) {
 349         case OMAPFB_COLOR_CLUT_8BPP:
 350                 lcdc.bpp = 8;
 351                 lcdc.palette_code = 0x3000;
 352                 lcdc.palette_size = 512;
 353                 break;
 354         case OMAPFB_COLOR_RGB565:
 355                 lcdc.bpp = 16;
 356                 lcdc.palette_code = 0x4000;
 357                 lcdc.palette_size = 32;
 358                 break;
 359         case OMAPFB_COLOR_RGB444:
 360                 lcdc.bpp = 16;
 361                 lcdc.palette_code = 0x4000;
 362                 lcdc.palette_size = 32;
 363                 break;
 364         case OMAPFB_COLOR_YUV420:
 365                 if (lcdc.ext_mode) {
 366                         lcdc.bpp = 12;
 367                         break;
 368                 }
 369                 /* fallthrough */
 370         case OMAPFB_COLOR_YUV422:
 371                 if (lcdc.ext_mode) {
 372                         lcdc.bpp = 16;
 373                         break;
 374                 }
 375                 /* fallthrough */
 376         default:
 377                 /* FIXME: other BPPs.
 378                  * bpp1: code  0,     size 256
 379                  * bpp2: code  0x1000 size 256
 380                  * bpp4: code  0x2000 size 256
 381                  * bpp12: code 0x4000 size 32
 382                  */
 383                 dev_dbg(lcdc.fbdev->dev, "invalid color mode %d\n", color_mode);
 384                 BUG();
 385                 return -1;
 386         }
 387
 388         if (lcdc.ext_mode) {
 389                 setup_lcd_dma();
 390                 return 0;
 391         }
 392
 393         if (lcdc.update_mode == OMAPFB_AUTO_UPDATE) {
 394                 disable_controller();
 395                 omap_stop_lcd_dma();
 396                 setup_lcd_dma();
 397                 enable_controller();
 398         }
 399
 400         return 0;
 401 }
 402
 403 static int omap_lcdc_enable_plane(int plane, int enable)
 404 {
 405         dev_dbg(lcdc.fbdev->dev,
 406                 "plane %d enable %d update_mode %d ext_mode %d\n",
 407                 plane, enable, lcdc.update_mode, lcdc.ext_mode);
 408         if (plane != OMAPFB_PLANE_GFX)
 409                 return -EINVAL;
 410
 411         return 0;
 412 }
 413
 414 /* Configure the LCD DMA for a palette load operation and do the palette
 415  * downloading synchronously. We don't use the frame+palette load mode of
 416  * the controller, since the palette can always be downloaded seperately.
 417  */
 418 static void load_palette(void)
 419 {
 420         u16     *palette;
 421
 422         palette = (u16 *)lcdc.palette_virt;
 423
 424         *(u16 *)palette &= 0x0fff;
 425         *(u16 *)palette |= lcdc.palette_code;
 426
 427         omap_set_lcd_dma_b1(lcdc.palette_phys,
 428                 lcdc.palette_size / 4 + 1, 1, OMAP_DMA_DATA_TYPE_S32);
 429
 430         omap_set_lcd_dma_single_transfer(1);
 431         omap_setup_lcd_dma();
 432
 433         init_completion(&lcdc.palette_load_complete);
 434         enable_irqs(OMAP_LCDC_IRQ_LOADED_PALETTE);
 435         set_load_mode(OMAP_LCDC_LOAD_PALETTE);
 436         enable_controller();
 437         if (!wait_for_completion_timeout(&lcdc.palette_load_complete,
 438                                 msecs_to_jiffies(500)))
 439                 dev_err(lcdc.fbdev->dev, "timeout waiting for FRAME DONE\n");
 440         /* The controller gets disabled in the irq handler */
 441         disable_irqs(OMAP_LCDC_IRQ_LOADED_PALETTE);
 442         omap_stop_lcd_dma();
 443
 444         omap_set_lcd_dma_single_transfer(lcdc.ext_mode);
 445 }
 446
 447 /* Used only in internal controller mode */
 448 static int omap_lcdc_setcolreg(u_int regno, u16 red, u16 green, u16 blue,
 449                                u16 transp, int update_hw_pal)
 450 {
 451         u16 *palette;
 452
 453         if (lcdc.color_mode != OMAPFB_COLOR_CLUT_8BPP || regno > 255)
 454                 return -EINVAL;
 455
 456         palette = (u16 *)lcdc.palette_virt;
 457
 458         palette[regno] &= ~0x0fff;
 459         palette[regno] |= ((red >> 12) << 8) | ((green >> 12) << 4 ) |
 460                            (blue >> 12);
 461
 462         if (update_hw_pal) {
 463                 disable_controller();
 464                 omap_stop_lcd_dma();
 465                 load_palette();
 466                 setup_lcd_dma();
 467                 set_load_mode(OMAP_LCDC_LOAD_FRAME);
 468                 enable_controller();
 469         }
 470
 471         return 0;
 472 }
 473
 474 static void calc_ck_div(int is_tft, int pck, int *pck_div)
 475 {
 476         unsigned long lck;
 477
 478         pck = max(1, pck);
 479         lck = clk_get_rate(lcdc.lcd_ck);
 480         *pck_div = (lck + pck - 1) / pck;
 481         if (is_tft)
 482                 *pck_div = max(2, *pck_div);
 483         else
 484                 *pck_div = max(3, *pck_div);
 485         if (*pck_div > 255) {
 486                 /* FIXME: try to adjust logic clock divider as well */
 487                 *pck_div = 255;
 488                 dev_warn(lcdc.fbdev->dev, "pixclock %d kHz too low.\n",
 489                          pck / 1000);
 490         }
 491 }
 492
 493 static void inline setup_regs(void)
 494 {
 495         u32 l;
 496         struct lcd_panel *panel = lcdc.fbdev->panel;
 497         int is_tft = panel->config & OMAP_LCDC_PANEL_TFT;
 498         unsigned long lck;
 499         int pcd;
 500
 501         l = omap_readl(OMAP_LCDC_CONTROL);
 502         l &= ~OMAP_LCDC_CTRL_LCD_TFT;
 503         l |= is_tft ? OMAP_LCDC_CTRL_LCD_TFT : 0;
 504 #ifdef CONFIG_MACH_OMAP_PALMTE
 505 /* FIXME:if (machine_is_omap_palmte()) { */
 506                 /* PalmTE uses alternate TFT setting in 8BPP mode */
 507                 l |= (is_tft && panel->bpp == 8) ? 0x810000 : 0;
 508 /*      } */
 509 #endif
 510         omap_writel(l, OMAP_LCDC_CONTROL);
 511
 512         l = omap_readl(OMAP_LCDC_TIMING2);
 513         l &= ~(((1 << 6) - 1) << 20);
 514         l |= (panel->config & OMAP_LCDC_SIGNAL_MASK) << 20;
 515         omap_writel(l, OMAP_LCDC_TIMING2);
 516
 517         l = panel->x_res - 1;
 518         l |= (panel->hsw - 1) << 10;
 519         l |= (panel->hfp - 1) << 16;
 520         l |= (panel->hbp - 1) << 24;
 521         omap_writel(l, OMAP_LCDC_TIMING0);
 522
 523         l = panel->y_res - 1;
 524         l |= (panel->vsw - 1) << 10;
 525         l |= panel->vfp << 16;
 526         l |= panel->vbp << 24;
 527         omap_writel(l, OMAP_LCDC_TIMING1);
 528
 529         l = omap_readl(OMAP_LCDC_TIMING2);
 530         l &= ~0xff;
 531
 532         lck = clk_get_rate(lcdc.lcd_ck);
 533
 534         if (!panel->pcd)
 535                 calc_ck_div(is_tft, panel->pixel_clock * 1000, &pcd);
 536         else {
 537                 dev_warn(lcdc.fbdev->dev,
 538                     "Pixel clock divider value is obsolete.\n"
 539                     "Try to set pixel_clock to %lu and pcd to 0 "
 540                     "in drivers/video/omap/lcd_%s.c and submit a patch.\n",
 541                         lck / panel->pcd / 1000, panel->name);
 542
 543                 pcd = panel->pcd;
 544         }
 545         l |= pcd & 0xff;
 546         l |= panel->acb << 8;
 547         omap_writel(l, OMAP_LCDC_TIMING2);
 548
 549         /* update panel info with the exact clock */
 550         panel->pixel_clock = lck / pcd / 1000;
 551 }
 552
 553 /* Configure the LCD controller, download the color palette and start a looped
 554  * DMA transfer of the frame image data. Called only in internal
 555  * controller mode.
 556  */
 557 static int omap_lcdc_set_update_mode(enum omapfb_update_mode mode)
 558 {
 559         int r = 0;
 560
 561         if (mode != lcdc.update_mode) {
 562                 switch (mode) {
 563                 case OMAPFB_AUTO_UPDATE:
 564                         setup_regs();
 565                         load_palette();
 566
 567                         /* Setup and start LCD DMA */
 568                         setup_lcd_dma();
 569
 570                         set_load_mode(OMAP_LCDC_LOAD_FRAME);
 571                         enable_irqs(OMAP_LCDC_IRQ_DONE);
 572                         /* This will start the actual DMA transfer */
 573                         enable_controller();
 574                         lcdc.update_mode = mode;
 575                         break;
 576                 case OMAPFB_UPDATE_DISABLED:
 577                         disable_controller();
 578                         omap_stop_lcd_dma();
 579                         lcdc.update_mode = mode;
 580                         break;
 581                 default:
 582                         r = -EINVAL;
 583                 }
 584         }
 585
 586         return r;
 587 }
 588
 589 static enum omapfb_update_mode omap_lcdc_get_update_mode(void)
 590 {
 591         return lcdc.update_mode;
 592 }
 593
 594 /* PM code called only in internal controller mode */
 595 static void omap_lcdc_suspend(void)
 596 {
 597         if (lcdc.update_mode == OMAPFB_AUTO_UPDATE) {
 598                 disable_controller();
 599                 omap_stop_lcd_dma();
 600         }
 601 }
 602
 603 static void omap_lcdc_resume(void)
 604 {
 605         if (lcdc.update_mode == OMAPFB_AUTO_UPDATE) {
 606                 setup_regs();
 607                 load_palette();
 608                 setup_lcd_dma();
 609                 set_load_mode(OMAP_LCDC_LOAD_FRAME);
 610                 enable_irqs(OMAP_LCDC_IRQ_DONE);
 611                 enable_controller();
 612         }
 613 }
 614
 615 static unsigned long omap_lcdc_get_caps(void)
 616 {
 617         return 0;
 618 }
 619
 620 int omap_lcdc_set_dma_callback(void (*callback)(void *data), void *data)
 621 {
 622         BUG_ON(callback == NULL);
 623
 624         if (lcdc.dma_callback)
 625                 return -EBUSY;
 626         else {
 627                 lcdc.dma_callback = callback;
 628                 lcdc.dma_callback_data = data;
 629         }
 630         return 0;
 631 }
 632 EXPORT_SYMBOL(omap_lcdc_set_dma_callback);
 633
 634 void omap_lcdc_free_dma_callback(void)
 635 {
 636         lcdc.dma_callback = NULL;
 637 }
 638 EXPORT_SYMBOL(omap_lcdc_free_dma_callback);
 639
 640 static void lcdc_dma_handler(u16 status, void *data)
 641 {
 642         if (lcdc.dma_callback)
 643                 lcdc.dma_callback(lcdc.dma_callback_data);
 644 }
 645
 646 static int mmap_kern(void)
 647 {
 648         struct vm_struct        *kvma;
 649         struct vm_area_struct   vma;
 650         pgprot_t                pgprot;
 651         unsigned long           vaddr;
 652
 653         kvma = get_vm_area(lcdc.vram_size, VM_IOREMAP);
 654         if (kvma == NULL) {
 655                 dev_err(lcdc.fbdev->dev, "can't get kernel vm area\n");
 656                 return -ENOMEM;
 657         }
 658         vma.vm_mm = &init_mm;
 659
 660         vaddr = (unsigned long)kvma->addr;
 661         vma.vm_start = vaddr;
 662         vma.vm_end = vaddr + lcdc.vram_size;
 663
 664         pgprot = pgprot_writecombine(pgprot_kernel);
 665         if (io_remap_pfn_range(&vma, vaddr,
 666                            lcdc.vram_phys >> PAGE_SHIFT,
 667                            lcdc.vram_size, pgprot) < 0) {
 668                 dev_err(lcdc.fbdev->dev, "kernel mmap for FB memory failed\n");
 669                 return -EAGAIN;
 670         }
 671
 672         lcdc.vram_virt = (void *)vaddr;
 673
 674         return 0;
 675 }
 676
 677 static void unmap_kern(void)
 678 {
 679         vunmap(lcdc.vram_virt);
 680 }
 681
 682 static int alloc_palette_ram(void)
 683 {
 684         lcdc.palette_virt = dma_alloc_writecombine(lcdc.fbdev->dev,
 685                 MAX_PALETTE_SIZE, &lcdc.palette_phys, GFP_KERNEL);
 686         if (lcdc.palette_virt == NULL) {
 687                 dev_err(lcdc.fbdev->dev, "failed to alloc palette memory\n");
 688                 return -ENOMEM;
 689         }
 690         memset(lcdc.palette_virt, 0, MAX_PALETTE_SIZE);
 691
 692         return 0;
 693 }
 694
 695 static void free_palette_ram(void)
 696 {
 697         dma_free_writecombine(lcdc.fbdev->dev, MAX_PALETTE_SIZE,
 698                         lcdc.palette_virt, lcdc.palette_phys);
 699 }
 700
 701 static int alloc_fbmem(struct omapfb_mem_region *region)
 702 {
 703         int bpp;
 704         int frame_size;
 705         struct lcd_panel *panel = lcdc.fbdev->panel;
 706
 707         bpp = panel->bpp;
 708         if (bpp == 12)
 709                 bpp = 16;
 710         frame_size = PAGE_ALIGN(panel->x_res * bpp / 8 * panel->y_res);
 711         if (region->size > frame_size)
 712                 frame_size = region->size;
 713         lcdc.vram_size = frame_size;
 714         lcdc.vram_virt = dma_alloc_writecombine(lcdc.fbdev->dev,
 715                         lcdc.vram_size, &lcdc.vram_phys, GFP_KERNEL);
 716         if (lcdc.vram_virt == NULL) {
 717                 dev_err(lcdc.fbdev->dev, "unable to allocate FB DMA memory\n");
 718                 return -ENOMEM;
 719         }
 720         region->size = frame_size;
 721         region->paddr = lcdc.vram_phys;
 722         region->alloc = 1;
 723
 724         memset(lcdc.vram_virt, 0, lcdc.vram_size);
 725
 726         return 0;
 727 }
 728
 729 static void free_fbmem(void)
 730 {
 731         dma_free_writecombine(lcdc.fbdev->dev, lcdc.vram_size,
 732                               lcdc.vram_virt, lcdc.vram_phys);
 733 }
 734
 735 static int setup_fbmem(struct omapfb_mem_desc *req_md)
 736 {
 737         int r;
 738
 739         if (!req_md->region_cnt) {
 740                 dev_err(lcdc.fbdev->dev, "no memory regions defined\n");
 741                 return -EINVAL;
 742         }
 743
 744         if (req_md->region_cnt > 1) {
 745                 dev_err(lcdc.fbdev->dev, "only one plane is supported\n");
 746                 req_md->region_cnt = 1;
 747         }
 748
 749         if (req_md->region[0].paddr == 0) {
 750                 lcdc.fbmem_allocated = 1;
 751                 if ((r = alloc_fbmem(&req_md->region[0])) < 0)
 752                         return r;
 753                 return 0;
 754         }
 755
 756         lcdc.vram_phys = req_md->region[0].paddr;
 757         lcdc.vram_size = req_md->region[0].size;
 758
 759         if ((r = mmap_kern()) < 0)
 760                 return r;
 761
 762         dev_dbg(lcdc.fbdev->dev, "vram at %08x size %08lx mapped to 0x%p\n",
 763                  lcdc.vram_phys, lcdc.vram_size, lcdc.vram_virt);
 764
 765         return 0;
 766 }
 767
 768 static void cleanup_fbmem(void)
 769 {
 770         if (lcdc.fbmem_allocated)
 771                 free_fbmem();
 772         else
 773                 unmap_kern();
 774 }
 775
 776 static int omap_lcdc_init(struct omapfb_device *fbdev, int ext_mode,
 777                           struct omapfb_mem_desc *req_vram)
 778 {
 779         int r;
 780         u32 l;
 781         int rate;
 782         struct clk *tc_ck;
 783
 784         lcdc.irq_mask = 0;
 785
 786         lcdc.fbdev = fbdev;
 787         lcdc.ext_mode = ext_mode;
 788
 789         l = 0;
 790         omap_writel(l, OMAP_LCDC_CONTROL);
 791
 792         /* FIXME:
 793          * According to errata some platforms have a clock rate limitiation
 794          */
 795         lcdc.lcd_ck = clk_get(NULL, "lcd_ck");
 796         if (IS_ERR(lcdc.lcd_ck)) {
 797                 dev_err(fbdev->dev, "unable to access LCD clock\n");
 798                 r = PTR_ERR(lcdc.lcd_ck);
 799                 goto fail0;
 800         }
 801
 802         tc_ck = clk_get(NULL, "tc_ck");
 803         if (IS_ERR(tc_ck)) {
 804                 dev_err(fbdev->dev, "unable to access TC clock\n");
 805                 r = PTR_ERR(tc_ck);
 806                 goto fail1;
 807         }
 808
 809         rate = clk_get_rate(tc_ck);
 810         clk_put(tc_ck);
 811
 812         if (machine_is_omap_h3())
 813                 rate /= 3;
 814         r = clk_set_rate(lcdc.lcd_ck, rate);
 815         if (r) {
 816                 dev_err(fbdev->dev, "failed to adjust LCD rate\n");
 817                 goto fail1;
 818         }
 819         clk_enable(lcdc.lcd_ck);
 820
 821         r = request_irq(OMAP_LCDC_IRQ, lcdc_irq_handler, 0, MODULE_NAME, fbdev);
 822         if (r) {
 823                 dev_err(fbdev->dev, "unable to get IRQ\n");
 824                 goto fail2;
 825         }
 826
 827         r = omap_request_lcd_dma(lcdc_dma_handler, NULL);
 828         if (r) {
 829                 dev_err(fbdev->dev, "unable to get LCD DMA\n");
 830                 goto fail3;
 831         }
 832
 833         omap_set_lcd_dma_single_transfer(ext_mode);
 834         omap_set_lcd_dma_ext_controller(ext_mode);
 835
 836         if (!ext_mode)
 837                 if ((r = alloc_palette_ram()) < 0)
 838                         goto fail4;
 839
 840         if ((r = setup_fbmem(req_vram)) < 0)
 841                 goto fail5;
 842
 843         pr_info("omapfb: LCDC initialized\n");
 844
 845         return 0;
 846 fail5:
 847         if (!ext_mode)
 848                 free_palette_ram();
 849 fail4:
 850         omap_free_lcd_dma();
 851 fail3:
 852         free_irq(OMAP_LCDC_IRQ, lcdc.fbdev);
 853 fail2:
 854         clk_disable(lcdc.lcd_ck);
 855 fail1:
 856         clk_put(lcdc.lcd_ck);
 857 fail0:
 858         return r;
 859 }
 860
 861 static void omap_lcdc_cleanup(void)
 862 {
 863         if (!lcdc.ext_mode)
 864                 free_palette_ram();
 865         cleanup_fbmem();
 866         omap_free_lcd_dma();
 867         free_irq(OMAP_LCDC_IRQ, lcdc.fbdev);
 868         clk_disable(lcdc.lcd_ck);
 869         clk_put(lcdc.lcd_ck);
 870 }
 871
 872 const struct lcd_ctrl omap1_int_ctrl = {
 873         .name                   = "internal",
 874         .init                   = omap_lcdc_init,
 875         .cleanup                = omap_lcdc_cleanup,
 876         .get_caps               = omap_lcdc_get_caps,
 877         .set_update_mode        = omap_lcdc_set_update_mode,
 878         .get_update_mode        = omap_lcdc_get_update_mode,
 879         .update_window          = NULL,
 880         .suspend                = omap_lcdc_suspend,
 881         .resume                 = omap_lcdc_resume,
 882         .setup_plane            = omap_lcdc_setup_plane,
 883         .enable_plane           = omap_lcdc_enable_plane,
 884         .setcolreg              = omap_lcdc_setcolreg,
 885 };