2 * File: drivers/video/omap/omap1/lcdc.c
4 * OMAP1 internal LCD controller
6 * Copyright (C) 2004 Nokia Corporation
7 * Author: Imre Deak <imre.deak@nokia.com>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 #include <linux/config.h>
25 #include <linux/module.h>
26 #include <linux/device.h>
27 #include <linux/interrupt.h>
28 #include <linux/spinlock.h>
29 #include <linux/err.h>
32 #include <linux/dma-mapping.h>
34 #include <asm/arch/dma.h>
35 #include <asm/arch/omapfb.h>
37 #include <asm/mach-types.h>
38 #include <asm/hardware/clock.h>
40 /* #define OMAPFB_DBG 2 */
44 #define MODULE_NAME "omapfb-lcdc"
46 #define OMAP_LCDC_BASE 0xfffec000
47 #define OMAP_LCDC_SIZE 256
48 #define OMAP_LCDC_IRQ INT_LCD_CTRL
50 #define OMAP_LCDC_CONTROL (OMAP_LCDC_BASE + 0x00)
51 #define OMAP_LCDC_TIMING0 (OMAP_LCDC_BASE + 0x04)
52 #define OMAP_LCDC_TIMING1 (OMAP_LCDC_BASE + 0x08)
53 #define OMAP_LCDC_TIMING2 (OMAP_LCDC_BASE + 0x0c)
54 #define OMAP_LCDC_STATUS (OMAP_LCDC_BASE + 0x10)
55 #define OMAP_LCDC_SUBPANEL (OMAP_LCDC_BASE + 0x14)
56 #define OMAP_LCDC_LINE_INT (OMAP_LCDC_BASE + 0x18)
57 #define OMAP_LCDC_DISPLAY_STATUS (OMAP_LCDC_BASE + 0x1c)
59 #define OMAP_LCDC_STAT_DONE (1 << 0)
60 #define OMAP_LCDC_STAT_VSYNC (1 << 1)
61 #define OMAP_LCDC_STAT_SYNC_LOST (1 << 2)
62 #define OMAP_LCDC_STAT_ABC (1 << 3)
63 #define OMAP_LCDC_STAT_LINE_INT (1 << 4)
64 #define OMAP_LCDC_STAT_FUF (1 << 5)
65 #define OMAP_LCDC_STAT_LOADED_PALETTE (1 << 6)
67 #define OMAP_LCDC_CTRL_LCD_EN (1 << 0)
68 #define OMAP_LCDC_CTRL_LCD_TFT (1 << 7)
69 #define OMAP_LCDC_CTRL_LINE_IRQ_CLR_SEL (1 << 10)
71 #define OMAP_LCDC_IRQ_VSYNC (1 << 2)
72 #define OMAP_LCDC_IRQ_DONE (1 << 3)
73 #define OMAP_LCDC_IRQ_LOADED_PALETTE (1 << 4)
74 #define OMAP_LCDC_IRQ_LINE_NIRQ (1 << 5)
75 #define OMAP_LCDC_IRQ_LINE (1 << 6)
76 #define OMAP_LCDC_IRQ_MASK (((1 << 5) - 1) << 2)
78 #define MAX_PALETTE_SIZE PAGE_SIZE
80 #define pr_err(fmt, args...) printk(KERN_ERR MODULE_NAME ": " fmt, ## args)
83 OMAP_LCDC_LOAD_PALETTE,
85 OMAP_LCDC_LOAD_PALETTE_AND_FRAME
88 static struct omap_lcd_controller {
89 enum omapfb_update_mode update_mode;
91 unsigned long frame_offset;
94 enum omapfb_color_format color_mode;
100 unsigned int irq_mask;
101 struct completion last_frame_complete;
102 struct completion palette_load_complete;
104 struct omapfb_device *fbdev;
106 dma_addr_t vram_phys;
108 unsigned long vram_size;
111 static void inline enable_irqs(int mask)
113 omap_lcdc.irq_mask |= mask;
116 static void inline disable_irqs(int mask)
118 omap_lcdc.irq_mask &= ~mask;
121 static void set_load_mode(enum lcdc_load_mode mode)
125 l = omap_readl(OMAP_LCDC_CONTROL);
128 case OMAP_LCDC_LOAD_PALETTE:
131 case OMAP_LCDC_LOAD_FRAME:
134 case OMAP_LCDC_LOAD_PALETTE_AND_FRAME:
139 omap_writel(l, OMAP_LCDC_CONTROL);
142 static void enable_controller(void)
146 l = omap_readl(OMAP_LCDC_CONTROL);
147 l |= OMAP_LCDC_CTRL_LCD_EN;
148 l &= ~OMAP_LCDC_IRQ_MASK;
149 l |= omap_lcdc.irq_mask | OMAP_LCDC_IRQ_DONE; /* enabled IRQs */
150 omap_writel(l, OMAP_LCDC_CONTROL);
153 static void disable_controller_async(void)
158 l = omap_readl(OMAP_LCDC_CONTROL);
159 mask = OMAP_LCDC_CTRL_LCD_EN | OMAP_LCDC_IRQ_MASK;
160 /* Preserve the DONE mask, since we still want to get the
161 * final DONE irq. It will be disabled in the IRQ handler.
163 mask &= ~OMAP_LCDC_IRQ_DONE;
165 omap_writel(l, OMAP_LCDC_CONTROL);
168 static void disable_controller(void)
170 init_completion(&omap_lcdc.last_frame_complete);
171 disable_controller_async();
172 if (!wait_for_completion_timeout(&omap_lcdc.last_frame_complete,
173 msecs_to_jiffies(500)))
174 pr_err("timeout waiting for FRAME DONE\n");
177 static void reset_controller(u32 status)
179 static unsigned long reset_count = 0;
180 static unsigned long last_jiffies = 0;
182 disable_controller_async();
184 if (reset_count == 1 || time_after(jiffies, last_jiffies + HZ)) {
185 pr_err("resetting (status %#010x,reset count %lu)\n",
186 status, reset_count);
187 last_jiffies = jiffies;
189 if (reset_count < 100) {
193 pr_err("too many reset attempts, giving up.\n");
197 /* Configure the LCD DMA according to the current mode specified by parameters
198 * in omap_lcdc.fbdev and fbdev->var.
200 static void setup_lcd_dma(void)
202 static const int dma_elem_type[] = {
204 OMAP_DMA_DATA_TYPE_S8,
205 OMAP_DMA_DATA_TYPE_S16,
207 OMAP_DMA_DATA_TYPE_S32,
209 struct fb_var_screeninfo *var = &omap_lcdc.fbdev->fb_info->var;
210 struct lcd_panel *panel = omap_lcdc.fbdev->panel;
212 int esize, xelem, yelem;
214 src = omap_lcdc.vram_phys + PAGE_ALIGN(MAX_PALETTE_SIZE) +
215 omap_lcdc.frame_offset;
217 switch (var->rotate) {
219 esize = omap_lcdc.fbdev->mirror || (src & 3) ? 2 : 4;
220 xelem = panel->x_res * omap_lcdc.bpp / 8 / esize;
221 yelem = panel->y_res;
226 if (cpu_is_omap15xx()) {
230 xelem = panel->y_res * omap_lcdc.bpp / 16;
231 yelem = panel->x_res;
237 DBGPRINT(1, "setup_dma: src %#010lx esize %d xelem %d yelem %d\n",
238 src, esize, xelem, yelem);
239 omap_set_lcd_dma_b1(src, xelem, yelem, dma_elem_type[esize]);
240 omap_set_lcd_dma_single_transfer(0);
241 if (!cpu_is_omap15xx()) {
242 /* Set virtual xres elem size */
243 omap_set_lcd_dma_b1_vxres(
244 omap_lcdc.screen_width * omap_lcdc.bpp / 8 / esize);
245 /* Setup transformations */
246 omap_set_lcd_dma_b1_rotation(var->rotate);
247 omap_set_lcd_dma_b1_mirror(omap_lcdc.fbdev->mirror);
249 omap_setup_lcd_dma();
252 static irqreturn_t lcdc_irq_handler(int irq, void *dev_id, struct pt_regs *fp)
256 status = omap_readl(OMAP_LCDC_STATUS);
258 if (status & (OMAP_LCDC_STAT_FUF | OMAP_LCDC_STAT_SYNC_LOST))
259 reset_controller(status);
261 if (status & OMAP_LCDC_STAT_DONE) {
264 /* Disable IRQ_DONE. The status bit will be cleared
265 * only when the controller is reenabled and we don't
266 * want to get more interrupts.
268 l = omap_readl(OMAP_LCDC_CONTROL);
269 l &= ~OMAP_LCDC_IRQ_DONE;
270 omap_writel(l, OMAP_LCDC_CONTROL);
271 complete(&omap_lcdc.last_frame_complete);
273 if (status & OMAP_LCDC_STAT_LOADED_PALETTE) {
274 disable_controller_async();
275 complete(&omap_lcdc.palette_load_complete);
279 /* Clear these interrupt status bits.
280 * Sync_lost, FUF bits were cleared by disabling the LCD controller
281 * LOADED_PALETTE can be cleared this way only in palette only
282 * load mode. In other load modes it's cleared by disabling the
285 status &= ~(OMAP_LCDC_STAT_VSYNC |
286 OMAP_LCDC_STAT_LOADED_PALETTE |
288 OMAP_LCDC_STAT_LINE_INT);
289 omap_writel(status, OMAP_LCDC_STATUS);
293 /* Change to a new video mode. We defer this to a later time to avoid any
294 * flicker and not to mess up the current LCD DMA context. For this we disable
295 * the LCD controler, which will generate a DONE irq after the last frame has
296 * been transferred. Then it'll be safe to reconfigure both the LCD controller
297 * as well as the LCD DMA.
299 static int omap_lcdc_setup_plane(int plane, int channel_out,
300 unsigned long offset, int screen_width,
301 int pos_x, int pos_y, int width, int height,
304 struct fb_var_screeninfo *var = &omap_lcdc.fbdev->fb_info->var;
305 struct lcd_panel *panel = omap_lcdc.fbdev->panel;
310 if (var->rotate == 0) {
311 rot_x = panel->x_res;
312 rot_y = panel->y_res;
314 rot_x = panel->y_res;
315 rot_y = panel->x_res;
317 if (plane != 0 || channel_out != 0 || pos_x != 0 || pos_y != 0 ||
318 width != rot_x || height != rot_y) {
319 DBGPRINT(1, "invalid plane params plane %d pos_x %d "
320 "pos_y %d w %d h %d\n", plane, pos_x, pos_y,
325 omap_lcdc.frame_offset = offset;
326 omap_lcdc.screen_width = screen_width;
327 omap_lcdc.color_mode = color_mode;
329 switch (color_mode) {
330 case OMAPFB_COLOR_CLUT_8BPP:
332 omap_lcdc.palette_code = 0x3000;
333 omap_lcdc.palette_size = 512;
335 case OMAPFB_COLOR_RGB565:
337 omap_lcdc.palette_code = 0x4000;
338 omap_lcdc.palette_size = 32;
341 /* FIXME: other BPPs.
342 * bpp1: code 0, size 256
343 * bpp2: code 0x1000 size 256
344 * bpp4: code 0x2000 size 256
345 * bpp12: code 0x4000 size 32
347 DBGPRINT(1, "invalid color mode %d\n", color_mode);
351 omap_lcdc.palette_org = PAGE_ALIGN(MAX_PALETTE_SIZE) -
352 omap_lcdc.palette_size;
354 if (omap_lcdc.update_mode == OMAPFB_AUTO_UPDATE) {
355 disable_controller();
366 static int omap_lcdc_enable_plane(int plane, int enable)
368 if (plane != 0 || enable != 1)
374 /* Configure the LCD DMA for a palette load operation and do the palette
375 * downloading synchronously. We don't use the frame+palette load mode of
376 * the controller, since the palette can always be downloaded seperately.
378 static void load_palette(void)
384 palette = (u16 *)((u8 *)omap_lcdc.vram_virt + omap_lcdc.palette_org);
386 *(u16 *)palette &= 0x0fff;
387 *(u16 *)palette |= omap_lcdc.palette_code;
389 omap_set_lcd_dma_b1(omap_lcdc.vram_phys + omap_lcdc.palette_org,
390 omap_lcdc.palette_size / 4 + 1, 1, OMAP_DMA_DATA_TYPE_S32);
392 omap_set_lcd_dma_single_transfer(1);
393 omap_setup_lcd_dma();
395 init_completion(&omap_lcdc.palette_load_complete);
396 enable_irqs(OMAP_LCDC_IRQ_LOADED_PALETTE);
397 set_load_mode(OMAP_LCDC_LOAD_PALETTE);
399 if (!wait_for_completion_timeout(&omap_lcdc.palette_load_complete,
400 msecs_to_jiffies(500)))
401 pr_err("timeout waiting for FRAME DONE\n");
402 /* The controller gets disabled in the irq handler */
403 disable_irqs(OMAP_LCDC_IRQ_LOADED_PALETTE);
409 static void calc_ck_div(int is_tft, int pck, int *pck_div)
414 lck = clk_get_rate(omap_lcdc.lcd_ck);
415 *pck_div = lck / pck;
417 *pck_div = max(2, *pck_div);
419 *pck_div = max(3, *pck_div);
420 if (*pck_div > 255) {
421 /* FIXME: try to adjust logic clock divider as well */
423 printk(KERN_WARNING MODULE_NAME ": pixclock %d kHz too low.\n",
428 static void inline setup_regs(void)
431 struct lcd_panel *panel = omap_lcdc.fbdev->panel;
432 int is_tft = panel->config & OMAP_LCDC_PANEL_TFT;
436 l = omap_readl(OMAP_LCDC_CONTROL);
437 l &= ~OMAP_LCDC_CTRL_LCD_TFT;
438 l |= is_tft ? OMAP_LCDC_CTRL_LCD_TFT : 0;
439 #ifdef CONFIG_MACH_OMAP_PALMTE
440 /* FIXME:if (machine_is_omap_palmte()) { */
441 /* PalmTE uses alternate TFT setting in 8BPP mode */
442 l |= (is_tft && panel->bpp == 8) ? 0x810000 : 0;
445 omap_writel(l, OMAP_LCDC_CONTROL);
447 l = omap_readl(OMAP_LCDC_TIMING2);
448 l &= ~(((1 << 6) - 1) << 20);
449 l |= (panel->config & OMAP_LCDC_SIGNAL_MASK) << 20;
450 omap_writel(l, OMAP_LCDC_TIMING2);
452 l = panel->x_res - 1;
453 l |= (panel->hsw - 1) << 10;
454 l |= (panel->hfp - 1) << 16;
455 l |= (panel->hbp - 1) << 24;
456 omap_writel(l, OMAP_LCDC_TIMING0);
458 l = panel->y_res - 1;
459 l |= (panel->vsw - 1) << 10;
460 l |= panel->vfp << 16;
461 l |= panel->vbp << 24;
462 omap_writel(l, OMAP_LCDC_TIMING1);
464 l = omap_readl(OMAP_LCDC_TIMING2);
467 lck = clk_get_rate(omap_lcdc.lcd_ck);
470 calc_ck_div(is_tft, panel->pixel_clock * 1000, &pcd);
473 MODULE_NAME ": Pixel clock divider value is obsolete.\n"
474 MODULE_NAME ": Try to set pixel_clock to %lu and pcd to 0 "
475 "in drivers/video/omap/lcd_%s.c and submit a patch.\n",
476 lck / panel->pcd / 1000, panel->name);
481 l |= panel->acb << 8;
482 omap_writel(l, OMAP_LCDC_TIMING2);
484 /* update panel info with the exact clock */
485 panel->pixel_clock = lck / pcd / 1000;
488 /* Configure the LCD controller, download the color palette and start a looped
489 * DMA transfer of the frame image data. */
490 static int omap_lcdc_set_update_mode(enum omapfb_update_mode mode)
496 if (mode != omap_lcdc.update_mode) {
498 case OMAPFB_AUTO_UPDATE:
502 /* Setup and start LCD DMA */
505 set_load_mode(OMAP_LCDC_LOAD_FRAME);
506 enable_irqs(OMAP_LCDC_IRQ_DONE);
507 /* This will start the actual DMA transfer */
509 omap_lcdc.update_mode = mode;
511 case OMAPFB_UPDATE_DISABLED:
512 disable_controller();
514 omap_lcdc.update_mode = mode;
525 static enum omapfb_update_mode omap_lcdc_get_update_mode(void)
527 return omap_lcdc.update_mode;
530 static void omap_lcdc_suspend(void)
532 if (omap_lcdc.update_mode == OMAPFB_AUTO_UPDATE) {
533 disable_controller();
538 static void omap_lcdc_resume(void)
540 if (omap_lcdc.update_mode == OMAPFB_AUTO_UPDATE) {
544 set_load_mode(OMAP_LCDC_LOAD_FRAME);
545 enable_irqs(OMAP_LCDC_IRQ_DONE);
550 static void omap_lcdc_get_vram_layout(unsigned long *size, void **virt,
553 *size = omap_lcdc.vram_size - PAGE_ALIGN(MAX_PALETTE_SIZE);
554 *virt = (u8 *)omap_lcdc.vram_virt + PAGE_ALIGN(MAX_PALETTE_SIZE);
555 *phys = omap_lcdc.vram_phys + PAGE_ALIGN(MAX_PALETTE_SIZE);
558 static int omap_lcdc_init(struct omapfb_device *fbdev, int ext_mode,
565 struct lcd_panel *panel = fbdev->panel;
570 omap_lcdc.irq_mask = 0;
572 omap_lcdc.fbdev = fbdev;
574 pr_info(MODULE_NAME ": init\n");
577 omap_writel(l, OMAP_LCDC_CONTROL);
580 * According to errata some platforms have a clock rate limitiation
582 omap_lcdc.lcd_ck = clk_get(NULL, "lcd_ck");
583 if (IS_ERR(omap_lcdc.lcd_ck)) {
584 pr_err("unable to access LCD clock\n");
585 r = PTR_ERR(omap_lcdc.lcd_ck);
589 tc_ck = clk_get(NULL, "tc_ck");
591 pr_err("unable to access TC clock\n");
596 rate = clk_get_rate(tc_ck);
599 if (machine_is_omap_h3())
601 r = clk_set_rate(omap_lcdc.lcd_ck, rate);
603 pr_err("failed to adjust LCD rate\n");
606 clk_use(omap_lcdc.lcd_ck);
608 r = request_irq(OMAP_LCDC_IRQ, lcdc_irq_handler, 0, "omap-lcdc",
611 pr_err("unable to get IRQ\n");
615 r = omap_request_lcd_dma(NULL, NULL);
617 pr_err("unable to get LCD DMA\n");
621 frame_size = panel->x_res * panel->bpp * panel->y_res / 8;
622 if (req_vram_size > frame_size)
623 frame_size = req_vram_size;
624 omap_lcdc.vram_size = PAGE_ALIGN(MAX_PALETTE_SIZE) + frame_size;
625 omap_lcdc.vram_virt = dma_alloc_writecombine(fbdev->dev,
626 omap_lcdc.vram_size, &omap_lcdc.vram_phys, GFP_KERNEL);
628 if (omap_lcdc.vram_virt == NULL) {
629 pr_err("unable to allocate fb DMA memory\n");
639 free_irq(OMAP_LCDC_IRQ, omap_lcdc.fbdev);
641 clk_unuse(omap_lcdc.lcd_ck);
643 clk_put(omap_lcdc.lcd_ck);
649 static void omap_lcdc_cleanup(void)
651 dma_free_writecombine(omap_lcdc.fbdev->dev, omap_lcdc.vram_size,
652 omap_lcdc.vram_virt, omap_lcdc.vram_phys);
654 free_irq(OMAP_LCDC_IRQ, omap_lcdc.fbdev);
655 clk_unuse(omap_lcdc.lcd_ck);
656 clk_put(omap_lcdc.lcd_ck);
659 static unsigned long omap_lcdc_get_caps(void)
664 static int omap_lcdc_setcolreg(u_int regno, u16 red, u16 green, u16 blue,
665 u16 transp, int update_hw_pal)
669 if (omap_lcdc.color_mode != OMAPFB_COLOR_CLUT_8BPP || regno > 255)
672 palette = (u16 *)((u8*)omap_lcdc.vram_virt +
673 PAGE_ALIGN(MAX_PALETTE_SIZE) - omap_lcdc.palette_size);
675 palette[regno] &= ~0x0fff;
676 palette[regno] |= ((red >> 12) << 8) | ((green >> 12) << 4 ) |
680 disable_controller();
684 set_load_mode(OMAP_LCDC_LOAD_FRAME);
691 struct lcd_ctrl omap1_int_ctrl = {
693 .init = omap_lcdc_init,
694 .cleanup = omap_lcdc_cleanup,
695 .get_vram_layout = omap_lcdc_get_vram_layout,
696 .get_caps = omap_lcdc_get_caps,
697 .set_update_mode = omap_lcdc_set_update_mode,
698 .get_update_mode = omap_lcdc_get_update_mode,
699 .update_window = NULL,
700 .suspend = omap_lcdc_suspend,
701 .resume = omap_lcdc_resume,
702 .setup_plane = omap_lcdc_setup_plane,
703 .enable_plane = omap_lcdc_enable_plane,
704 .setcolreg = omap_lcdc_setcolreg,
707 MODULE_DESCRIPTION("TI OMAP LCDC controller");
708 MODULE_LICENSE("GPL");