drivers/video/omap/lcdc.c

   1 /*
   2  * File: drivers/video/omap/omap1/lcdc.c
   3  *
   4  * OMAP1 internal LCD controller
   5  *
   6  * Copyright (C) 2004 Nokia Corporation
   7  * Author: Imre Deak <imre.deak@nokia.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of the GNU General Public License as published by the
  11  * Free Software Foundation; either version 2 of the License, or (at your
  12  * option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along
  20  * with this program; if not, write to the Free Software Foundation, Inc.,
  21  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  22  */
  23 #include <linux/module.h>
  24 #include <linux/device.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/err.h>
  28 #include <linux/mm.h>
  29 #include <linux/fb.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/vmalloc.h>
  32 #include <linux/clk.h>
  33
  34 #include <asm/arch/dma.h>
  35 #include <asm/arch/omapfb.h>
  36
  37 #include <asm/mach-types.h>
  38
  39 #define MODULE_NAME                     "lcdc"
  40
  41 #define OMAP_LCDC_BASE                  0xfffec000
  42 #define OMAP_LCDC_SIZE                  256
  43 #define OMAP_LCDC_IRQ                   INT_LCD_CTRL
  44
  45 #define OMAP_LCDC_CONTROL               (OMAP_LCDC_BASE + 0x00)
  46 #define OMAP_LCDC_TIMING0               (OMAP_LCDC_BASE + 0x04)
  47 #define OMAP_LCDC_TIMING1               (OMAP_LCDC_BASE + 0x08)
  48 #define OMAP_LCDC_TIMING2               (OMAP_LCDC_BASE + 0x0c)
  49 #define OMAP_LCDC_STATUS                (OMAP_LCDC_BASE + 0x10)
  50 #define OMAP_LCDC_SUBPANEL              (OMAP_LCDC_BASE + 0x14)
  51 #define OMAP_LCDC_LINE_INT              (OMAP_LCDC_BASE + 0x18)
  52 #define OMAP_LCDC_DISPLAY_STATUS        (OMAP_LCDC_BASE + 0x1c)
  53
  54 #define OMAP_LCDC_STAT_DONE             (1 << 0)
  55 #define OMAP_LCDC_STAT_VSYNC            (1 << 1)
  56 #define OMAP_LCDC_STAT_SYNC_LOST        (1 << 2)
  57 #define OMAP_LCDC_STAT_ABC              (1 << 3)
  58 #define OMAP_LCDC_STAT_LINE_INT         (1 << 4)
  59 #define OMAP_LCDC_STAT_FUF              (1 << 5)
  60 #define OMAP_LCDC_STAT_LOADED_PALETTE   (1 << 6)
  61
  62 #define OMAP_LCDC_CTRL_LCD_EN           (1 << 0)
  63 #define OMAP_LCDC_CTRL_LCD_TFT          (1 << 7)
  64 #define OMAP_LCDC_CTRL_LINE_IRQ_CLR_SEL (1 << 10)
  65
  66 #define OMAP_LCDC_IRQ_VSYNC             (1 << 2)
  67 #define OMAP_LCDC_IRQ_DONE              (1 << 3)
  68 #define OMAP_LCDC_IRQ_LOADED_PALETTE    (1 << 4)
  69 #define OMAP_LCDC_IRQ_LINE_NIRQ         (1 << 5)
  70 #define OMAP_LCDC_IRQ_LINE              (1 << 6)
  71 #define OMAP_LCDC_IRQ_MASK              (((1 << 5) - 1) << 2)
  72
  73 #define MAX_PALETTE_SIZE                PAGE_SIZE
  74
  75 enum lcdc_load_mode {
  76         OMAP_LCDC_LOAD_PALETTE,
  77         OMAP_LCDC_LOAD_FRAME,
  78         OMAP_LCDC_LOAD_PALETTE_AND_FRAME
  79 };
  80
  81 static struct omap_lcd_controller {
  82         enum omapfb_update_mode update_mode;
  83         int                     ext_mode;
  84
  85         unsigned long           frame_offset;
  86         int                     screen_width;
  87         int                     xres;
  88         int                     yres;
  89
  90         enum omapfb_color_format        color_mode;
  91         int                     bpp;
  92         void                    *palette_virt;
  93         dma_addr_t              palette_phys;
  94         int                     palette_code;
  95         int                     palette_size;
  96
  97         unsigned int            irq_mask;
  98         struct completion       last_frame_complete;
  99         struct completion       palette_load_complete;
 100         struct clk              *lcd_ck;
 101         struct omapfb_device    *fbdev;
 102
 103         void                    (*dma_callback)(void *data);
 104         void                    *dma_callback_data;
 105
 106         int                     fbmem_allocated;
 107         dma_addr_t              vram_phys;
 108         void                    *vram_virt;
 109         unsigned long           vram_size;
 110 } lcdc;
 111
 112 static void inline enable_irqs(int mask)
 113 {
 114         lcdc.irq_mask |= mask;
 115 }
 116
 117 static void inline disable_irqs(int mask)
 118 {
 119         lcdc.irq_mask &= ~mask;
 120 }
 121
 122 static void set_load_mode(enum lcdc_load_mode mode)
 123 {
 124         u32 l;
 125
 126         l = omap_readl(OMAP_LCDC_CONTROL);
 127         l &= ~(3 << 20);
 128         switch (mode) {
 129         case OMAP_LCDC_LOAD_PALETTE:
 130                 l |= 1 << 20;
 131                 break;
 132         case OMAP_LCDC_LOAD_FRAME:
 133                 l |= 2 << 20;
 134                 break;
 135         case OMAP_LCDC_LOAD_PALETTE_AND_FRAME:
 136                 break;
 137         default:
 138                 BUG();
 139         }
 140         omap_writel(l, OMAP_LCDC_CONTROL);
 141 }
 142
 143 static void enable_controller(void)
 144 {
 145         u32 l;
 146
 147         l = omap_readl(OMAP_LCDC_CONTROL);
 148         l |= OMAP_LCDC_CTRL_LCD_EN;
 149         l &= ~OMAP_LCDC_IRQ_MASK;
 150         l |= lcdc.irq_mask | OMAP_LCDC_IRQ_DONE;        /* enabled IRQs */
 151         omap_writel(l, OMAP_LCDC_CONTROL);
 152 }
 153
 154 static void disable_controller_async(void)
 155 {
 156         u32 l;
 157         u32 mask;
 158
 159         l = omap_readl(OMAP_LCDC_CONTROL);
 160         mask = OMAP_LCDC_CTRL_LCD_EN | OMAP_LCDC_IRQ_MASK;
 161         /* Preserve the DONE mask, since we still want to get the
 162          * final DONE irq. It will be disabled in the IRQ handler.
 163          */
 164         mask &= ~OMAP_LCDC_IRQ_DONE;
 165         l &= ~mask;
 166         omap_writel(l, OMAP_LCDC_CONTROL);
 167 }
 168
 169 static void disable_controller(void)
 170 {
 171         init_completion(&lcdc.last_frame_complete);
 172         disable_controller_async();
 173         if (!wait_for_completion_timeout(&lcdc.last_frame_complete,
 174                                 msecs_to_jiffies(500)))
 175                 dev_err(lcdc.fbdev->dev, "timeout waiting for FRAME DONE\n");
 176 }
 177
 178 static void reset_controller(u32 status)
 179 {
 180         static unsigned long reset_count = 0;
 181         static unsigned long last_jiffies = 0;
 182
 183         disable_controller_async();
 184         reset_count++;
 185         if (reset_count == 1 || time_after(jiffies, last_jiffies + HZ)) {
 186                 dev_err(lcdc.fbdev->dev,
 187                           "resetting (status %#010x,reset count %lu)\n",
 188                           status, reset_count);
 189                 last_jiffies = jiffies;
 190         }
 191         if (reset_count < 100) {
 192                 enable_controller();
 193         } else {
 194                 reset_count = 0;
 195                 dev_err(lcdc.fbdev->dev,
 196                         "too many reset attempts, giving up.\n");
 197         }
 198 }
 199
 200 /* Configure the LCD DMA according to the current mode specified by parameters
 201  * in lcdc.fbdev and fbdev->var.
 202  */
 203 static void setup_lcd_dma(void)
 204 {
 205         static const int dma_elem_type[] = {
 206                 0,
 207                 OMAP_DMA_DATA_TYPE_S8,
 208                 OMAP_DMA_DATA_TYPE_S16,
 209                 0,
 210                 OMAP_DMA_DATA_TYPE_S32,
 211         };
 212         struct omapfb_plane_struct *plane = lcdc.fbdev->fb_info[0]->par;
 213         struct fb_var_screeninfo *var = &lcdc.fbdev->fb_info[0]->var;
 214         unsigned long   src;
 215         int             esize, xelem, yelem;
 216
 217         src = lcdc.vram_phys + lcdc.frame_offset;
 218
 219         switch (var->rotate) {
 220         case 0:
 221                 if (plane->info.mirror || (src & 3) ||
 222                     lcdc.color_mode == OMAPFB_COLOR_YUV420 ||
 223                     (lcdc.xres & 1))
 224                         esize = 2;
 225                 else
 226                         esize = 4;
 227                 xelem = lcdc.xres * lcdc.bpp / 8 / esize;
 228                 yelem = lcdc.yres;
 229                 break;
 230         case 90:
 231         case 180:
 232         case 270:
 233                 if (cpu_is_omap15xx()) {
 234                         BUG();
 235                 }
 236                 esize = 2;
 237                 xelem = lcdc.yres * lcdc.bpp / 16;
 238                 yelem = lcdc.xres;
 239                 break;
 240         default:
 241                 BUG();
 242                 return;
 243         }
 244 #ifdef VERBOSE
 245         dev_dbg(lcdc.fbdev->dev,
 246                  "setup_dma: src %#010lx esize %d xelem %d yelem %d\n",
 247                  src, esize, xelem, yelem);
 248 #endif
 249         omap_set_lcd_dma_b1(src, xelem, yelem, dma_elem_type[esize]);
 250         if (!cpu_is_omap15xx()) {
 251                 int bpp = lcdc.bpp;
 252
 253                 /* YUV support is only for external mode when we have the
 254                  * YUV window embedded in a 16bpp frame buffer.
 255                  */
 256                 if (lcdc.color_mode == OMAPFB_COLOR_YUV420)
 257                         bpp = 16;
 258                 /* Set virtual xres elem size */
 259                 omap_set_lcd_dma_b1_vxres(
 260                         lcdc.screen_width * bpp / 8 / esize);
 261                 /* Setup transformations */
 262                 omap_set_lcd_dma_b1_rotation(var->rotate);
 263                 omap_set_lcd_dma_b1_mirror(plane->info.mirror);
 264         }
 265         omap_setup_lcd_dma();
 266 }
 267
 268 static irqreturn_t lcdc_irq_handler(int irq, void *dev_id)
 269 {
 270         u32 status;
 271
 272         status = omap_readl(OMAP_LCDC_STATUS);
 273
 274         if (status & (OMAP_LCDC_STAT_FUF | OMAP_LCDC_STAT_SYNC_LOST))
 275                 reset_controller(status);
 276         else {
 277                 if (status & OMAP_LCDC_STAT_DONE) {
 278                         u32 l;
 279
 280                         /* Disable IRQ_DONE. The status bit will be cleared
 281                          * only when the controller is reenabled and we don't
 282                          * want to get more interrupts.
 283                          */
 284                         l = omap_readl(OMAP_LCDC_CONTROL);
 285                         l &= ~OMAP_LCDC_IRQ_DONE;
 286                         omap_writel(l, OMAP_LCDC_CONTROL);
 287                         complete(&lcdc.last_frame_complete);
 288                 }
 289                 if (status & OMAP_LCDC_STAT_LOADED_PALETTE) {
 290                         disable_controller_async();
 291                         complete(&lcdc.palette_load_complete);
 292                 }
 293         }
 294
 295         /* Clear these interrupt status bits.
 296          * Sync_lost, FUF bits were cleared by disabling the LCD controller
 297          * LOADED_PALETTE can be cleared this way only in palette only
 298          * load mode. In other load modes it's cleared by disabling the
 299          * controller.
 300          */
 301         status &= ~(OMAP_LCDC_STAT_VSYNC |
 302                     OMAP_LCDC_STAT_LOADED_PALETTE |
 303                     OMAP_LCDC_STAT_ABC |
 304                     OMAP_LCDC_STAT_LINE_INT);
 305         omap_writel(status, OMAP_LCDC_STATUS);
 306         return IRQ_HANDLED;
 307 }
 308
 309 /* Change to a new video mode. We defer this to a later time to avoid any
 310  * flicker and not to mess up the current LCD DMA context. For this we disable
 311  * the LCD controler, which will generate a DONE irq after the last frame has
 312  * been transferred. Then it'll be safe to reconfigure both the LCD controller
 313  * as well as the LCD DMA.
 314  */
 315 static int omap_lcdc_setup_plane(int plane, int channel_out,
 316                                  unsigned long offset, int screen_width,
 317                                  int pos_x, int pos_y, int width, int height,
 318                                  int color_mode)
 319 {
 320         struct fb_var_screeninfo *var = &lcdc.fbdev->fb_info[0]->var;
 321         struct lcd_panel *panel = lcdc.fbdev->panel;
 322         int rot_x, rot_y;
 323
 324         if (var->rotate == 0) {
 325                 rot_x = panel->x_res;
 326                 rot_y = panel->y_res;
 327         } else {
 328                 rot_x = panel->y_res;
 329                 rot_y = panel->x_res;
 330         }
 331         if (plane != 0 || channel_out != 0 || pos_x != 0 || pos_y != 0 ||
 332             width > rot_x || height > rot_y) {
 333 #ifdef VERBOSE
 334                 dev_dbg(lcdc.fbdev->dev,
 335                         "invalid plane params plane %d pos_x %d pos_y %d "
 336                         "w %d h %d\n", plane, pos_x, pos_y, width, height);
 337 #endif
 338                 return -EINVAL;
 339         }
 340
 341         lcdc.frame_offset = offset;
 342         lcdc.xres = width;
 343         lcdc.yres = height;
 344         lcdc.screen_width = screen_width;
 345         lcdc.color_mode = color_mode;
 346
 347         switch (color_mode) {
 348         case OMAPFB_COLOR_CLUT_8BPP:
 349                 lcdc.bpp = 8;
 350                 lcdc.palette_code = 0x3000;
 351                 lcdc.palette_size = 512;
 352                 break;
 353         case OMAPFB_COLOR_RGB565:
 354                 lcdc.bpp = 16;
 355                 lcdc.palette_code = 0x4000;
 356                 lcdc.palette_size = 32;
 357                 break;
 358         case OMAPFB_COLOR_RGB444:
 359                 lcdc.bpp = 16;
 360                 lcdc.palette_code = 0x4000;
 361                 lcdc.palette_size = 32;
 362                 break;
 363         case OMAPFB_COLOR_YUV420:
 364                 if (lcdc.ext_mode) {
 365                         lcdc.bpp = 12;
 366                         break;
 367                 }
 368                 /* fallthrough */
 369         case OMAPFB_COLOR_YUV422:
 370                 if (lcdc.ext_mode) {
 371                         lcdc.bpp = 16;
 372                         break;
 373                 }
 374                 /* fallthrough */
 375         default:
 376                 /* FIXME: other BPPs.
 377                  * bpp1: code  0,     size 256
 378                  * bpp2: code  0x1000 size 256
 379                  * bpp4: code  0x2000 size 256
 380                  * bpp12: code 0x4000 size 32
 381                  */
 382                 dev_dbg(lcdc.fbdev->dev, "invalid color mode %d\n", color_mode);
 383                 BUG();
 384                 return -1;
 385         }
 386
 387         if (lcdc.ext_mode) {
 388                 setup_lcd_dma();
 389                 return 0;
 390         }
 391
 392         if (lcdc.update_mode == OMAPFB_AUTO_UPDATE) {
 393                 disable_controller();
 394                 omap_stop_lcd_dma();
 395                 setup_lcd_dma();
 396                 enable_controller();
 397         }
 398
 399         return 0;
 400 }
 401
 402 static int omap_lcdc_enable_plane(int plane, int enable)
 403 {
 404         dev_dbg(lcdc.fbdev->dev,
 405                 "plane %d enable %d update_mode %d ext_mode %d\n",
 406                 plane, enable, lcdc.update_mode, lcdc.ext_mode);
 407         if (plane != OMAPFB_PLANE_GFX)
 408                 return -EINVAL;
 409
 410         return 0;
 411 }
 412
 413 /* Configure the LCD DMA for a palette load operation and do the palette
 414  * downloading synchronously. We don't use the frame+palette load mode of
 415  * the controller, since the palette can always be downloaded seperately.
 416  */
 417 static void load_palette(void)
 418 {
 419         u16     *palette;
 420
 421         palette = (u16 *)lcdc.palette_virt;
 422
 423         *(u16 *)palette &= 0x0fff;
 424         *(u16 *)palette |= lcdc.palette_code;
 425
 426         omap_set_lcd_dma_b1(lcdc.palette_phys,
 427                 lcdc.palette_size / 4 + 1, 1, OMAP_DMA_DATA_TYPE_S32);
 428
 429         omap_set_lcd_dma_single_transfer(1);
 430         omap_setup_lcd_dma();
 431
 432         init_completion(&lcdc.palette_load_complete);
 433         enable_irqs(OMAP_LCDC_IRQ_LOADED_PALETTE);
 434         set_load_mode(OMAP_LCDC_LOAD_PALETTE);
 435         enable_controller();
 436         if (!wait_for_completion_timeout(&lcdc.palette_load_complete,
 437                                 msecs_to_jiffies(500)))
 438                 dev_err(lcdc.fbdev->dev, "timeout waiting for FRAME DONE\n");
 439         /* The controller gets disabled in the irq handler */
 440         disable_irqs(OMAP_LCDC_IRQ_LOADED_PALETTE);
 441         omap_stop_lcd_dma();
 442
 443         omap_set_lcd_dma_single_transfer(lcdc.ext_mode);
 444 }
 445
 446 /* Used only in internal controller mode */
 447 static int omap_lcdc_setcolreg(u_int regno, u16 red, u16 green, u16 blue,
 448                                u16 transp, int update_hw_pal)
 449 {
 450         u16 *palette;
 451
 452         if (lcdc.color_mode != OMAPFB_COLOR_CLUT_8BPP || regno > 255)
 453                 return -EINVAL;
 454
 455         palette = (u16 *)lcdc.palette_virt;
 456
 457         palette[regno] &= ~0x0fff;
 458         palette[regno] |= ((red >> 12) << 8) | ((green >> 12) << 4 ) |
 459                            (blue >> 12);
 460
 461         if (update_hw_pal) {
 462                 disable_controller();
 463                 omap_stop_lcd_dma();
 464                 load_palette();
 465                 setup_lcd_dma();
 466                 set_load_mode(OMAP_LCDC_LOAD_FRAME);
 467                 enable_controller();
 468         }
 469
 470         return 0;
 471 }
 472
 473 static void calc_ck_div(int is_tft, int pck, int *pck_div)
 474 {
 475         unsigned long lck;
 476
 477         pck = max(1, pck);
 478         lck = clk_get_rate(lcdc.lcd_ck);
 479         *pck_div = (lck + pck - 1) / pck;
 480         if (is_tft)
 481                 *pck_div = max(2, *pck_div);
 482         else
 483                 *pck_div = max(3, *pck_div);
 484         if (*pck_div > 255) {
 485                 /* FIXME: try to adjust logic clock divider as well */
 486                 *pck_div = 255;
 487                 dev_warn(lcdc.fbdev->dev, "pixclock %d kHz too low.\n",
 488                          pck / 1000);
 489         }
 490 }
 491
 492 static void inline setup_regs(void)
 493 {
 494         u32 l;
 495         struct lcd_panel *panel = lcdc.fbdev->panel;
 496         int is_tft = panel->config & OMAP_LCDC_PANEL_TFT;
 497         unsigned long lck;
 498         int pcd;
 499
 500         l = omap_readl(OMAP_LCDC_CONTROL);
 501         l &= ~OMAP_LCDC_CTRL_LCD_TFT;
 502         l |= is_tft ? OMAP_LCDC_CTRL_LCD_TFT : 0;
 503 #ifdef CONFIG_MACH_OMAP_PALMTE
 504 /* FIXME:if (machine_is_omap_palmte()) { */
 505                 /* PalmTE uses alternate TFT setting in 8BPP mode */
 506                 l |= (is_tft && panel->bpp == 8) ? 0x810000 : 0;
 507 /*      } */
 508 #endif
 509         omap_writel(l, OMAP_LCDC_CONTROL);
 510
 511         l = omap_readl(OMAP_LCDC_TIMING2);
 512         l &= ~(((1 << 6) - 1) << 20);
 513         l |= (panel->config & OMAP_LCDC_SIGNAL_MASK) << 20;
 514         omap_writel(l, OMAP_LCDC_TIMING2);
 515
 516         l = panel->x_res - 1;
 517         l |= (panel->hsw - 1) << 10;
 518         l |= (panel->hfp - 1) << 16;
 519         l |= (panel->hbp - 1) << 24;
 520         omap_writel(l, OMAP_LCDC_TIMING0);
 521
 522         l = panel->y_res - 1;
 523         l |= (panel->vsw - 1) << 10;
 524         l |= panel->vfp << 16;
 525         l |= panel->vbp << 24;
 526         omap_writel(l, OMAP_LCDC_TIMING1);
 527
 528         l = omap_readl(OMAP_LCDC_TIMING2);
 529         l &= ~0xff;
 530
 531         lck = clk_get_rate(lcdc.lcd_ck);
 532
 533         if (!panel->pcd)
 534                 calc_ck_div(is_tft, panel->pixel_clock * 1000, &pcd);
 535         else {
 536                 dev_warn(lcdc.fbdev->dev,
 537                     "Pixel clock divider value is obsolete.\n"
 538                     "Try to set pixel_clock to %lu and pcd to 0 "
 539                     "in drivers/video/omap/lcd_%s.c and submit a patch.\n",
 540                         lck / panel->pcd / 1000, panel->name);
 541
 542                 pcd = panel->pcd;
 543         }
 544         l |= pcd & 0xff;
 545         l |= panel->acb << 8;
 546         omap_writel(l, OMAP_LCDC_TIMING2);
 547
 548         /* update panel info with the exact clock */
 549         panel->pixel_clock = lck / pcd / 1000;
 550 }
 551
 552 /* Configure the LCD controller, download the color palette and start a looped
 553  * DMA transfer of the frame image data. Called only in internal
 554  * controller mode.
 555  */
 556 static int omap_lcdc_set_update_mode(enum omapfb_update_mode mode)
 557 {
 558         int r = 0;
 559
 560         if (mode != lcdc.update_mode) {
 561                 switch (mode) {
 562                 case OMAPFB_AUTO_UPDATE:
 563                         setup_regs();
 564                         load_palette();
 565
 566                         /* Setup and start LCD DMA */
 567                         setup_lcd_dma();
 568
 569                         set_load_mode(OMAP_LCDC_LOAD_FRAME);
 570                         enable_irqs(OMAP_LCDC_IRQ_DONE);
 571                         /* This will start the actual DMA transfer */
 572                         enable_controller();
 573                         lcdc.update_mode = mode;
 574                         break;
 575                 case OMAPFB_UPDATE_DISABLED:
 576                         disable_controller();
 577                         omap_stop_lcd_dma();
 578                         lcdc.update_mode = mode;
 579                         break;
 580                 default:
 581                         r = -EINVAL;
 582                 }
 583         }
 584
 585         return r;
 586 }
 587
 588 static enum omapfb_update_mode omap_lcdc_get_update_mode(void)
 589 {
 590         return lcdc.update_mode;
 591 }
 592
 593 /* PM code called only in internal controller mode */
 594 static void omap_lcdc_suspend(void)
 595 {
 596         if (lcdc.update_mode == OMAPFB_AUTO_UPDATE) {
 597                 disable_controller();
 598                 omap_stop_lcd_dma();
 599         }
 600 }
 601
 602 static void omap_lcdc_resume(void)
 603 {
 604         if (lcdc.update_mode == OMAPFB_AUTO_UPDATE) {
 605                 setup_regs();
 606                 load_palette();
 607                 setup_lcd_dma();
 608                 set_load_mode(OMAP_LCDC_LOAD_FRAME);
 609                 enable_irqs(OMAP_LCDC_IRQ_DONE);
 610                 enable_controller();
 611         }
 612 }
 613
 614 static unsigned long omap_lcdc_get_caps(void)
 615 {
 616         return 0;
 617 }
 618
 619 int omap_lcdc_set_dma_callback(void (*callback)(void *data), void *data)
 620 {
 621         BUG_ON(callback == NULL);
 622
 623         if (lcdc.dma_callback)
 624                 return -EBUSY;
 625         else {
 626                 lcdc.dma_callback = callback;
 627                 lcdc.dma_callback_data = data;
 628         }
 629         return 0;
 630 }
 631 EXPORT_SYMBOL(omap_lcdc_set_dma_callback);
 632
 633 void omap_lcdc_free_dma_callback(void)
 634 {
 635         lcdc.dma_callback = NULL;
 636 }
 637 EXPORT_SYMBOL(omap_lcdc_free_dma_callback);
 638
 639 static void lcdc_dma_handler(u16 status, void *data)
 640 {
 641         if (lcdc.dma_callback)
 642                 lcdc.dma_callback(lcdc.dma_callback_data);
 643 }
 644
 645 static int mmap_kern(void)
 646 {
 647         struct vm_struct        *kvma;
 648         struct vm_area_struct   vma;
 649         pgprot_t                pgprot;
 650         unsigned long           vaddr;
 651
 652         kvma = get_vm_area(lcdc.vram_size, VM_IOREMAP);
 653         if (kvma == NULL) {
 654                 dev_err(lcdc.fbdev->dev, "can't get kernel vm area\n");
 655                 return -ENOMEM;
 656         }
 657         vma.vm_mm = &init_mm;
 658
 659         vaddr = (unsigned long)kvma->addr;
 660         vma.vm_start = vaddr;
 661         vma.vm_end = vaddr + lcdc.vram_size;
 662
 663         pgprot = pgprot_writecombine(pgprot_kernel);
 664         if (io_remap_pfn_range(&vma, vaddr,
 665                            lcdc.vram_phys >> PAGE_SHIFT,
 666                            lcdc.vram_size, pgprot) < 0) {
 667                 dev_err(lcdc.fbdev->dev, "kernel mmap for FB memory failed\n");
 668                 return -EAGAIN;
 669         }
 670
 671         lcdc.vram_virt = (void *)vaddr;
 672
 673         return 0;
 674 }
 675
 676 static void unmap_kern(void)
 677 {
 678         vunmap(lcdc.vram_virt);
 679 }
 680
 681 static int alloc_palette_ram(void)
 682 {
 683         lcdc.palette_virt = dma_alloc_writecombine(lcdc.fbdev->dev,
 684                 MAX_PALETTE_SIZE, &lcdc.palette_phys, GFP_KERNEL);
 685         if (lcdc.palette_virt == NULL) {
 686                 dev_err(lcdc.fbdev->dev, "failed to alloc palette memory\n");
 687                 return -ENOMEM;
 688         }
 689         memset(lcdc.palette_virt, 0, MAX_PALETTE_SIZE);
 690
 691         return 0;
 692 }
 693
 694 static void free_palette_ram(void)
 695 {
 696         dma_free_writecombine(lcdc.fbdev->dev, MAX_PALETTE_SIZE,
 697                         lcdc.palette_virt, lcdc.palette_phys);
 698 }
 699
 700 static int alloc_fbmem(struct omapfb_mem_region *region)
 701 {
 702         int bpp;
 703         int frame_size;
 704         struct lcd_panel *panel = lcdc.fbdev->panel;
 705
 706         bpp = panel->bpp;
 707         if (bpp == 12)
 708                 bpp = 16;
 709         frame_size = PAGE_ALIGN(panel->x_res * bpp / 8 * panel->y_res);
 710         if (region->size > frame_size)
 711                 frame_size = region->size;
 712         lcdc.vram_size = frame_size;
 713         lcdc.vram_virt = dma_alloc_writecombine(lcdc.fbdev->dev,
 714                         lcdc.vram_size, &lcdc.vram_phys, GFP_KERNEL);
 715         if (lcdc.vram_virt == NULL) {
 716                 dev_err(lcdc.fbdev->dev, "unable to allocate FB DMA memory\n");
 717                 return -ENOMEM;
 718         }
 719         region->size = frame_size;
 720         region->paddr = lcdc.vram_phys;
 721         region->vaddr = lcdc.vram_virt;
 722         region->alloc = 1;
 723
 724         memset(lcdc.vram_virt, 0, lcdc.vram_size);
 725
 726         return 0;
 727 }
 728
 729 static void free_fbmem(void)
 730 {
 731         dma_free_writecombine(lcdc.fbdev->dev, lcdc.vram_size,
 732                               lcdc.vram_virt, lcdc.vram_phys);
 733 }
 734
 735 static int setup_fbmem(struct omapfb_mem_desc *req_md)
 736 {
 737         int r;
 738
 739         if (!req_md->region_cnt) {
 740                 dev_err(lcdc.fbdev->dev, "no memory regions defined\n");
 741                 return -EINVAL;
 742         }
 743
 744         if (req_md->region_cnt > 1) {
 745                 dev_err(lcdc.fbdev->dev, "only one plane is supported\n");
 746                 req_md->region_cnt = 1;
 747         }
 748
 749         if (req_md->region[0].paddr == 0) {
 750                 lcdc.fbmem_allocated = 1;
 751                 if ((r = alloc_fbmem(&req_md->region[0])) < 0)
 752                         return r;
 753                 return 0;
 754         }
 755
 756         lcdc.vram_phys = req_md->region[0].paddr;
 757         lcdc.vram_size = req_md->region[0].size;
 758
 759         if ((r = mmap_kern()) < 0)
 760                 return r;
 761
 762         dev_dbg(lcdc.fbdev->dev, "vram at %08x size %08lx mapped to 0x%p\n",
 763                  lcdc.vram_phys, lcdc.vram_size, lcdc.vram_virt);
 764
 765         return 0;
 766 }
 767
 768 static void cleanup_fbmem(void)
 769 {
 770         if (lcdc.fbmem_allocated)
 771                 free_fbmem();
 772         else
 773                 unmap_kern();
 774 }
 775
 776 static int omap_lcdc_init(struct omapfb_device *fbdev, int ext_mode,
 777                           struct omapfb_mem_desc *req_vram)
 778 {
 779         int r;
 780         u32 l;
 781         int rate;
 782         struct clk *tc_ck;
 783
 784         lcdc.irq_mask = 0;
 785
 786         lcdc.fbdev = fbdev;
 787         lcdc.ext_mode = ext_mode;
 788
 789         l = 0;
 790         omap_writel(l, OMAP_LCDC_CONTROL);
 791
 792         /* FIXME:
 793          * According to errata some platforms have a clock rate limitiation
 794          */
 795         lcdc.lcd_ck = clk_get(NULL, "lcd_ck");
 796         if (IS_ERR(lcdc.lcd_ck)) {
 797                 dev_err(fbdev->dev, "unable to access LCD clock\n");
 798                 r = PTR_ERR(lcdc.lcd_ck);
 799                 goto fail0;
 800         }
 801
 802         tc_ck = clk_get(NULL, "tc_ck");
 803         if (IS_ERR(tc_ck)) {
 804                 dev_err(fbdev->dev, "unable to access TC clock\n");
 805                 r = PTR_ERR(tc_ck);
 806                 goto fail1;
 807         }
 808
 809         rate = clk_get_rate(tc_ck);
 810         clk_put(tc_ck);
 811
 812         if (machine_is_ams_delta())
 813                 rate /= 4;
 814         if (machine_is_omap_h3())
 815                 rate /= 3;
 816         r = clk_set_rate(lcdc.lcd_ck, rate);
 817         if (r) {
 818                 dev_err(fbdev->dev, "failed to adjust LCD rate\n");
 819                 goto fail1;
 820         }
 821         clk_enable(lcdc.lcd_ck);
 822
 823         r = request_irq(OMAP_LCDC_IRQ, lcdc_irq_handler, 0, MODULE_NAME, fbdev);
 824         if (r) {
 825                 dev_err(fbdev->dev, "unable to get IRQ\n");
 826                 goto fail2;
 827         }
 828
 829         r = omap_request_lcd_dma(lcdc_dma_handler, NULL);
 830         if (r) {
 831                 dev_err(fbdev->dev, "unable to get LCD DMA\n");
 832                 goto fail3;
 833         }
 834
 835         omap_set_lcd_dma_single_transfer(ext_mode);
 836         omap_set_lcd_dma_ext_controller(ext_mode);
 837
 838         if (!ext_mode)
 839                 if ((r = alloc_palette_ram()) < 0)
 840                         goto fail4;
 841
 842         if ((r = setup_fbmem(req_vram)) < 0)
 843                 goto fail5;
 844
 845         pr_info("omapfb: LCDC initialized\n");
 846
 847         return 0;
 848 fail5:
 849         if (!ext_mode)
 850                 free_palette_ram();
 851 fail4:
 852         omap_free_lcd_dma();
 853 fail3:
 854         free_irq(OMAP_LCDC_IRQ, lcdc.fbdev);
 855 fail2:
 856         clk_disable(lcdc.lcd_ck);
 857 fail1:
 858         clk_put(lcdc.lcd_ck);
 859 fail0:
 860         return r;
 861 }
 862
 863 static void omap_lcdc_cleanup(void)
 864 {
 865         if (!lcdc.ext_mode)
 866                 free_palette_ram();
 867         cleanup_fbmem();
 868         omap_free_lcd_dma();
 869         free_irq(OMAP_LCDC_IRQ, lcdc.fbdev);
 870         clk_disable(lcdc.lcd_ck);
 871         clk_put(lcdc.lcd_ck);
 872 }
 873
 874 const struct lcd_ctrl omap1_int_ctrl = {
 875         .name                   = "internal",
 876         .init                   = omap_lcdc_init,
 877         .cleanup                = omap_lcdc_cleanup,
 878         .get_caps               = omap_lcdc_get_caps,
 879         .set_update_mode        = omap_lcdc_set_update_mode,
 880         .get_update_mode        = omap_lcdc_get_update_mode,
 881         .update_window          = NULL,
 882         .suspend                = omap_lcdc_suspend,
 883         .resume                 = omap_lcdc_resume,
 884         .setup_plane            = omap_lcdc_setup_plane,
 885         .enable_plane           = omap_lcdc_enable_plane,
 886         .setcolreg              = omap_lcdc_setcolreg,
 887 };