2 * File: drivers/video/omap/hwa742.c
4 * Epson HWA742 LCD controller driver
6 * Copyright (C) 2004-2005 Nokia Corporation
7 * Authors: Juha Yrjölä <juha.yrjola@nokia.com>
8 * Imre Deak <imre.deak@nokia.com>
9 * YUV support: Jussi Laako <jussi.laako@nokia.com>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
25 #include <linux/module.h>
28 #include <linux/delay.h>
29 #include <linux/clk.h>
31 #include <asm/arch/dma.h>
32 #include <asm/arch/omapfb.h>
33 #include <asm/arch/hwa742.h>
35 #define HWA742_REV_CODE_REG 0x0
36 #define HWA742_CONFIG_REG 0x2
37 #define HWA742_PLL_DIV_REG 0x4
38 #define HWA742_PLL_0_REG 0x6
39 #define HWA742_PLL_1_REG 0x8
40 #define HWA742_PLL_2_REG 0xa
41 #define HWA742_PLL_3_REG 0xc
42 #define HWA742_PLL_4_REG 0xe
43 #define HWA742_CLK_SRC_REG 0x12
44 #define HWA742_PANEL_TYPE_REG 0x14
45 #define HWA742_H_DISP_REG 0x16
46 #define HWA742_H_NDP_REG 0x18
47 #define HWA742_V_DISP_1_REG 0x1a
48 #define HWA742_V_DISP_2_REG 0x1c
49 #define HWA742_V_NDP_REG 0x1e
50 #define HWA742_HS_W_REG 0x20
51 #define HWA742_HP_S_REG 0x22
52 #define HWA742_VS_W_REG 0x24
53 #define HWA742_VP_S_REG 0x26
54 #define HWA742_PCLK_POL_REG 0x28
55 #define HWA742_INPUT_MODE_REG 0x2a
56 #define HWA742_TRANSL_MODE_REG1 0x2e
57 #define HWA742_DISP_MODE_REG 0x34
58 #define HWA742_WINDOW_TYPE 0x36
59 #define HWA742_WINDOW_X_START_0 0x38
60 #define HWA742_WINDOW_X_START_1 0x3a
61 #define HWA742_WINDOW_Y_START_0 0x3c
62 #define HWA742_WINDOW_Y_START_1 0x3e
63 #define HWA742_WINDOW_X_END_0 0x40
64 #define HWA742_WINDOW_X_END_1 0x42
65 #define HWA742_WINDOW_Y_END_0 0x44
66 #define HWA742_WINDOW_Y_END_1 0x46
67 #define HWA742_MEMORY_WRITE_LSB 0x48
68 #define HWA742_MEMORY_WRITE_MSB 0x49
69 #define HWA742_MEMORY_READ_0 0x4a
70 #define HWA742_MEMORY_READ_1 0x4c
71 #define HWA742_MEMORY_READ_2 0x4e
72 #define HWA742_POWER_SAVE 0x56
73 #define HWA742_NDP_CTRL 0x58
75 #define HWA742_AUTO_UPDATE_TIME (HZ / 20)
77 /* Reserve 4 request slots for requests in irq context */
78 #define REQ_POOL_SIZE 24
79 #define IRQ_REQ_POOL_SIZE 4
81 #define REQ_FROM_IRQ_POOL 0x01
83 #define REQ_COMPLETE 0
87 int x, y, width, height;
92 struct hwa742_request {
93 struct list_head entry;
96 int (*handler)(struct hwa742_request *req);
97 void (*complete)(void *data);
101 struct update_param update;
102 struct completion *sync;
107 enum omapfb_update_mode update_mode;
108 enum omapfb_update_mode update_mode_before_suspend;
110 struct timer_list auto_update_timer;
111 int stop_auto_update;
112 struct omapfb_update_window auto_update_window;
113 unsigned te_connected:1;
114 unsigned vsync_only:1;
116 struct hwa742_request req_pool[REQ_POOL_SIZE];
117 struct list_head pending_req_list;
118 struct list_head free_req_list;
119 struct semaphore req_sema;
122 struct extif_timings reg_timings, lut_timings;
128 u32 max_transmit_size;
129 u32 extif_clk_period;
130 unsigned long pix_tx_time;
131 unsigned long line_upd_time;
134 struct omapfb_device *fbdev;
135 struct lcd_ctrl_extif *extif;
136 struct lcd_ctrl *int_ctrl;
138 void (*power_up)(struct device *dev);
139 void (*power_down)(struct device *dev);
142 struct lcd_ctrl hwa742_ctrl;
144 static u8 hwa742_read_reg(u8 reg)
148 hwa742.extif->set_bits_per_cycle(8);
149 hwa742.extif->write_command(®, 1);
150 hwa742.extif->read_data(&data, 1);
155 static void hwa742_write_reg(u8 reg, u8 data)
157 hwa742.extif->set_bits_per_cycle(8);
158 hwa742.extif->write_command(®, 1);
159 hwa742.extif->write_data(&data, 1);
162 static void set_window_regs(int x_start, int y_start, int x_end, int y_end)
170 tmp[1] = x_start >> 8;
172 tmp[3] = y_start >> 8;
178 hwa742.extif->set_bits_per_cycle(8);
179 cmd = HWA742_WINDOW_X_START_0;
181 hwa742.extif->write_command(&cmd, 1);
183 hwa742.extif->write_data(tmp, 8);
186 static void set_format_regs(int conv, int transl, int flags)
188 if (flags & OMAPFB_FORMAT_FLAG_DOUBLE) {
189 hwa742.window_type = ((hwa742.window_type & 0xfc) | 0x01);
191 dev_dbg(hwa742.fbdev->dev, "hwa742: enabled pixel doubling\n");
194 hwa742.window_type = (hwa742.window_type & 0xfc);
196 dev_dbg(hwa742.fbdev->dev, "hwa742: disabled pixel doubling\n");
200 hwa742_write_reg(HWA742_INPUT_MODE_REG, conv);
201 hwa742_write_reg(HWA742_TRANSL_MODE_REG1, transl);
202 hwa742_write_reg(HWA742_WINDOW_TYPE, hwa742.window_type);
205 static void enable_tearsync(int y, int width, int height, int screen_height,
210 b = hwa742_read_reg(HWA742_NDP_CTRL);
212 hwa742_write_reg(HWA742_NDP_CTRL, b);
214 if (likely(hwa742.vsync_only || force_vsync)) {
215 hwa742.extif->enable_tearsync(1, 0);
219 if (width * hwa742.pix_tx_time < hwa742.line_upd_time) {
220 hwa742.extif->enable_tearsync(1, 0);
224 if ((width * hwa742.pix_tx_time / 1000) * height <
225 (y + height) * (hwa742.line_upd_time / 1000)) {
226 hwa742.extif->enable_tearsync(1, 0);
230 hwa742.extif->enable_tearsync(1, y + 1);
233 static void disable_tearsync(void)
237 hwa742.extif->enable_tearsync(0, 0);
239 b = hwa742_read_reg(HWA742_NDP_CTRL);
241 hwa742_write_reg(HWA742_NDP_CTRL, b);
244 static inline struct hwa742_request *alloc_req(void)
247 struct hwa742_request *req;
251 down(&hwa742.req_sema);
253 req_flags = REQ_FROM_IRQ_POOL;
255 spin_lock_irqsave(&hwa742.req_lock, flags);
256 BUG_ON(list_empty(&hwa742.free_req_list));
257 req = list_entry(hwa742.free_req_list.next,
258 struct hwa742_request, entry);
259 list_del(&req->entry);
260 spin_unlock_irqrestore(&hwa742.req_lock, flags);
262 INIT_LIST_HEAD(&req->entry);
263 req->flags = req_flags;
268 static inline void free_req(struct hwa742_request *req)
272 spin_lock_irqsave(&hwa742.req_lock, flags);
274 list_del(&req->entry);
275 list_add(&req->entry, &hwa742.free_req_list);
276 if (!(req->flags & REQ_FROM_IRQ_POOL))
277 up(&hwa742.req_sema);
279 spin_unlock_irqrestore(&hwa742.req_lock, flags);
282 static void process_pending_requests(void)
286 spin_lock_irqsave(&hwa742.req_lock, flags);
288 while (!list_empty(&hwa742.pending_req_list)) {
289 struct hwa742_request *req;
290 void (*complete)(void *);
293 req = list_entry(hwa742.pending_req_list.next,
294 struct hwa742_request, entry);
295 spin_unlock_irqrestore(&hwa742.req_lock, flags);
297 if (req->handler(req) == REQ_PENDING)
300 complete = req->complete;
301 complete_data = req->complete_data;
305 complete(complete_data);
307 spin_lock_irqsave(&hwa742.req_lock, flags);
310 spin_unlock_irqrestore(&hwa742.req_lock, flags);
313 static void submit_req_list(struct list_head *head)
318 spin_lock_irqsave(&hwa742.req_lock, flags);
319 if (likely(!list_empty(&hwa742.pending_req_list)))
321 list_splice_init(head, hwa742.pending_req_list.prev);
322 spin_unlock_irqrestore(&hwa742.req_lock, flags);
325 process_pending_requests();
328 static void request_complete(void *data)
330 struct hwa742_request *req = (struct hwa742_request *)data;
331 void (*complete)(void *);
334 complete = req->complete;
335 complete_data = req->complete_data;
340 complete(complete_data);
342 process_pending_requests();
345 static int send_frame_handler(struct hwa742_request *req)
347 struct update_param *par = &req->par.update;
354 unsigned long offset;
355 int color_mode = par->color_mode;
356 int flags = par->flags;
357 int scr_width = hwa742.fbdev->panel->x_res;
358 int scr_height = hwa742.fbdev->panel->y_res;
361 dev_dbg(hwa742.fbdev->dev, "x %d y %d w %d h %d scr_width %d "
362 "color_mode %d flags %d\n",
363 x, y, w, h, scr_width, color_mode, flags);
366 switch (color_mode) {
367 case OMAPFB_COLOR_YUV422:
372 case OMAPFB_COLOR_YUV420:
377 case OMAPFB_COLOR_RGB565:
386 if (hwa742.prev_flags != flags ||
387 hwa742.prev_color_mode != color_mode) {
388 set_format_regs(conv, transl, flags);
389 hwa742.prev_color_mode = color_mode;
390 hwa742.prev_flags = flags;
392 flags = req->par.update.flags;
393 if (flags & OMAPFB_FORMAT_FLAG_TEARSYNC)
394 enable_tearsync(y, scr_width, h, scr_height,
395 flags & OMAPFB_FORMAT_FLAG_FORCE_VSYNC);
399 set_window_regs(x, y, x + w, y + h);
401 offset = (scr_width * y + x) * bpp / 8;
403 hwa742.int_ctrl->setup_plane(OMAPFB_PLANE_GFX,
404 OMAPFB_CHANNEL_OUT_LCD, offset, scr_width, 0, 0, w, h,
407 hwa742.extif->set_bits_per_cycle(16);
409 hwa742.int_ctrl->enable_plane(OMAPFB_PLANE_GFX, 1);
410 hwa742.extif->transfer_area(w, h, request_complete, req);
415 static void send_frame_complete(void *data)
417 hwa742.int_ctrl->enable_plane(OMAPFB_PLANE_GFX, 0);
420 #define ADD_PREQ(_x, _y, _w, _h) do { \
422 req->handler = send_frame_handler; \
423 req->complete = send_frame_complete; \
424 req->par.update.x = _x; \
425 req->par.update.y = _y; \
426 req->par.update.width = _w; \
427 req->par.update.height = _h; \
428 req->par.update.color_mode = color_mode;\
429 req->par.update.flags = flags; \
430 list_add_tail(&req->entry, req_head); \
433 static void create_req_list(struct omapfb_update_window *win,
434 struct list_head *req_head)
436 struct hwa742_request *req;
439 int width = win->width;
440 int height = win->height;
444 flags = win->format & ~OMAPFB_FORMAT_MASK;
445 color_mode = win->format & OMAPFB_FORMAT_MASK;
448 ADD_PREQ(x, y, 1, height);
451 flags &= ~OMAPFB_FORMAT_FLAG_TEARSYNC;
454 unsigned int xspan = width & ~1;
455 unsigned int ystart = y;
456 unsigned int yspan = height;
458 if (xspan * height * 2 > hwa742.max_transmit_size) {
459 yspan = hwa742.max_transmit_size / (xspan * 2);
460 ADD_PREQ(x, ystart, xspan, yspan);
462 yspan = height - yspan;
463 flags &= ~OMAPFB_FORMAT_FLAG_TEARSYNC;
466 ADD_PREQ(x, ystart, xspan, yspan);
469 flags &= ~OMAPFB_FORMAT_FLAG_TEARSYNC;
472 ADD_PREQ(x, y, 1, height);
475 static void auto_update_complete(void *data)
477 if (!hwa742.stop_auto_update)
478 mod_timer(&hwa742.auto_update_timer,
479 jiffies + HWA742_AUTO_UPDATE_TIME);
482 static void hwa742_update_window_auto(unsigned long arg)
485 struct hwa742_request *last;
487 create_req_list(&hwa742.auto_update_window, &req_list);
488 last = list_entry(req_list.prev, struct hwa742_request, entry);
490 last->complete = auto_update_complete;
491 last->complete_data = NULL;
493 submit_req_list(&req_list);
496 int hwa742_update_window_async(struct fb_info *fbi,
497 struct omapfb_update_window *win,
498 void (*complete_callback)(void *arg),
499 void *complete_callback_data)
502 struct hwa742_request *last;
505 if (hwa742.update_mode != OMAPFB_MANUAL_UPDATE) {
506 dev_dbg(hwa742.fbdev->dev, "invalid update mode\n");
510 if (unlikely(win->format &
511 ~(0x03 | OMAPFB_FORMAT_FLAG_DOUBLE |
512 OMAPFB_FORMAT_FLAG_TEARSYNC | OMAPFB_FORMAT_FLAG_FORCE_VSYNC))) {
513 dev_dbg(hwa742.fbdev->dev, "invalid window flag");
518 create_req_list(win, &req_list);
519 last = list_entry(req_list.prev, struct hwa742_request, entry);
521 last->complete = complete_callback;
522 last->complete_data = (void *)complete_callback_data;
524 submit_req_list(&req_list);
529 EXPORT_SYMBOL(hwa742_update_window_async);
531 static int hwa742_setup_plane(int plane, int channel_out,
532 unsigned long offset, int screen_width,
533 int pos_x, int pos_y, int width, int height,
536 if (plane != OMAPFB_PLANE_GFX ||
537 channel_out != OMAPFB_CHANNEL_OUT_LCD)
543 static int hwa742_enable_plane(int plane, int enable)
548 hwa742.int_ctrl->enable_plane(plane, enable);
553 static int sync_handler(struct hwa742_request *req)
555 complete(req->par.sync);
559 static void hwa742_sync(void)
562 struct hwa742_request *req;
563 struct completion comp;
567 req->handler = sync_handler;
568 req->complete = NULL;
569 init_completion(&comp);
570 req->par.sync = ∁
572 list_add(&req->entry, &req_list);
573 submit_req_list(&req_list);
575 wait_for_completion(&comp);
578 static void hwa742_bind_client(struct omapfb_notifier_block *nb)
580 dev_dbg(hwa742.fbdev->dev, "update_mode %d\n", hwa742.update_mode);
581 if (hwa742.update_mode == OMAPFB_MANUAL_UPDATE) {
582 omapfb_notify_clients(hwa742.fbdev, OMAPFB_EVENT_READY);
586 static int hwa742_set_update_mode(enum omapfb_update_mode mode)
588 if (mode != OMAPFB_MANUAL_UPDATE && mode != OMAPFB_AUTO_UPDATE &&
589 mode != OMAPFB_UPDATE_DISABLED)
592 if (mode == hwa742.update_mode)
595 dev_info(hwa742.fbdev->dev, "HWA742: setting update mode to %s\n",
596 mode == OMAPFB_UPDATE_DISABLED ? "disabled" :
597 (mode == OMAPFB_AUTO_UPDATE ? "auto" : "manual"));
599 switch (hwa742.update_mode) {
600 case OMAPFB_MANUAL_UPDATE:
601 omapfb_notify_clients(hwa742.fbdev, OMAPFB_EVENT_DISABLED);
603 case OMAPFB_AUTO_UPDATE:
604 hwa742.stop_auto_update = 1;
605 del_timer_sync(&hwa742.auto_update_timer);
607 case OMAPFB_UPDATE_DISABLED:
611 hwa742.update_mode = mode;
613 hwa742.stop_auto_update = 0;
616 case OMAPFB_MANUAL_UPDATE:
617 omapfb_notify_clients(hwa742.fbdev, OMAPFB_EVENT_READY);
619 case OMAPFB_AUTO_UPDATE:
620 hwa742_update_window_auto(0);
622 case OMAPFB_UPDATE_DISABLED:
629 static enum omapfb_update_mode hwa742_get_update_mode(void)
631 return hwa742.update_mode;
634 static unsigned long round_to_extif_ticks(unsigned long ps, int div)
636 int bus_tick = hwa742.extif_clk_period * div;
637 return (ps + bus_tick - 1) / bus_tick * bus_tick;
640 static int calc_reg_timing(unsigned long sysclk, int div)
642 struct extif_timings *t;
643 unsigned long systim;
645 /* CSOnTime 0, WEOnTime 2 ns, REOnTime 2 ns,
646 * AccessTime 2 ns + 12.2 ns (regs),
647 * WEOffTime = WEOnTime + 1 ns,
648 * REOffTime = REOnTime + 16 ns (regs),
649 * CSOffTime = REOffTime + 1 ns
650 * ReadCycle = 2ns + 2*SYSCLK (regs),
651 * WriteCycle = 2*SYSCLK + 2 ns,
652 * CSPulseWidth = 10 ns */
653 systim = 1000000000 / (sysclk / 1000);
654 dev_dbg(hwa742.fbdev->dev, "HWA742 systim %lu ps extif_clk_period %u ps"
655 "extif_clk_div %d\n", systim, hwa742.extif_clk_period, div);
657 t = &hwa742.reg_timings;
658 memset(t, 0, sizeof(*t));
661 t->we_on_time = round_to_extif_ticks(t->cs_on_time + 2000, div);
662 t->re_on_time = round_to_extif_ticks(t->cs_on_time + 2000, div);
663 t->access_time = round_to_extif_ticks(t->re_on_time + 12200, div);
664 t->we_off_time = round_to_extif_ticks(t->we_on_time + 1000, div);
665 t->re_off_time = round_to_extif_ticks(t->re_on_time + 16000, div);
666 t->cs_off_time = round_to_extif_ticks(t->re_off_time + 1000, div);
667 t->we_cycle_time = round_to_extif_ticks(2 * systim + 2000, div);
668 if (t->we_cycle_time < t->we_off_time)
669 t->we_cycle_time = t->we_off_time;
670 t->re_cycle_time = round_to_extif_ticks(2 * systim + 2000, div);
671 if (t->re_cycle_time < t->re_off_time)
672 t->re_cycle_time = t->re_off_time;
673 t->cs_pulse_width = 0;
675 dev_dbg(hwa742.fbdev->dev, "[reg]cson %d csoff %d reon %d reoff %d\n",
676 t->cs_on_time, t->cs_off_time, t->re_on_time, t->re_off_time);
677 dev_dbg(hwa742.fbdev->dev, "[reg]weon %d weoff %d recyc %d wecyc %d\n",
678 t->we_on_time, t->we_off_time, t->re_cycle_time,
680 dev_dbg(hwa742.fbdev->dev, "[reg]rdaccess %d cspulse %d\n",
681 t->access_time, t->cs_pulse_width);
683 return hwa742.extif->convert_timings(t);
686 static int calc_lut_timing(unsigned long sysclk, int div)
688 struct extif_timings *t;
689 unsigned long systim;
691 /* CSOnTime 0, WEOnTime 2 ns, REOnTime 2 ns,
692 * AccessTime 2 ns + 4 * SYSCLK + 26 (lut),
693 * WEOffTime = WEOnTime + 1 ns,
694 * REOffTime = REOnTime + 4*SYSCLK + 26 ns (lut),
695 * CSOffTime = REOffTime + 1 ns
696 * ReadCycle = 2ns + 4*SYSCLK + 26 ns (lut),
697 * WriteCycle = 2*SYSCLK + 2 ns,
698 * CSPulseWidth = 10 ns
700 systim = 1000000000 / (sysclk / 1000);
701 dev_dbg(hwa742.fbdev->dev, "HWA742 systim %lu ps extif_clk_period %u ps"
702 "extif_clk_div %d\n", systim, hwa742.extif_clk_period, div);
704 t = &hwa742.lut_timings;
705 memset(t, 0, sizeof(*t));
710 t->we_on_time = round_to_extif_ticks(t->cs_on_time + 2000, div);
711 t->re_on_time = round_to_extif_ticks(t->cs_on_time + 2000, div);
712 t->access_time = round_to_extif_ticks(t->re_on_time + 4 * systim +
714 t->we_off_time = round_to_extif_ticks(t->we_on_time + 1000, div);
715 t->re_off_time = round_to_extif_ticks(t->re_on_time + 4 * systim +
717 t->cs_off_time = round_to_extif_ticks(t->re_off_time + 1000, div);
718 t->we_cycle_time = round_to_extif_ticks(2 * systim + 2000, div);
719 if (t->we_cycle_time < t->we_off_time)
720 t->we_cycle_time = t->we_off_time;
721 t->re_cycle_time = round_to_extif_ticks(2000 + 4 * systim + 26000, div);
722 if (t->re_cycle_time < t->re_off_time)
723 t->re_cycle_time = t->re_off_time;
724 t->cs_pulse_width = 0;
726 dev_dbg(hwa742.fbdev->dev, "[lut]cson %d csoff %d reon %d reoff %d\n",
727 t->cs_on_time, t->cs_off_time, t->re_on_time, t->re_off_time);
728 dev_dbg(hwa742.fbdev->dev, "[lut]weon %d weoff %d recyc %d wecyc %d\n",
729 t->we_on_time, t->we_off_time, t->re_cycle_time,
731 dev_dbg(hwa742.fbdev->dev, "[lut]rdaccess %d cspulse %d\n",
732 t->access_time, t->cs_pulse_width);
734 return hwa742.extif->convert_timings(t);
737 static int calc_extif_timings(unsigned long sysclk, int *extif_mem_div)
742 hwa742.extif->get_clk_info(&hwa742.extif_clk_period, &max_clk_div);
743 for (div = 1; div < max_clk_div; div++) {
744 if (calc_reg_timing(sysclk, div) == 0)
747 if (div > max_clk_div)
750 *extif_mem_div = div;
752 for (div = 1; div < max_clk_div; div++) {
753 if (calc_lut_timing(sysclk, div) == 0)
757 if (div > max_clk_div)
763 dev_err(hwa742.fbdev->dev, "can't setup timings\n");
767 static void calc_hwa742_clk_rates(unsigned long ext_clk,
768 unsigned long *sys_clk, unsigned long *pix_clk)
771 int sys_div = 0, sys_mul = 0;
774 pix_clk_src = hwa742_read_reg(HWA742_CLK_SRC_REG);
775 pix_div = ((pix_clk_src >> 3) & 0x1f) + 1;
776 if ((pix_clk_src & (0x3 << 1)) == 0) {
777 /* Source is the PLL */
778 sys_div = (hwa742_read_reg(HWA742_PLL_DIV_REG) & 0x3f) + 1;
779 sys_mul = (hwa742_read_reg(HWA742_PLL_4_REG) & 0x7f) + 1;
780 *sys_clk = ext_clk * sys_mul / sys_div;
781 } else /* else source is ext clk, or oscillator */
784 *pix_clk = *sys_clk / pix_div; /* HZ */
785 dev_dbg(hwa742.fbdev->dev,
786 "ext_clk %ld pix_src %d pix_div %d sys_div %d sys_mul %d\n",
787 ext_clk, pix_clk_src & (0x3 << 1), pix_div, sys_div, sys_mul);
788 dev_dbg(hwa742.fbdev->dev, "sys_clk %ld pix_clk %ld\n",
793 static int setup_tearsync(unsigned long pix_clk, int extif_div)
799 int hs_pol_inv, vs_pol_inv;
800 int use_hsvs, use_ndp;
803 hsw = hwa742_read_reg(HWA742_HS_W_REG);
804 vsw = hwa742_read_reg(HWA742_VS_W_REG);
805 hs_pol_inv = !(hsw & 0x80);
806 vs_pol_inv = !(vsw & 0x80);
810 hdisp = (hwa742_read_reg(HWA742_H_DISP_REG) & 0x7f) * 8;
811 vdisp = hwa742_read_reg(HWA742_V_DISP_1_REG) +
812 ((hwa742_read_reg(HWA742_V_DISP_2_REG) & 0x3) << 8);
814 hndp = hwa742_read_reg(HWA742_H_NDP_REG) & 0x7f;
815 vndp = hwa742_read_reg(HWA742_V_NDP_REG);
817 /* time to transfer one pixel (16bpp) in ps */
818 hwa742.pix_tx_time = hwa742.reg_timings.we_cycle_time;
819 if (hwa742.extif->get_max_tx_rate != NULL) {
820 /* The external interface might have a rate limitation,
821 * if so, we have to maximize our transfer rate.
823 unsigned long min_tx_time;
824 unsigned long max_tx_rate = hwa742.extif->get_max_tx_rate();
826 dev_dbg(hwa742.fbdev->dev, "max_tx_rate %ld HZ\n",
828 min_tx_time = 1000000000 / (max_tx_rate / 1000); /* ps */
829 if (hwa742.pix_tx_time < min_tx_time)
830 hwa742.pix_tx_time = min_tx_time;
833 /* time to update one line in ps */
834 hwa742.line_upd_time = (hdisp + hndp) * 1000000 / (pix_clk / 1000);
835 hwa742.line_upd_time *= 1000;
836 if (hdisp * hwa742.pix_tx_time > hwa742.line_upd_time)
837 /* transfer speed too low, we might have to use both
841 /* decent transfer speed, we'll always use only VS */
844 if (use_hsvs && (hs_pol_inv || vs_pol_inv)) {
845 /* HS or'ed with VS doesn't work, use the active high
846 * TE signal based on HNDP / VNDP */
853 /* Use HS or'ed with VS as a TE signal if both are needed
854 * or VNDP if only vsync is needed. */
864 hs = hs * 1000000 / (pix_clk / 1000); /* ps */
867 vs = vs * (hdisp + hndp) * 1000000 / (pix_clk / 1000); /* ps */
872 /* set VS to 120% of HS to minimize VS detection time */
874 /* minimize HS too */
877 b = hwa742_read_reg(HWA742_NDP_CTRL);
879 b |= use_hsvs ? 1 : 0;
880 b |= (use_ndp && use_hsvs) ? 0 : 2;
881 hwa742_write_reg(HWA742_NDP_CTRL, b);
883 hwa742.vsync_only = !use_hsvs;
885 dev_dbg(hwa742.fbdev->dev,
886 "pix_clk %ld HZ pix_tx_time %ld ps line_upd_time %ld ps\n",
887 pix_clk, hwa742.pix_tx_time, hwa742.line_upd_time);
888 dev_dbg(hwa742.fbdev->dev,
889 "hs %d ps vs %d ps mode %d vsync_only %d\n",
890 hs, vs, (b & 0x3), !use_hsvs);
892 return hwa742.extif->setup_tearsync(1, hs, vs,
893 hs_pol_inv, vs_pol_inv, extif_div);
896 static unsigned long hwa742_get_caps(void)
900 caps = OMAPFB_CAPS_MANUAL_UPDATE;
901 if (hwa742.te_connected)
902 caps |= OMAPFB_CAPS_TEARSYNC;
906 static void hwa742_suspend(void)
908 hwa742.update_mode_before_suspend = hwa742.update_mode;
909 hwa742_set_update_mode(OMAPFB_UPDATE_DISABLED);
910 /* Enable sleep mode */
911 hwa742_write_reg(HWA742_POWER_SAVE, 1 << 1);
912 if (hwa742.power_down != NULL)
913 hwa742.power_down(hwa742.fbdev->dev);
916 static void hwa742_resume(void)
918 if (hwa742.power_up != NULL)
919 hwa742.power_up(hwa742.fbdev->dev);
920 /* Disable sleep mode */
921 hwa742_write_reg(HWA742_POWER_SAVE, 0);
923 /* Loop until PLL output is stabilized */
924 if (hwa742_read_reg(HWA742_PLL_DIV_REG) & (1 << 7))
926 set_current_state(TASK_UNINTERRUPTIBLE);
927 schedule_timeout(msecs_to_jiffies(5));
929 hwa742_set_update_mode(hwa742.update_mode_before_suspend);
932 static int hwa742_init(struct omapfb_device *fbdev, int ext_mode,
933 struct omapfb_mem_desc *req_vram)
937 unsigned long ext_clk;
938 unsigned long sys_clk, pix_clk;
940 struct omapfb_platform_data *omapfb_conf;
941 struct hwa742_platform_data *ctrl_conf;
943 BUG_ON(!fbdev->ext_if || !fbdev->int_ctrl);
945 hwa742.fbdev = fbdev;
946 hwa742.extif = fbdev->ext_if;
947 hwa742.int_ctrl = fbdev->int_ctrl;
949 omapfb_conf = fbdev->dev->platform_data;
950 ctrl_conf = omapfb_conf->ctrl_platform_data;
952 if (ctrl_conf == NULL || ctrl_conf->get_clock_rate == NULL) {
953 dev_err(fbdev->dev, "HWA742: missing platform data\n");
958 hwa742.power_down = ctrl_conf->power_down;
959 hwa742.power_up = ctrl_conf->power_up;
961 spin_lock_init(&hwa742.req_lock);
963 if ((r = hwa742.int_ctrl->init(fbdev, 1, req_vram)) < 0)
966 if ((r = hwa742.extif->init(fbdev)) < 0)
969 ext_clk = ctrl_conf->get_clock_rate(fbdev->dev);
970 if ((r = calc_extif_timings(ext_clk, &extif_mem_div)) < 0)
972 hwa742.extif->set_timings(&hwa742.reg_timings);
973 if (hwa742.power_up != NULL)
974 hwa742.power_up(fbdev->dev);
976 calc_hwa742_clk_rates(ext_clk, &sys_clk, &pix_clk);
977 if ((r = calc_extif_timings(sys_clk, &extif_mem_div)) < 0)
979 hwa742.extif->set_timings(&hwa742.reg_timings);
981 rev = hwa742_read_reg(HWA742_REV_CODE_REG);
982 if ((rev & 0xfc) != 0x80) {
983 dev_err(fbdev->dev, "HWA742: invalid revision %02x\n", rev);
989 if (!(hwa742_read_reg(HWA742_PLL_DIV_REG) & 0x80)) {
991 "HWA742: controller not initialized by the bootloader\n");
996 if (ctrl_conf->te_connected) {
997 if ((r = setup_tearsync(pix_clk, extif_mem_div)) < 0) {
998 dev_err(hwa742.fbdev->dev,
999 "HWA742: can't setup tearing synchronization\n");
1002 hwa742.te_connected = 1;
1005 hwa742.max_transmit_size = hwa742.extif->max_transmit_size;
1007 hwa742.update_mode = OMAPFB_UPDATE_DISABLED;
1009 hwa742.auto_update_window.x = 0;
1010 hwa742.auto_update_window.y = 0;
1011 hwa742.auto_update_window.width = fbdev->panel->x_res;
1012 hwa742.auto_update_window.height = fbdev->panel->y_res;
1013 hwa742.auto_update_window.format = 0;
1015 init_timer(&hwa742.auto_update_timer);
1016 hwa742.auto_update_timer.function = hwa742_update_window_auto;
1017 hwa742.auto_update_timer.data = 0;
1019 hwa742.prev_color_mode = -1;
1020 hwa742.prev_flags = 0;
1022 hwa742.fbdev = fbdev;
1024 INIT_LIST_HEAD(&hwa742.free_req_list);
1025 INIT_LIST_HEAD(&hwa742.pending_req_list);
1026 for (i = 0; i < ARRAY_SIZE(hwa742.req_pool); i++)
1027 list_add(&hwa742.req_pool[i].entry, &hwa742.free_req_list);
1028 BUG_ON(i <= IRQ_REQ_POOL_SIZE);
1029 sema_init(&hwa742.req_sema, i - IRQ_REQ_POOL_SIZE);
1031 conf = hwa742_read_reg(HWA742_CONFIG_REG);
1032 dev_info(fbdev->dev, ": Epson HWA742 LCD controller rev %d "
1033 "initialized (CNF pins %x)\n", rev & 0x03, conf & 0x07);
1037 if (hwa742.power_down != NULL)
1038 hwa742.power_down(fbdev->dev);
1040 hwa742.extif->cleanup();
1042 hwa742.int_ctrl->cleanup();
1047 static void hwa742_cleanup(void)
1049 hwa742_set_update_mode(OMAPFB_UPDATE_DISABLED);
1050 hwa742.extif->cleanup();
1051 hwa742.int_ctrl->cleanup();
1052 if (hwa742.power_down != NULL)
1053 hwa742.power_down(hwa742.fbdev->dev);
1056 struct lcd_ctrl hwa742_ctrl = {
1058 .init = hwa742_init,
1059 .cleanup = hwa742_cleanup,
1060 .bind_client = hwa742_bind_client,
1061 .get_caps = hwa742_get_caps,
1062 .set_update_mode = hwa742_set_update_mode,
1063 .get_update_mode = hwa742_get_update_mode,
1064 .setup_plane = hwa742_setup_plane,
1065 .enable_plane = hwa742_enable_plane,
1066 .update_window = hwa742_update_window_async,
1067 .sync = hwa742_sync,
1068 .suspend = hwa742_suspend,
1069 .resume = hwa742_resume,