drivers/video/omap/hwa742.c

   1 /*
   2  * File: drivers/video/omap/hwa742.c
   3  *
   4  * Epson HWA742 LCD controller driver
   5  *
   6  * Copyright (C) 2004-2005 Nokia Corporation
   7  * Authors:     Juha Yrjölä   <juha.yrjola@nokia.com>
   8  *              Imre Deak     <imre.deak@nokia.com>
   9  * YUV support: Jussi Laako   <jussi.laako@nokia.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify it
  12  * under the terms of the GNU General Public License as published by the
  13  * Free Software Foundation; either version 2 of the License, or (at your
  14  * option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  19  * General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License along
  22  * with this program; if not, write to the Free Software Foundation, Inc.,
  23  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  */
  25 #include <linux/module.h>
  26 #include <linux/mm.h>
  27 #include <linux/fb.h>
  28 #include <linux/delay.h>
  29 #include <linux/clk.h>
  30
  31 #include <asm/arch/dma.h>
  32 #include <asm/arch/omapfb.h>
  33 #include <asm/arch/hwa742.h>
  34
  35 #define HWA742_REV_CODE_REG       0x0
  36 #define HWA742_CONFIG_REG         0x2
  37 #define HWA742_PLL_DIV_REG        0x4
  38 #define HWA742_PLL_0_REG          0x6
  39 #define HWA742_PLL_1_REG          0x8
  40 #define HWA742_PLL_2_REG          0xa
  41 #define HWA742_PLL_3_REG          0xc
  42 #define HWA742_PLL_4_REG          0xe
  43 #define HWA742_CLK_SRC_REG        0x12
  44 #define HWA742_PANEL_TYPE_REG     0x14
  45 #define HWA742_H_DISP_REG         0x16
  46 #define HWA742_H_NDP_REG          0x18
  47 #define HWA742_V_DISP_1_REG       0x1a
  48 #define HWA742_V_DISP_2_REG       0x1c
  49 #define HWA742_V_NDP_REG          0x1e
  50 #define HWA742_HS_W_REG           0x20
  51 #define HWA742_HP_S_REG           0x22
  52 #define HWA742_VS_W_REG           0x24
  53 #define HWA742_VP_S_REG           0x26
  54 #define HWA742_PCLK_POL_REG       0x28
  55 #define HWA742_INPUT_MODE_REG     0x2a
  56 #define HWA742_TRANSL_MODE_REG1   0x2e
  57 #define HWA742_DISP_MODE_REG      0x34
  58 #define HWA742_WINDOW_TYPE        0x36
  59 #define HWA742_WINDOW_X_START_0   0x38
  60 #define HWA742_WINDOW_X_START_1   0x3a
  61 #define HWA742_WINDOW_Y_START_0   0x3c
  62 #define HWA742_WINDOW_Y_START_1   0x3e
  63 #define HWA742_WINDOW_X_END_0     0x40
  64 #define HWA742_WINDOW_X_END_1     0x42
  65 #define HWA742_WINDOW_Y_END_0     0x44
  66 #define HWA742_WINDOW_Y_END_1     0x46
  67 #define HWA742_MEMORY_WRITE_LSB   0x48
  68 #define HWA742_MEMORY_WRITE_MSB   0x49
  69 #define HWA742_MEMORY_READ_0      0x4a
  70 #define HWA742_MEMORY_READ_1      0x4c
  71 #define HWA742_MEMORY_READ_2      0x4e
  72 #define HWA742_POWER_SAVE         0x56
  73 #define HWA742_NDP_CTRL           0x58
  74
  75 #define HWA742_AUTO_UPDATE_TIME         (HZ / 20)
  76
  77 /* Reserve 4 request slots for requests in irq context */
  78 #define REQ_POOL_SIZE                   24
  79 #define IRQ_REQ_POOL_SIZE               4
  80
  81 #define REQ_FROM_IRQ_POOL 0x01
  82
  83 #define REQ_COMPLETE    0
  84 #define REQ_PENDING     1
  85
  86 struct update_param {
  87         int     x, y, width, height;
  88         int     color_mode;
  89         int     flags;
  90 };
  91
  92 struct hwa742_request {
  93         struct list_head entry;
  94         unsigned int     flags;
  95
  96         int              (*handler)(struct hwa742_request *req);
  97         void             (*complete)(void *data);
  98         void             *complete_data;
  99
 100         union {
 101                 struct update_param     update;
 102                 struct completion       *sync;
 103         } par;
 104 };
 105
 106 struct {
 107         enum omapfb_update_mode update_mode;
 108         enum omapfb_update_mode update_mode_before_suspend;
 109
 110         struct timer_list       auto_update_timer;
 111         int                     stop_auto_update;
 112         struct omapfb_update_window     auto_update_window;
 113         unsigned                te_connected:1;
 114         unsigned                vsync_only:1;
 115
 116         struct hwa742_request   req_pool[REQ_POOL_SIZE];
 117         struct list_head        pending_req_list;
 118         struct list_head        free_req_list;
 119         struct semaphore        req_sema;
 120         spinlock_t              req_lock;
 121
 122         struct extif_timings    reg_timings, lut_timings;
 123
 124         int                     prev_color_mode;
 125         int                     prev_flags;
 126         int                     window_type;
 127
 128         u32                     max_transmit_size;
 129         u32                     extif_clk_period;
 130         unsigned long           pix_tx_time;
 131         unsigned long           line_upd_time;
 132
 133
 134         struct omapfb_device    *fbdev;
 135         struct lcd_ctrl_extif   *extif;
 136         struct lcd_ctrl         *int_ctrl;
 137
 138         void                    (*power_up)(struct device *dev);
 139         void                    (*power_down)(struct device *dev);
 140 } hwa742;
 141
 142 struct lcd_ctrl hwa742_ctrl;
 143
 144 static u8 hwa742_read_reg(u8 reg)
 145 {
 146         u8 data;
 147
 148         hwa742.extif->set_bits_per_cycle(8);
 149         hwa742.extif->write_command(&reg, 1);
 150         hwa742.extif->read_data(&data, 1);
 151
 152         return data;
 153 }
 154
 155 static void hwa742_write_reg(u8 reg, u8 data)
 156 {
 157         hwa742.extif->set_bits_per_cycle(8);
 158         hwa742.extif->write_command(&reg, 1);
 159         hwa742.extif->write_data(&data, 1);
 160 }
 161
 162 static void set_window_regs(int x_start, int y_start, int x_end, int y_end)
 163 {
 164         u8 tmp[8];
 165         u8 cmd;
 166
 167         x_end--;
 168         y_end--;
 169         tmp[0] = x_start;
 170         tmp[1] = x_start >> 8;
 171         tmp[2] = y_start;
 172         tmp[3] = y_start >> 8;
 173         tmp[4] = x_end;
 174         tmp[5] = x_end >> 8;
 175         tmp[6] = y_end;
 176         tmp[7] = y_end >> 8;
 177
 178         hwa742.extif->set_bits_per_cycle(8);
 179         cmd = HWA742_WINDOW_X_START_0;
 180
 181         hwa742.extif->write_command(&cmd, 1);
 182
 183         hwa742.extif->write_data(tmp, 8);
 184 }
 185
 186 static void set_format_regs(int conv, int transl, int flags)
 187 {
 188         if (flags & OMAPFB_FORMAT_FLAG_DOUBLE) {
 189                 hwa742.window_type = ((hwa742.window_type & 0xfc) | 0x01);
 190 #ifdef VERBOSE
 191                 dev_dbg(hwa742.fbdev->dev, "hwa742: enabled pixel doubling\n");
 192 #endif
 193         } else {
 194                 hwa742.window_type = (hwa742.window_type & 0xfc);
 195 #ifdef VERBOSE
 196                 dev_dbg(hwa742.fbdev->dev, "hwa742: disabled pixel doubling\n");
 197 #endif
 198         }
 199
 200         hwa742_write_reg(HWA742_INPUT_MODE_REG, conv);
 201         hwa742_write_reg(HWA742_TRANSL_MODE_REG1, transl);
 202         hwa742_write_reg(HWA742_WINDOW_TYPE, hwa742.window_type);
 203 }
 204
 205 static void enable_tearsync(int y, int width, int height, int screen_height,
 206                             int force_vsync)
 207 {
 208         u8 b;
 209
 210         b = hwa742_read_reg(HWA742_NDP_CTRL);
 211         b |= 1 << 2;
 212         hwa742_write_reg(HWA742_NDP_CTRL, b);
 213
 214         if (likely(hwa742.vsync_only || force_vsync)) {
 215                 hwa742.extif->enable_tearsync(1, 0);
 216                 return;
 217         }
 218
 219         if (width * hwa742.pix_tx_time < hwa742.line_upd_time) {
 220                 hwa742.extif->enable_tearsync(1, 0);
 221                 return;
 222         }
 223
 224         if ((width * hwa742.pix_tx_time / 1000) * height <
 225             (y + height) * (hwa742.line_upd_time / 1000)) {
 226                 hwa742.extif->enable_tearsync(1, 0);
 227                 return;
 228         }
 229
 230         hwa742.extif->enable_tearsync(1, y + 1);
 231 }
 232
 233 static void disable_tearsync(void)
 234 {
 235         u8 b;
 236
 237         hwa742.extif->enable_tearsync(0, 0);
 238
 239         b = hwa742_read_reg(HWA742_NDP_CTRL);
 240         b &= ~(1 << 2);
 241         hwa742_write_reg(HWA742_NDP_CTRL, b);
 242 }
 243
 244 static inline struct hwa742_request *alloc_req(void)
 245 {
 246         unsigned long flags;
 247         struct hwa742_request *req;
 248         int req_flags = 0;
 249
 250         if (!in_interrupt())
 251                 down(&hwa742.req_sema);
 252         else
 253                 req_flags = REQ_FROM_IRQ_POOL;
 254
 255         spin_lock_irqsave(&hwa742.req_lock, flags);
 256         BUG_ON(list_empty(&hwa742.free_req_list));
 257         req = list_entry(hwa742.free_req_list.next,
 258                          struct hwa742_request, entry);
 259         list_del(&req->entry);
 260         spin_unlock_irqrestore(&hwa742.req_lock, flags);
 261
 262         INIT_LIST_HEAD(&req->entry);
 263         req->flags = req_flags;
 264
 265         return req;
 266 }
 267
 268 static inline void free_req(struct hwa742_request *req)
 269 {
 270         unsigned long flags;
 271
 272         spin_lock_irqsave(&hwa742.req_lock, flags);
 273
 274         list_del(&req->entry);
 275         list_add(&req->entry, &hwa742.free_req_list);
 276         if (!(req->flags & REQ_FROM_IRQ_POOL))
 277                 up(&hwa742.req_sema);
 278
 279         spin_unlock_irqrestore(&hwa742.req_lock, flags);
 280 }
 281
 282 static void process_pending_requests(void)
 283 {
 284         unsigned long flags;
 285
 286         spin_lock_irqsave(&hwa742.req_lock, flags);
 287
 288         while (!list_empty(&hwa742.pending_req_list)) {
 289                 struct hwa742_request *req;
 290                 void (*complete)(void *);
 291                 void *complete_data;
 292
 293                 req = list_entry(hwa742.pending_req_list.next,
 294                                  struct hwa742_request, entry);
 295                 spin_unlock_irqrestore(&hwa742.req_lock, flags);
 296
 297                 if (req->handler(req) == REQ_PENDING)
 298                         return;
 299
 300                 complete = req->complete;
 301                 complete_data = req->complete_data;
 302                 free_req(req);
 303
 304                 if (complete)
 305                         complete(complete_data);
 306
 307                 spin_lock_irqsave(&hwa742.req_lock, flags);
 308         }
 309
 310         spin_unlock_irqrestore(&hwa742.req_lock, flags);
 311 }
 312
 313 static void submit_req_list(struct list_head *head)
 314 {
 315         unsigned long flags;
 316         int process = 1;
 317
 318         spin_lock_irqsave(&hwa742.req_lock, flags);
 319         if (likely(!list_empty(&hwa742.pending_req_list)))
 320                 process = 0;
 321         list_splice_init(head, hwa742.pending_req_list.prev);
 322         spin_unlock_irqrestore(&hwa742.req_lock, flags);
 323
 324         if (process)
 325                 process_pending_requests();
 326 }
 327
 328 static void request_complete(void *data)
 329 {
 330         struct hwa742_request   *req = (struct hwa742_request *)data;
 331         void                    (*complete)(void *);
 332         void                    *complete_data;
 333
 334         complete = req->complete;
 335         complete_data = req->complete_data;
 336
 337         free_req(req);
 338
 339         if (complete)
 340                 complete(complete_data);
 341
 342         process_pending_requests();
 343 }
 344
 345 static int send_frame_handler(struct hwa742_request *req)
 346 {
 347         struct update_param *par = &req->par.update;
 348         int x = par->x;
 349         int y = par->y;
 350         int w = par->width;
 351         int h = par->height;
 352         int bpp;
 353         int conv, transl;
 354         unsigned long offset;
 355         int color_mode = par->color_mode;
 356         int flags = par->flags;
 357         int scr_width = hwa742.fbdev->panel->x_res;
 358         int scr_height = hwa742.fbdev->panel->y_res;
 359
 360 #ifdef VERBOSE
 361         dev_dbg(hwa742.fbdev->dev, "x %d y %d w %d h %d scr_width %d "
 362                 "color_mode %d flags %d\n",
 363                 x, y, w, h, scr_width, color_mode, flags);
 364 #endif
 365
 366         switch (color_mode) {
 367         case OMAPFB_COLOR_YUV422:
 368                 bpp = 16;
 369                 conv = 0x08;
 370                 transl = 0x25;
 371                 break;
 372         case OMAPFB_COLOR_YUV420:
 373                 bpp = 12;
 374                 conv = 0x09;
 375                 transl = 0x25;
 376                 break;
 377         case OMAPFB_COLOR_RGB565:
 378                 bpp = 16;
 379                 conv = 0x01;
 380                 transl = 0x05;
 381                 break;
 382         default:
 383                 return -EINVAL;
 384         }
 385
 386         if (hwa742.prev_flags != flags ||
 387             hwa742.prev_color_mode != color_mode) {
 388                 set_format_regs(conv, transl, flags);
 389                 hwa742.prev_color_mode = color_mode;
 390                 hwa742.prev_flags = flags;
 391         }
 392         flags = req->par.update.flags;
 393         if (flags & OMAPFB_FORMAT_FLAG_TEARSYNC)
 394                 enable_tearsync(y, scr_width, h, scr_height,
 395                                 flags & OMAPFB_FORMAT_FLAG_FORCE_VSYNC);
 396         else
 397                 disable_tearsync();
 398
 399         set_window_regs(x, y, x + w, y + h);
 400
 401         offset = (scr_width * y + x) * bpp / 8;
 402
 403         hwa742.int_ctrl->setup_plane(OMAPFB_PLANE_GFX,
 404                         OMAPFB_CHANNEL_OUT_LCD, offset, scr_width, 0, 0, w, h,
 405                         color_mode);
 406
 407         hwa742.extif->set_bits_per_cycle(16);
 408
 409         hwa742.int_ctrl->enable_plane(OMAPFB_PLANE_GFX, 1);
 410         hwa742.extif->transfer_area(w, h, request_complete, req);
 411
 412         return REQ_PENDING;
 413 }
 414
 415 static void send_frame_complete(void *data)
 416 {
 417         hwa742.int_ctrl->enable_plane(OMAPFB_PLANE_GFX, 0);
 418 }
 419
 420 #define ADD_PREQ(_x, _y, _w, _h) do {           \
 421         req = alloc_req();                      \
 422         req->handler    = send_frame_handler;   \
 423         req->complete   = send_frame_complete;  \
 424         req->par.update.x = _x;                 \
 425         req->par.update.y = _y;                 \
 426         req->par.update.width  = _w;            \
 427         req->par.update.height = _h;            \
 428         req->par.update.color_mode = color_mode;\
 429         req->par.update.flags     = flags;      \
 430         list_add_tail(&req->entry, req_head);   \
 431 } while(0)
 432
 433 static void create_req_list(struct omapfb_update_window *win,
 434                             struct list_head *req_head)
 435 {
 436         struct hwa742_request *req;
 437         int x = win->x;
 438         int y = win->y;
 439         int width = win->width;
 440         int height = win->height;
 441         int color_mode;
 442         int flags;
 443
 444         flags = win->format & ~OMAPFB_FORMAT_MASK;
 445         color_mode = win->format & OMAPFB_FORMAT_MASK;
 446
 447         if (x & 1) {
 448                 ADD_PREQ(x, y, 1, height);
 449                 width--;
 450                 x++;
 451                 flags &= ~OMAPFB_FORMAT_FLAG_TEARSYNC;
 452         }
 453         if (width & ~1) {
 454                 unsigned int xspan = width & ~1;
 455                 unsigned int ystart = y;
 456                 unsigned int yspan = height;
 457
 458                 if (xspan * height * 2 > hwa742.max_transmit_size) {
 459                         yspan = hwa742.max_transmit_size / (xspan * 2);
 460                         ADD_PREQ(x, ystart, xspan, yspan);
 461                         ystart += yspan;
 462                         yspan = height - yspan;
 463                         flags &= ~OMAPFB_FORMAT_FLAG_TEARSYNC;
 464                 }
 465
 466                 ADD_PREQ(x, ystart, xspan, yspan);
 467                 x += xspan;
 468                 width -= xspan;
 469                 flags &= ~OMAPFB_FORMAT_FLAG_TEARSYNC;
 470         }
 471         if (width)
 472                 ADD_PREQ(x, y, 1, height);
 473 }
 474
 475 static void auto_update_complete(void *data)
 476 {
 477         if (!hwa742.stop_auto_update)
 478                 mod_timer(&hwa742.auto_update_timer,
 479                           jiffies + HWA742_AUTO_UPDATE_TIME);
 480 }
 481
 482 static void hwa742_update_window_auto(unsigned long arg)
 483 {
 484         LIST_HEAD(req_list);
 485         struct hwa742_request *last;
 486
 487         create_req_list(&hwa742.auto_update_window, &req_list);
 488         last = list_entry(req_list.prev, struct hwa742_request, entry);
 489
 490         last->complete = auto_update_complete;
 491         last->complete_data = NULL;
 492
 493         submit_req_list(&req_list);
 494 }
 495
 496 int hwa742_update_window_async(struct fb_info *fbi,
 497                                  struct omapfb_update_window *win,
 498                                  void (*complete_callback)(void *arg),
 499                                  void *complete_callback_data)
 500 {
 501         LIST_HEAD(req_list);
 502         struct hwa742_request *last;
 503         int r = 0;
 504
 505         if (hwa742.update_mode != OMAPFB_MANUAL_UPDATE) {
 506                 dev_dbg(hwa742.fbdev->dev, "invalid update mode\n");
 507                 r = -EINVAL;
 508                 goto out;
 509         }
 510         if (unlikely(win->format &
 511             ~(0x03 | OMAPFB_FORMAT_FLAG_DOUBLE |
 512             OMAPFB_FORMAT_FLAG_TEARSYNC | OMAPFB_FORMAT_FLAG_FORCE_VSYNC))) {
 513                 dev_dbg(hwa742.fbdev->dev, "invalid window flag");
 514                 r = -EINVAL;
 515                 goto out;
 516         }
 517
 518         create_req_list(win, &req_list);
 519         last = list_entry(req_list.prev, struct hwa742_request, entry);
 520
 521         last->complete = complete_callback;
 522         last->complete_data = (void *)complete_callback_data;
 523
 524         submit_req_list(&req_list);
 525
 526 out:
 527         return r;
 528 }
 529 EXPORT_SYMBOL(hwa742_update_window_async);
 530
 531 static int hwa742_setup_plane(int plane, int channel_out,
 532                                   unsigned long offset, int screen_width,
 533                                   int pos_x, int pos_y, int width, int height,
 534                                   int color_mode)
 535 {
 536         if (plane != OMAPFB_PLANE_GFX ||
 537             channel_out != OMAPFB_CHANNEL_OUT_LCD)
 538                 return -EINVAL;
 539
 540         return 0;
 541 }
 542
 543 static int hwa742_enable_plane(int plane, int enable)
 544 {
 545         if (plane != 0)
 546                 return -EINVAL;
 547
 548         hwa742.int_ctrl->enable_plane(plane, enable);
 549
 550         return 0;
 551 }
 552
 553 static int sync_handler(struct hwa742_request *req)
 554 {
 555         complete(req->par.sync);
 556         return REQ_COMPLETE;
 557 }
 558
 559 static void hwa742_sync(void)
 560 {
 561         LIST_HEAD(req_list);
 562         struct hwa742_request *req;
 563         struct completion comp;
 564
 565         req = alloc_req();
 566
 567         req->handler = sync_handler;
 568         req->complete = NULL;
 569         init_completion(&comp);
 570         req->par.sync = &comp;
 571
 572         list_add(&req->entry, &req_list);
 573         submit_req_list(&req_list);
 574
 575         wait_for_completion(&comp);
 576 }
 577
 578 static void hwa742_bind_client(struct omapfb_notifier_block *nb)
 579 {
 580         dev_dbg(hwa742.fbdev->dev, "update_mode %d\n", hwa742.update_mode);
 581         if (hwa742.update_mode == OMAPFB_MANUAL_UPDATE) {
 582                 omapfb_notify_clients(hwa742.fbdev, OMAPFB_EVENT_READY);
 583         }
 584 }
 585
 586 static int hwa742_set_update_mode(enum omapfb_update_mode mode)
 587 {
 588         if (mode != OMAPFB_MANUAL_UPDATE && mode != OMAPFB_AUTO_UPDATE &&
 589             mode != OMAPFB_UPDATE_DISABLED)
 590                 return -EINVAL;
 591
 592         if (mode == hwa742.update_mode)
 593                 return 0;
 594
 595         dev_info(hwa742.fbdev->dev, "HWA742: setting update mode to %s\n",
 596                         mode == OMAPFB_UPDATE_DISABLED ? "disabled" :
 597                         (mode == OMAPFB_AUTO_UPDATE ? "auto" : "manual"));
 598
 599         switch (hwa742.update_mode) {
 600         case OMAPFB_MANUAL_UPDATE:
 601                 omapfb_notify_clients(hwa742.fbdev, OMAPFB_EVENT_DISABLED);
 602                 break;
 603         case OMAPFB_AUTO_UPDATE:
 604                 hwa742.stop_auto_update = 1;
 605                 del_timer_sync(&hwa742.auto_update_timer);
 606                 break;
 607         case OMAPFB_UPDATE_DISABLED:
 608                 break;
 609         }
 610
 611         hwa742.update_mode = mode;
 612         hwa742_sync();
 613         hwa742.stop_auto_update = 0;
 614
 615         switch (mode) {
 616         case OMAPFB_MANUAL_UPDATE:
 617                 omapfb_notify_clients(hwa742.fbdev, OMAPFB_EVENT_READY);
 618                 break;
 619         case OMAPFB_AUTO_UPDATE:
 620                 hwa742_update_window_auto(0);
 621                 break;
 622         case OMAPFB_UPDATE_DISABLED:
 623                 break;
 624         }
 625
 626         return 0;
 627 }
 628
 629 static enum omapfb_update_mode hwa742_get_update_mode(void)
 630 {
 631         return hwa742.update_mode;
 632 }
 633
 634 static unsigned long round_to_extif_ticks(unsigned long ps, int div)
 635 {
 636         int bus_tick = hwa742.extif_clk_period * div;
 637         return (ps + bus_tick - 1) / bus_tick * bus_tick;
 638 }
 639
 640 static int calc_reg_timing(unsigned long sysclk, int div)
 641 {
 642         struct extif_timings *t;
 643         unsigned long systim;
 644
 645         /* CSOnTime 0, WEOnTime 2 ns, REOnTime 2 ns,
 646          * AccessTime 2 ns + 12.2 ns (regs),
 647          * WEOffTime = WEOnTime + 1 ns,
 648          * REOffTime = REOnTime + 16 ns (regs),
 649          * CSOffTime = REOffTime + 1 ns
 650          * ReadCycle = 2ns + 2*SYSCLK  (regs),
 651          * WriteCycle = 2*SYSCLK + 2 ns,
 652          * CSPulseWidth = 10 ns */
 653         systim = 1000000000 / (sysclk / 1000);
 654         dev_dbg(hwa742.fbdev->dev, "HWA742 systim %lu ps extif_clk_period %u ps"
 655                   "extif_clk_div %d\n", systim, hwa742.extif_clk_period, div);
 656
 657         t = &hwa742.reg_timings;
 658         memset(t, 0, sizeof(*t));
 659         t->clk_div = div;
 660         t->cs_on_time = 0;
 661         t->we_on_time = round_to_extif_ticks(t->cs_on_time + 2000, div);
 662         t->re_on_time = round_to_extif_ticks(t->cs_on_time + 2000, div);
 663         t->access_time = round_to_extif_ticks(t->re_on_time + 12200, div);
 664         t->we_off_time = round_to_extif_ticks(t->we_on_time + 1000, div);
 665         t->re_off_time = round_to_extif_ticks(t->re_on_time + 16000, div);
 666         t->cs_off_time = round_to_extif_ticks(t->re_off_time + 1000, div);
 667         t->we_cycle_time = round_to_extif_ticks(2 * systim + 2000, div);
 668         if (t->we_cycle_time < t->we_off_time)
 669                 t->we_cycle_time = t->we_off_time;
 670         t->re_cycle_time = round_to_extif_ticks(2 * systim + 2000, div);
 671         if (t->re_cycle_time < t->re_off_time)
 672                 t->re_cycle_time = t->re_off_time;
 673         t->cs_pulse_width = 0;
 674
 675         dev_dbg(hwa742.fbdev->dev, "[reg]cson %d csoff %d reon %d reoff %d\n",
 676                  t->cs_on_time, t->cs_off_time, t->re_on_time, t->re_off_time);
 677         dev_dbg(hwa742.fbdev->dev, "[reg]weon %d weoff %d recyc %d wecyc %d\n",
 678                  t->we_on_time, t->we_off_time, t->re_cycle_time,
 679                  t->we_cycle_time);
 680         dev_dbg(hwa742.fbdev->dev, "[reg]rdaccess %d cspulse %d\n",
 681                  t->access_time, t->cs_pulse_width);
 682
 683         return hwa742.extif->convert_timings(t);
 684 }
 685
 686 static int calc_lut_timing(unsigned long sysclk, int div)
 687 {
 688         struct extif_timings *t;
 689         unsigned long systim;
 690
 691         /* CSOnTime 0, WEOnTime 2 ns, REOnTime 2 ns,
 692          * AccessTime 2 ns + 4 * SYSCLK + 26 (lut),
 693          * WEOffTime = WEOnTime + 1 ns,
 694          * REOffTime = REOnTime + 4*SYSCLK + 26 ns (lut),
 695          * CSOffTime = REOffTime + 1 ns
 696          * ReadCycle = 2ns + 4*SYSCLK + 26 ns (lut),
 697          * WriteCycle = 2*SYSCLK + 2 ns,
 698          * CSPulseWidth = 10 ns
 699          */
 700         systim = 1000000000 / (sysclk / 1000);
 701         dev_dbg(hwa742.fbdev->dev, "HWA742 systim %lu ps extif_clk_period %u ps"
 702                   "extif_clk_div %d\n", systim, hwa742.extif_clk_period, div);
 703
 704         t = &hwa742.lut_timings;
 705         memset(t, 0, sizeof(*t));
 706
 707         t->clk_div = div;
 708
 709         t->cs_on_time = 0;
 710         t->we_on_time = round_to_extif_ticks(t->cs_on_time + 2000, div);
 711         t->re_on_time = round_to_extif_ticks(t->cs_on_time + 2000, div);
 712         t->access_time = round_to_extif_ticks(t->re_on_time + 4 * systim +
 713                                               26000, div);
 714         t->we_off_time = round_to_extif_ticks(t->we_on_time + 1000, div);
 715         t->re_off_time = round_to_extif_ticks(t->re_on_time + 4 * systim +
 716                                               26000, div);
 717         t->cs_off_time = round_to_extif_ticks(t->re_off_time + 1000, div);
 718         t->we_cycle_time = round_to_extif_ticks(2 * systim + 2000, div);
 719         if (t->we_cycle_time < t->we_off_time)
 720                 t->we_cycle_time = t->we_off_time;
 721         t->re_cycle_time = round_to_extif_ticks(2000 + 4 * systim + 26000, div);
 722         if (t->re_cycle_time < t->re_off_time)
 723                 t->re_cycle_time = t->re_off_time;
 724         t->cs_pulse_width = 0;
 725
 726         dev_dbg(hwa742.fbdev->dev, "[lut]cson %d csoff %d reon %d reoff %d\n",
 727                  t->cs_on_time, t->cs_off_time, t->re_on_time, t->re_off_time);
 728         dev_dbg(hwa742.fbdev->dev, "[lut]weon %d weoff %d recyc %d wecyc %d\n",
 729                  t->we_on_time, t->we_off_time, t->re_cycle_time,
 730                  t->we_cycle_time);
 731         dev_dbg(hwa742.fbdev->dev, "[lut]rdaccess %d cspulse %d\n",
 732                  t->access_time, t->cs_pulse_width);
 733
 734         return hwa742.extif->convert_timings(t);
 735 }
 736
 737 static int calc_extif_timings(unsigned long sysclk, int *extif_mem_div)
 738 {
 739         int max_clk_div;
 740         int div;
 741
 742         hwa742.extif->get_clk_info(&hwa742.extif_clk_period, &max_clk_div);
 743         for (div = 1; div < max_clk_div; div++) {
 744                 if (calc_reg_timing(sysclk, div) == 0)
 745                         break;
 746         }
 747         if (div > max_clk_div)
 748                 goto err;
 749
 750         *extif_mem_div = div;
 751
 752         for (div = 1; div < max_clk_div; div++) {
 753                 if (calc_lut_timing(sysclk, div) == 0)
 754                         break;
 755         }
 756
 757         if (div > max_clk_div)
 758                 goto err;
 759
 760         return 0;
 761
 762 err:
 763         dev_err(hwa742.fbdev->dev, "can't setup timings\n");
 764         return -1;
 765 }
 766
 767 static void calc_hwa742_clk_rates(unsigned long ext_clk,
 768                                 unsigned long *sys_clk, unsigned long *pix_clk)
 769 {
 770         int pix_clk_src;
 771         int sys_div = 0, sys_mul = 0;
 772         int pix_div;
 773
 774         pix_clk_src = hwa742_read_reg(HWA742_CLK_SRC_REG);
 775         pix_div = ((pix_clk_src >> 3) & 0x1f) + 1;
 776         if ((pix_clk_src & (0x3 << 1)) == 0) {
 777                 /* Source is the PLL */
 778                 sys_div = (hwa742_read_reg(HWA742_PLL_DIV_REG) & 0x3f) + 1;
 779                 sys_mul = (hwa742_read_reg(HWA742_PLL_4_REG) & 0x7f) + 1;
 780                 *sys_clk = ext_clk * sys_mul / sys_div;
 781         } else  /* else source is ext clk, or oscillator */
 782                 *sys_clk = ext_clk;
 783
 784         *pix_clk = *sys_clk / pix_div;                  /* HZ */
 785         dev_dbg(hwa742.fbdev->dev,
 786                 "ext_clk %ld pix_src %d pix_div %d sys_div %d sys_mul %d\n",
 787                 ext_clk, pix_clk_src & (0x3 << 1), pix_div, sys_div, sys_mul);
 788         dev_dbg(hwa742.fbdev->dev, "sys_clk %ld pix_clk %ld\n",
 789                 *sys_clk, *pix_clk);
 790 }
 791
 792
 793 static int setup_tearsync(unsigned long pix_clk, int extif_div)
 794 {
 795         int hdisp, vdisp;
 796         int hndp, vndp;
 797         int hsw, vsw;
 798         int hs, vs;
 799         int hs_pol_inv, vs_pol_inv;
 800         int use_hsvs, use_ndp;
 801         u8  b;
 802
 803         hsw = hwa742_read_reg(HWA742_HS_W_REG);
 804         vsw = hwa742_read_reg(HWA742_VS_W_REG);
 805         hs_pol_inv = !(hsw & 0x80);
 806         vs_pol_inv = !(vsw & 0x80);
 807         hsw = hsw & 0x7f;
 808         vsw = vsw & 0x3f;
 809
 810         hdisp = (hwa742_read_reg(HWA742_H_DISP_REG) & 0x7f) * 8;
 811         vdisp = hwa742_read_reg(HWA742_V_DISP_1_REG) +
 812                 ((hwa742_read_reg(HWA742_V_DISP_2_REG) & 0x3) << 8);
 813
 814         hndp = hwa742_read_reg(HWA742_H_NDP_REG) & 0x7f;
 815         vndp = hwa742_read_reg(HWA742_V_NDP_REG);
 816
 817         /* time to transfer one pixel (16bpp) in ps */
 818         hwa742.pix_tx_time = hwa742.reg_timings.we_cycle_time;
 819         if (hwa742.extif->get_max_tx_rate != NULL) {
 820                 /* The external interface might have a rate limitation,
 821                  * if so, we have to maximize our transfer rate.
 822                  */
 823                 unsigned long min_tx_time;
 824                 unsigned long max_tx_rate = hwa742.extif->get_max_tx_rate();
 825
 826                 dev_dbg(hwa742.fbdev->dev, "max_tx_rate %ld HZ\n",
 827                         max_tx_rate);
 828                 min_tx_time = 1000000000 / (max_tx_rate / 1000);  /* ps */
 829                 if (hwa742.pix_tx_time < min_tx_time)
 830                         hwa742.pix_tx_time = min_tx_time;
 831         }
 832
 833         /* time to update one line in ps */
 834         hwa742.line_upd_time = (hdisp + hndp) * 1000000 / (pix_clk / 1000);
 835         hwa742.line_upd_time *= 1000;
 836         if (hdisp * hwa742.pix_tx_time > hwa742.line_upd_time)
 837                 /* transfer speed too low, we might have to use both
 838                  * HS and VS */
 839                 use_hsvs = 1;
 840         else
 841                 /* decent transfer speed, we'll always use only VS */
 842                 use_hsvs = 0;
 843
 844         if (use_hsvs && (hs_pol_inv || vs_pol_inv)) {
 845                 /* HS or'ed with VS doesn't work, use the active high
 846                  * TE signal based on HNDP / VNDP */
 847                 use_ndp = 1;
 848                 hs_pol_inv = 0;
 849                 vs_pol_inv = 0;
 850                 hs = hndp;
 851                 vs = vndp;
 852         } else {
 853                 /* Use HS or'ed with VS as a TE signal if both are needed
 854                  * or VNDP if only vsync is needed. */
 855                 use_ndp = 0;
 856                 hs = hsw;
 857                 vs = vsw;
 858                 if (!use_hsvs) {
 859                         hs_pol_inv = 0;
 860                         vs_pol_inv = 0;
 861                 }
 862         }
 863
 864         hs = hs * 1000000 / (pix_clk / 1000);                   /* ps */
 865         hs *= 1000;
 866
 867         vs = vs * (hdisp + hndp) * 1000000 / (pix_clk / 1000);  /* ps */
 868         vs *= 1000;
 869
 870         if (vs <= hs)
 871                 return -EDOM;
 872         /* set VS to 120% of HS to minimize VS detection time */
 873         vs = hs * 12 / 10;
 874         /* minimize HS too */
 875         hs = 10000;
 876
 877         b = hwa742_read_reg(HWA742_NDP_CTRL);
 878         b &= ~0x3;
 879         b |= use_hsvs ? 1 : 0;
 880         b |= (use_ndp && use_hsvs) ? 0 : 2;
 881         hwa742_write_reg(HWA742_NDP_CTRL, b);
 882
 883         hwa742.vsync_only = !use_hsvs;
 884
 885         dev_dbg(hwa742.fbdev->dev,
 886                 "pix_clk %ld HZ pix_tx_time %ld ps line_upd_time %ld ps\n",
 887                 pix_clk, hwa742.pix_tx_time, hwa742.line_upd_time);
 888         dev_dbg(hwa742.fbdev->dev,
 889                 "hs %d ps vs %d ps mode %d vsync_only %d\n",
 890                 hs, vs, (b & 0x3), !use_hsvs);
 891
 892         return hwa742.extif->setup_tearsync(1, hs, vs,
 893                                             hs_pol_inv, vs_pol_inv, extif_div);
 894 }
 895
 896 static void hwa742_get_caps(int plane, struct omapfb_caps *caps)
 897 {
 898         hwa742.int_ctrl->get_caps(plane, caps);
 899         caps->ctrl |= OMAPFB_CAPS_MANUAL_UPDATE |
 900                       OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE;
 901         if (hwa742.te_connected)
 902                 caps->ctrl |= OMAPFB_CAPS_TEARSYNC;
 903         caps->wnd_color |= (1 << OMAPFB_COLOR_RGB565) |
 904                            (1 << OMAPFB_COLOR_YUV420);
 905 }
 906
 907 static void hwa742_suspend(void)
 908 {
 909         hwa742.update_mode_before_suspend = hwa742.update_mode;
 910         hwa742_set_update_mode(OMAPFB_UPDATE_DISABLED);
 911         /* Enable sleep mode */
 912         hwa742_write_reg(HWA742_POWER_SAVE, 1 << 1);
 913         if (hwa742.power_down != NULL)
 914                 hwa742.power_down(hwa742.fbdev->dev);
 915 }
 916
 917 static void hwa742_resume(void)
 918 {
 919         if (hwa742.power_up != NULL)
 920                 hwa742.power_up(hwa742.fbdev->dev);
 921         /* Disable sleep mode */
 922         hwa742_write_reg(HWA742_POWER_SAVE, 0);
 923         while (1) {
 924                 /* Loop until PLL output is stabilized */
 925                 if (hwa742_read_reg(HWA742_PLL_DIV_REG) & (1 << 7))
 926                         break;
 927                 set_current_state(TASK_UNINTERRUPTIBLE);
 928                 schedule_timeout(msecs_to_jiffies(5));
 929         }
 930         hwa742_set_update_mode(hwa742.update_mode_before_suspend);
 931 }
 932
 933 static int hwa742_init(struct omapfb_device *fbdev, int ext_mode,
 934                        struct omapfb_mem_desc *req_vram)
 935 {
 936         int r = 0, i;
 937         u8 rev, conf;
 938         unsigned long ext_clk;
 939         unsigned long sys_clk, pix_clk;
 940         int extif_mem_div;
 941         struct omapfb_platform_data *omapfb_conf;
 942         struct hwa742_platform_data *ctrl_conf;
 943
 944         BUG_ON(!fbdev->ext_if || !fbdev->int_ctrl);
 945
 946         hwa742.fbdev = fbdev;
 947         hwa742.extif = fbdev->ext_if;
 948         hwa742.int_ctrl = fbdev->int_ctrl;
 949
 950         omapfb_conf = fbdev->dev->platform_data;
 951         ctrl_conf = omapfb_conf->ctrl_platform_data;
 952
 953         if (ctrl_conf == NULL || ctrl_conf->get_clock_rate == NULL) {
 954                 dev_err(fbdev->dev, "HWA742: missing platform data\n");
 955                 r = -ENOENT;
 956                 goto err1;
 957         }
 958
 959         hwa742.power_down = ctrl_conf->power_down;
 960         hwa742.power_up = ctrl_conf->power_up;
 961
 962         spin_lock_init(&hwa742.req_lock);
 963
 964         if ((r = hwa742.int_ctrl->init(fbdev, 1, req_vram)) < 0)
 965                 goto err1;
 966
 967         if ((r = hwa742.extif->init(fbdev)) < 0)
 968                 goto err2;
 969
 970         ext_clk = ctrl_conf->get_clock_rate(fbdev->dev);
 971         if ((r = calc_extif_timings(ext_clk, &extif_mem_div)) < 0)
 972                 goto err3;
 973         hwa742.extif->set_timings(&hwa742.reg_timings);
 974         if (hwa742.power_up != NULL)
 975                 hwa742.power_up(fbdev->dev);
 976
 977         calc_hwa742_clk_rates(ext_clk, &sys_clk, &pix_clk);
 978         if ((r = calc_extif_timings(sys_clk, &extif_mem_div)) < 0)
 979                 goto err4;
 980         hwa742.extif->set_timings(&hwa742.reg_timings);
 981
 982         rev = hwa742_read_reg(HWA742_REV_CODE_REG);
 983         if ((rev & 0xfc) != 0x80) {
 984                 dev_err(fbdev->dev, "HWA742: invalid revision %02x\n", rev);
 985                 r = -ENODEV;
 986                 goto err4;
 987         }
 988
 989
 990         if (!(hwa742_read_reg(HWA742_PLL_DIV_REG) & 0x80)) {
 991                 dev_err(fbdev->dev,
 992                       "HWA742: controller not initialized by the bootloader\n");
 993                 r = -ENODEV;
 994                 goto err4;
 995         }
 996
 997         if (ctrl_conf->te_connected) {
 998                 if ((r = setup_tearsync(pix_clk, extif_mem_div)) < 0) {
 999                         dev_err(hwa742.fbdev->dev,
1000                                "HWA742: can't setup tearing synchronization\n");
1001                         goto err4;
1002                 }
1003                 hwa742.te_connected = 1;
1004         }
1005
1006         hwa742.max_transmit_size = hwa742.extif->max_transmit_size;
1007
1008         hwa742.update_mode = OMAPFB_UPDATE_DISABLED;
1009
1010         hwa742.auto_update_window.x = 0;
1011         hwa742.auto_update_window.y = 0;
1012         hwa742.auto_update_window.width = fbdev->panel->x_res;
1013         hwa742.auto_update_window.height = fbdev->panel->y_res;
1014         hwa742.auto_update_window.format = 0;
1015
1016         init_timer(&hwa742.auto_update_timer);
1017         hwa742.auto_update_timer.function = hwa742_update_window_auto;
1018         hwa742.auto_update_timer.data = 0;
1019
1020         hwa742.prev_color_mode = -1;
1021         hwa742.prev_flags = 0;
1022
1023         hwa742.fbdev = fbdev;
1024
1025         INIT_LIST_HEAD(&hwa742.free_req_list);
1026         INIT_LIST_HEAD(&hwa742.pending_req_list);
1027         for (i = 0; i < ARRAY_SIZE(hwa742.req_pool); i++)
1028                 list_add(&hwa742.req_pool[i].entry, &hwa742.free_req_list);
1029         BUG_ON(i <= IRQ_REQ_POOL_SIZE);
1030         sema_init(&hwa742.req_sema, i - IRQ_REQ_POOL_SIZE);
1031
1032         conf = hwa742_read_reg(HWA742_CONFIG_REG);
1033         dev_info(fbdev->dev, ": Epson HWA742 LCD controller rev %d "
1034                         "initialized (CNF pins %x)\n", rev & 0x03, conf & 0x07);
1035
1036         return 0;
1037 err4:
1038         if (hwa742.power_down != NULL)
1039                 hwa742.power_down(fbdev->dev);
1040 err3:
1041         hwa742.extif->cleanup();
1042 err2:
1043         hwa742.int_ctrl->cleanup();
1044 err1:
1045         return r;
1046 }
1047
1048 static void hwa742_cleanup(void)
1049 {
1050         hwa742_set_update_mode(OMAPFB_UPDATE_DISABLED);
1051         hwa742.extif->cleanup();
1052         hwa742.int_ctrl->cleanup();
1053         if (hwa742.power_down != NULL)
1054                 hwa742.power_down(hwa742.fbdev->dev);
1055 }
1056
1057 struct lcd_ctrl hwa742_ctrl = {
1058         .name                   = "hwa742",
1059         .init                   = hwa742_init,
1060         .cleanup                = hwa742_cleanup,
1061         .bind_client            = hwa742_bind_client,
1062         .get_caps               = hwa742_get_caps,
1063         .set_update_mode        = hwa742_set_update_mode,
1064         .get_update_mode        = hwa742_get_update_mode,
1065         .setup_plane            = hwa742_setup_plane,
1066         .enable_plane           = hwa742_enable_plane,
1067         .update_window          = hwa742_update_window_async,
1068         .sync                   = hwa742_sync,
1069         .suspend                = hwa742_suspend,
1070         .resume                 = hwa742_resume,
1071 };
1072