drivers/video/omap/dispc.c

   1 /*
   2  * File: drivers/video/omap/omap2/dispc.c
   3  *
   4  * OMAP2 display controller support
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * Author: Imre Deak <imre.deak@nokia.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of the GNU General Public License as published by the
  11  * Free Software Foundation; either version 2 of the License, or (at your
  12  * option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along
  20  * with this program; if not, write to the Free Software Foundation, Inc.,
  21  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  22  */
  23 #include <linux/kernel.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/vmalloc.h>
  26 #include <linux/clk.h>
  27
  28 #include <asm/io.h>
  29
  30 #include <asm/arch/sram.h>
  31 #include <asm/arch/omapfb.h>
  32 #include <asm/arch/board.h>
  33
  34 #include "dispc.h"
  35
  36 #define MODULE_NAME                     "dispc"
  37
  38 #define DSS_BASE                        0x48050000
  39 #define DSS_SYSCONFIG                   0x0010
  40
  41 #define DISPC_BASE                      0x48050400
  42
  43 /* DISPC common */
  44 #define DISPC_REVISION                  0x0000
  45 #define DISPC_SYSCONFIG                 0x0010
  46 #define DISPC_SYSSTATUS                 0x0014
  47 #define DISPC_IRQSTATUS                 0x0018
  48 #define DISPC_IRQENABLE                 0x001C
  49 #define DISPC_CONTROL                   0x0040
  50 #define DISPC_CONFIG                    0x0044
  51 #define DISPC_CAPABLE                   0x0048
  52 #define DISPC_DEFAULT_COLOR0            0x004C
  53 #define DISPC_DEFAULT_COLOR1            0x0050
  54 #define DISPC_TRANS_COLOR0              0x0054
  55 #define DISPC_TRANS_COLOR1              0x0058
  56 #define DISPC_LINE_STATUS               0x005C
  57 #define DISPC_LINE_NUMBER               0x0060
  58 #define DISPC_TIMING_H                  0x0064
  59 #define DISPC_TIMING_V                  0x0068
  60 #define DISPC_POL_FREQ                  0x006C
  61 #define DISPC_DIVISOR                   0x0070
  62 #define DISPC_SIZE_DIG                  0x0078
  63 #define DISPC_SIZE_LCD                  0x007C
  64
  65 #define DISPC_DATA_CYCLE1               0x01D4
  66 #define DISPC_DATA_CYCLE2               0x01D8
  67 #define DISPC_DATA_CYCLE3               0x01DC
  68
  69 /* DISPC GFX plane */
  70 #define DISPC_GFX_BA0                   0x0080
  71 #define DISPC_GFX_BA1                   0x0084
  72 #define DISPC_GFX_POSITION              0x0088
  73 #define DISPC_GFX_SIZE                  0x008C
  74 #define DISPC_GFX_ATTRIBUTES            0x00A0
  75 #define DISPC_GFX_FIFO_THRESHOLD        0x00A4
  76 #define DISPC_GFX_FIFO_SIZE_STATUS      0x00A8
  77 #define DISPC_GFX_ROW_INC               0x00AC
  78 #define DISPC_GFX_PIXEL_INC             0x00B0
  79 #define DISPC_GFX_WINDOW_SKIP           0x00B4
  80 #define DISPC_GFX_TABLE_BA              0x00B8
  81
  82 /* DISPC Video plane 1/2 */
  83 #define DISPC_VID1_BASE                 0x00BC
  84 #define DISPC_VID2_BASE                 0x014C
  85
  86 /* Offsets into DISPC_VID1/2_BASE */
  87 #define DISPC_VID_BA0                   0x0000
  88 #define DISPC_VID_BA1                   0x0004
  89 #define DISPC_VID_POSITION              0x0008
  90 #define DISPC_VID_SIZE                  0x000C
  91 #define DISPC_VID_ATTRIBUTES            0x0010
  92 #define DISPC_VID_FIFO_THRESHOLD        0x0014
  93 #define DISPC_VID_FIFO_SIZE_STATUS      0x0018
  94 #define DISPC_VID_ROW_INC               0x001C
  95 #define DISPC_VID_PIXEL_INC             0x0020
  96 #define DISPC_VID_FIR                   0x0024
  97 #define DISPC_VID_PICTURE_SIZE          0x0028
  98 #define DISPC_VID_ACCU0                 0x002C
  99 #define DISPC_VID_ACCU1                 0x0030
 100
 101 /* 8 elements in 8 byte increments */
 102 #define DISPC_VID_FIR_COEF_H0           0x0034
 103 /* 8 elements in 8 byte increments */
 104 #define DISPC_VID_FIR_COEF_HV0          0x0038
 105 /* 5 elements in 4 byte increments */
 106 #define DISPC_VID_CONV_COEF0            0x0074
 107
 108 #define DISPC_IRQ_FRAMEMASK             0x0001
 109 #define DISPC_IRQ_VSYNC                 0x0002
 110 #define DISPC_IRQ_EVSYNC_EVEN           0x0004
 111 #define DISPC_IRQ_EVSYNC_ODD            0x0008
 112 #define DISPC_IRQ_ACBIAS_COUNT_STAT     0x0010
 113 #define DISPC_IRQ_PROG_LINE_NUM         0x0020
 114 #define DISPC_IRQ_GFX_FIFO_UNDERFLOW    0x0040
 115 #define DISPC_IRQ_GFX_END_WIN           0x0080
 116 #define DISPC_IRQ_PAL_GAMMA_MASK        0x0100
 117 #define DISPC_IRQ_OCP_ERR               0x0200
 118 #define DISPC_IRQ_VID1_FIFO_UNDERFLOW   0x0400
 119 #define DISPC_IRQ_VID1_END_WIN          0x0800
 120 #define DISPC_IRQ_VID2_FIFO_UNDERFLOW   0x1000
 121 #define DISPC_IRQ_VID2_END_WIN          0x2000
 122 #define DISPC_IRQ_SYNC_LOST             0x4000
 123
 124 #define DISPC_IRQ_MASK_ALL              0x7fff
 125
 126 #define DISPC_IRQ_MASK_ERROR            (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
 127                                              DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
 128                                              DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
 129                                              DISPC_IRQ_SYNC_LOST)
 130
 131 #define RFBI_CONTROL                    0x48050040
 132
 133 #define MAX_PALETTE_SIZE                (256 * 16)
 134
 135 #define FLD_MASK(pos, len)      (((1 << len) - 1) << pos)
 136
 137 #define MOD_REG_FLD(reg, mask, val) \
 138         dispc_write_reg((reg), (dispc_read_reg(reg) & ~(mask)) | (val));
 139
 140 static struct {
 141         u32             base;
 142
 143         struct omapfb_mem_desc  mem_desc;
 144
 145         dma_addr_t      palette_paddr;
 146         void            *palette_vaddr;
 147
 148         int             ext_mode;
 149         int             fbmem_allocated;
 150
 151         unsigned long   enabled_irqs;
 152         void            (*irq_callback)(void *);
 153         void            *irq_callback_data;
 154         struct completion       frame_done;
 155
 156         int             fir_hinc[OMAPFB_PLANE_NUM];
 157         int             fir_vinc[OMAPFB_PLANE_NUM];
 158
 159         struct clk      *dss_ick, *dss1_fck;
 160         struct clk      *dss_54m_fck;
 161
 162         enum omapfb_update_mode update_mode;
 163         struct omapfb_device    *fbdev;
 164
 165         struct omapfb_color_key color_key;
 166 } dispc;
 167
 168 static void enable_lcd_clocks(int enable);
 169
 170 static void inline dispc_write_reg(int idx, u32 val)
 171 {
 172         __raw_writel(val, dispc.base + idx);
 173 }
 174
 175 static u32 inline dispc_read_reg(int idx)
 176 {
 177         u32 l = __raw_readl(dispc.base + idx);
 178         return l;
 179 }
 180
 181 /* Select RFBI or bypass mode */
 182 static void enable_rfbi_mode(int enable)
 183 {
 184         u32 l;
 185
 186         l = dispc_read_reg(DISPC_CONTROL);
 187         /* Enable RFBI, GPIO0/1 */
 188         l &= ~((1 << 11) | (1 << 15) | (1 << 16));
 189         l |= enable ? (1 << 11) : 0;
 190         /* RFBI En: GPIO0/1=10  RFBI Dis: GPIO0/1=11 */
 191         l |= 1 << 15;
 192         l |= enable ? 0 : (1 << 16);
 193         dispc_write_reg(DISPC_CONTROL, l);
 194
 195         /* Set bypass mode in RFBI module */
 196         l = __raw_readl(io_p2v(RFBI_CONTROL));
 197         l |= enable ? 0 : (1 << 1);
 198         __raw_writel(l, io_p2v(RFBI_CONTROL));
 199 }
 200
 201 static void set_lcd_data_lines(int data_lines)
 202 {
 203         u32 l;
 204         int code = 0;
 205
 206         switch (data_lines) {
 207         case 12:
 208                 code = 0;
 209                 break;
 210         case 16:
 211                 code = 1;
 212                 break;
 213         case 18:
 214                 code = 2;
 215                 break;
 216         case 24:
 217                 code = 3;
 218                 break;
 219         default:
 220                 BUG();
 221         }
 222
 223         l = dispc_read_reg(DISPC_CONTROL);
 224         l &= ~(0x03 << 8);
 225         l |= code << 8;
 226         dispc_write_reg(DISPC_CONTROL, l);
 227 }
 228
 229 static void set_load_mode(int mode)
 230 {
 231         BUG_ON(mode & ~(DISPC_LOAD_CLUT_ONLY | DISPC_LOAD_FRAME_ONLY |
 232                         DISPC_LOAD_CLUT_ONCE_FRAME));
 233         MOD_REG_FLD(DISPC_CONFIG, 0x03 << 1, mode << 1);
 234 }
 235
 236 void omap_dispc_set_lcd_size(int x, int y)
 237 {
 238         BUG_ON((x > (1 << 11)) || (y > (1 << 11)));
 239         enable_lcd_clocks(1);
 240         MOD_REG_FLD(DISPC_SIZE_LCD, FLD_MASK(16, 11) | FLD_MASK(0, 11),
 241                         ((y - 1) << 16) | (x - 1));
 242         enable_lcd_clocks(0);
 243 }
 244 EXPORT_SYMBOL(omap_dispc_set_lcd_size);
 245
 246 void omap_dispc_set_digit_size(int x, int y)
 247 {
 248         BUG_ON((x > (1 << 11)) || (y > (1 << 11)));
 249         enable_lcd_clocks(1);
 250         MOD_REG_FLD(DISPC_SIZE_DIG, FLD_MASK(16, 11) | FLD_MASK(0, 11),
 251                         ((y - 1) << 16) | (x - 1));
 252         enable_lcd_clocks(0);
 253 }
 254 EXPORT_SYMBOL(omap_dispc_set_digit_size);
 255
 256 static void setup_plane_fifo(int plane, int ext_mode)
 257 {
 258         const u32 ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
 259                                 DISPC_VID1_BASE + DISPC_VID_FIFO_THRESHOLD,
 260                                 DISPC_VID2_BASE + DISPC_VID_FIFO_THRESHOLD };
 261         const u32 fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
 262                                 DISPC_VID1_BASE + DISPC_VID_FIFO_SIZE_STATUS,
 263                                 DISPC_VID2_BASE + DISPC_VID_FIFO_SIZE_STATUS };
 264         int low, high;
 265         u32 l;
 266
 267         BUG_ON(plane > 2);
 268
 269         l = dispc_read_reg(fsz_reg[plane]);
 270         l &= FLD_MASK(0, 9);
 271         if (ext_mode) {
 272                 low = l * 3 / 4;
 273                 high = l;
 274         } else {
 275                 low = l / 4;
 276                 high = l * 3 / 4;
 277         }
 278         MOD_REG_FLD(ftrs_reg[plane], FLD_MASK(16, 9) | FLD_MASK(0, 9),
 279                         (high << 16) | low);
 280 }
 281
 282 void omap_dispc_enable_lcd_out(int enable)
 283 {
 284         enable_lcd_clocks(1);
 285         MOD_REG_FLD(DISPC_CONTROL, 1, enable ? 1 : 0);
 286         enable_lcd_clocks(0);
 287 }
 288 EXPORT_SYMBOL(omap_dispc_enable_lcd_out);
 289
 290 void omap_dispc_enable_digit_out(int enable)
 291 {
 292         enable_lcd_clocks(1);
 293         MOD_REG_FLD(DISPC_CONTROL, 1 << 1, enable ? 1 << 1 : 0);
 294         enable_lcd_clocks(0);
 295 }
 296 EXPORT_SYMBOL(omap_dispc_enable_digit_out);
 297
 298 static inline int _setup_plane(int plane, int channel_out,
 299                                   u32 paddr, int screen_width,
 300                                   int pos_x, int pos_y, int width, int height,
 301                                   int color_mode)
 302 {
 303         const u32 at_reg[] = { DISPC_GFX_ATTRIBUTES,
 304                                 DISPC_VID1_BASE + DISPC_VID_ATTRIBUTES,
 305                                 DISPC_VID2_BASE + DISPC_VID_ATTRIBUTES };
 306         const u32 ba_reg[] = { DISPC_GFX_BA0, DISPC_VID1_BASE + DISPC_VID_BA0,
 307                                 DISPC_VID2_BASE + DISPC_VID_BA0 };
 308         const u32 ps_reg[] = { DISPC_GFX_POSITION,
 309                                 DISPC_VID1_BASE + DISPC_VID_POSITION,
 310                                 DISPC_VID2_BASE + DISPC_VID_POSITION };
 311         const u32 sz_reg[] = { DISPC_GFX_SIZE,
 312                                 DISPC_VID1_BASE + DISPC_VID_PICTURE_SIZE,
 313                                 DISPC_VID2_BASE + DISPC_VID_PICTURE_SIZE };
 314         const u32 ri_reg[] = { DISPC_GFX_ROW_INC,
 315                                 DISPC_VID1_BASE + DISPC_VID_ROW_INC,
 316                                 DISPC_VID2_BASE + DISPC_VID_ROW_INC };
 317         const u32 vs_reg[]= { 0, DISPC_VID1_BASE + DISPC_VID_SIZE,
 318                                 DISPC_VID2_BASE + DISPC_VID_SIZE };
 319
 320         int chout_shift, burst_shift;
 321         int chout_val;
 322         int color_code;
 323         int bpp;
 324         int cconv_en;
 325         int set_vsize;
 326         u32 l;
 327
 328 #ifdef VERBOSE
 329         dev_dbg(dispc.fbdev->dev, "plane %d channel %d paddr %#08x scr_width %d "
 330                     "pos_x %d pos_y %d width %d height %d color_mode %d\n",
 331                     plane, channel_out, paddr, screen_width, pos_x, pos_y,
 332                     width, height, color_mode);
 333 #endif
 334
 335         set_vsize = 0;
 336         switch (plane) {
 337         case OMAPFB_PLANE_GFX:
 338                 burst_shift = 6;
 339                 chout_shift = 8;
 340                 break;
 341         case OMAPFB_PLANE_VID1:
 342         case OMAPFB_PLANE_VID2:
 343                 burst_shift = 14;
 344                 chout_shift = 16;
 345                 set_vsize = 1;
 346                 break;
 347         default:
 348                 return -EINVAL;
 349         }
 350
 351         switch (channel_out) {
 352         case OMAPFB_CHANNEL_OUT_LCD:
 353                 chout_val = 0;
 354                 break;
 355         case OMAPFB_CHANNEL_OUT_DIGIT:
 356                 chout_val = 1;
 357                 break;
 358         default:
 359                 return -EINVAL;
 360         }
 361
 362         cconv_en = 0;
 363         switch (color_mode) {
 364         case OMAPFB_COLOR_RGB565:
 365                 color_code = DISPC_RGB_16_BPP;
 366                 bpp = 16;
 367                 break;
 368         case OMAPFB_COLOR_YUV422:
 369                 if (plane == 0)
 370                         return -EINVAL;
 371                 color_code = DISPC_UYVY_422;
 372                 cconv_en = 1;
 373                 bpp = 16;
 374                 break;
 375         case OMAPFB_COLOR_YUY422:
 376                 if (plane == 0)
 377                         return -EINVAL;
 378                 color_code = DISPC_YUV2_422;
 379                 cconv_en = 1;
 380                 bpp = 16;
 381                 break;
 382         default:
 383                 return -EINVAL;
 384         }
 385
 386         l = dispc_read_reg(at_reg[plane]);
 387
 388         l &= ~(0x0f << 1);
 389         l |= color_code << 1;
 390         l &= ~(1 << 9);
 391         l |= cconv_en << 9;
 392
 393         l &= ~(0x03 << burst_shift);
 394         l |= DISPC_BURST_8x32 << burst_shift;
 395
 396         l &= ~(1 << chout_shift);
 397         l |= chout_val << chout_shift;
 398
 399         dispc_write_reg(at_reg[plane], l);
 400
 401         dispc_write_reg(ba_reg[plane], paddr);
 402         MOD_REG_FLD(ps_reg[plane],
 403                     FLD_MASK(16, 11) | FLD_MASK(0, 11), (pos_y << 16) | pos_x);
 404
 405         MOD_REG_FLD(sz_reg[plane], FLD_MASK(16, 11) | FLD_MASK(0, 11),
 406                         ((height - 1) << 16) | (width - 1));
 407
 408         if (set_vsize) {
 409                 /* Set video size if set_scale hasn't set it */
 410                 if (!dispc.fir_vinc[plane])
 411                         MOD_REG_FLD(vs_reg[plane],
 412                                 FLD_MASK(16, 11), (height - 1) << 16);
 413                 if (!dispc.fir_hinc[plane])
 414                         MOD_REG_FLD(vs_reg[plane],
 415                                 FLD_MASK(0, 11), width - 1);
 416         }
 417
 418         dispc_write_reg(ri_reg[plane], (screen_width - width) * bpp / 8 + 1);
 419
 420         return height * screen_width * bpp / 8;
 421 }
 422
 423 static int omap_dispc_setup_plane(int plane, int channel_out,
 424                                   unsigned long offset,
 425                                   int screen_width,
 426                                   int pos_x, int pos_y, int width, int height,
 427                                   int color_mode)
 428 {
 429         u32 paddr;
 430         int r;
 431
 432         if ((unsigned)plane > dispc.mem_desc.region_cnt)
 433                 return -EINVAL;
 434         paddr = dispc.mem_desc.region[plane].paddr + offset;
 435         enable_lcd_clocks(1);
 436         r = _setup_plane(plane, channel_out, paddr,
 437                         screen_width,
 438                         pos_x, pos_y, width, height, color_mode);
 439         enable_lcd_clocks(0);
 440         return r;
 441 }
 442
 443 static void write_firh_reg(int plane, int reg, u32 value)
 444 {
 445         u32 base;
 446
 447         if (plane == 1)
 448                 base = DISPC_VID1_BASE + DISPC_VID_FIR_COEF_H0;
 449         else
 450                 base = DISPC_VID2_BASE + DISPC_VID_FIR_COEF_H0;
 451         dispc_write_reg(base + reg * 8, value);
 452 }
 453
 454 static void write_firhv_reg(int plane, int reg, u32 value)
 455 {
 456         u32 base;
 457
 458         if (plane == 1)
 459                 base = DISPC_VID1_BASE + DISPC_VID_FIR_COEF_HV0;
 460         else
 461                 base = DISPC_VID2_BASE + DISPC_VID_FIR_COEF_HV0;
 462         dispc_write_reg(base + reg * 8, value);
 463 }
 464
 465 static void set_upsampling_coef_table(int plane)
 466 {
 467         const u32 coef[][2] = {
 468                 { 0x00800000, 0x00800000 },
 469                 { 0x0D7CF800, 0x037B02FF },
 470                 { 0x1E70F5FF, 0x0C6F05FE },
 471                 { 0x335FF5FE, 0x205907FB },
 472                 { 0xF74949F7, 0x00404000 },
 473                 { 0xF55F33FB, 0x075920FE },
 474                 { 0xF5701EFE, 0x056F0CFF },
 475                 { 0xF87C0DFF, 0x027B0300 },
 476         };
 477         int i;
 478
 479         for (i = 0; i < 8; i++) {
 480                 write_firh_reg(plane, i, coef[i][0]);
 481                 write_firhv_reg(plane, i, coef[i][1]);
 482         }
 483 }
 484
 485 static int omap_dispc_set_scale(int plane,
 486                                 int orig_width, int orig_height,
 487                                 int out_width, int out_height)
 488 {
 489         const u32 at_reg[]  = { 0, DISPC_VID1_BASE + DISPC_VID_ATTRIBUTES,
 490                                    DISPC_VID2_BASE + DISPC_VID_ATTRIBUTES };
 491         const u32 vs_reg[]  = { 0, DISPC_VID1_BASE + DISPC_VID_SIZE,
 492                                    DISPC_VID2_BASE + DISPC_VID_SIZE };
 493         const u32 fir_reg[] = { 0, DISPC_VID1_BASE + DISPC_VID_FIR,
 494                                    DISPC_VID2_BASE + DISPC_VID_FIR };
 495
 496         u32 l;
 497         int fir_hinc;
 498         int fir_vinc;
 499
 500         if ((unsigned)plane > OMAPFB_PLANE_NUM)
 501                 return -ENODEV;
 502
 503         if (plane == OMAPFB_PLANE_GFX &&
 504             (out_width != orig_width || out_height != orig_height))
 505                 return -EINVAL;
 506
 507         enable_lcd_clocks(1);
 508         if (orig_width < out_width) {
 509                 /* Upsampling.
 510                  * Currently you can only scale both dimensions in one way.
 511                  */
 512                 if (orig_height > out_height ||
 513                     orig_width * 8 < out_width ||
 514                     orig_height * 8 < out_height) {
 515                         enable_lcd_clocks(0);
 516                         return -EINVAL;
 517                 }
 518                 set_upsampling_coef_table(plane);
 519         } else if (orig_width > out_width) {
 520                 /* Downsampling not yet supported
 521                 */
 522
 523                 enable_lcd_clocks(0);
 524                 return -EINVAL;
 525         }
 526         if (!orig_width || orig_width == out_width)
 527                 fir_hinc = 0;
 528         else
 529                 fir_hinc = 1024 * orig_width / out_width;
 530         if (!orig_height || orig_height == out_height)
 531                 fir_vinc = 0;
 532         else
 533                 fir_vinc = 1024 * orig_height / out_height;
 534         dispc.fir_hinc[plane] = fir_hinc;
 535         dispc.fir_vinc[plane] = fir_vinc;
 536
 537         MOD_REG_FLD(fir_reg[plane],
 538                     FLD_MASK(16, 12) | FLD_MASK(0, 12),
 539                     ((fir_vinc & 4095) << 16) |
 540                     (fir_hinc & 4095));
 541
 542         dev_dbg(dispc.fbdev->dev, "out_width %d out_height %d orig_width %d "
 543                 "orig_height %d fir_hinc  %d fir_vinc %d\n",
 544                 out_width, out_height, orig_width, orig_height,
 545                 fir_hinc, fir_vinc);
 546
 547         MOD_REG_FLD(vs_reg[plane],
 548                     FLD_MASK(16, 11) | FLD_MASK(0, 11),
 549                     ((out_height - 1) << 16) | (out_width - 1));
 550
 551         l = dispc_read_reg(at_reg[plane]);
 552         l &= ~(0x03 << 5);
 553         l |= fir_hinc ? (1 << 5) : 0;
 554         l |= fir_vinc ? (1 << 6) : 0;
 555         dispc_write_reg(at_reg[plane], l);
 556
 557         enable_lcd_clocks(0);
 558         return 0;
 559 }
 560
 561 static int omap_dispc_enable_plane(int plane, int enable)
 562 {
 563         const u32 at_reg[] = { DISPC_GFX_ATTRIBUTES,
 564                                 DISPC_VID1_BASE + DISPC_VID_ATTRIBUTES,
 565                                 DISPC_VID2_BASE + DISPC_VID_ATTRIBUTES };
 566         if ((unsigned int)plane > dispc.mem_desc.region_cnt)
 567                 return -EINVAL;
 568
 569         enable_lcd_clocks(1);
 570         MOD_REG_FLD(at_reg[plane], 1, enable ? 1 : 0);
 571         enable_lcd_clocks(0);
 572
 573         return 0;
 574 }
 575
 576 static int omap_dispc_set_color_key(struct omapfb_color_key *ck)
 577 {
 578         u32 df_reg, tr_reg;
 579         int shift, val;
 580
 581         switch (ck->channel_out) {
 582         case OMAPFB_CHANNEL_OUT_LCD:
 583                 df_reg = DISPC_DEFAULT_COLOR0;
 584                 tr_reg = DISPC_TRANS_COLOR0;
 585                 shift = 10;
 586                 break;
 587         case OMAPFB_CHANNEL_OUT_DIGIT:
 588                 df_reg = DISPC_DEFAULT_COLOR1;
 589                 tr_reg = DISPC_TRANS_COLOR1;
 590                 shift = 12;
 591                 break;
 592         default:
 593                 return -EINVAL;
 594         }
 595         switch (ck->key_type) {
 596         case OMAPFB_COLOR_KEY_DISABLED:
 597                 val = 0;
 598                 break;
 599         case OMAPFB_COLOR_KEY_GFX_DST:
 600                 val = 1;
 601                 break;
 602         case OMAPFB_COLOR_KEY_VID_SRC:
 603                 val = 3;
 604                 break;
 605         default:
 606                 return -EINVAL;
 607         }
 608         enable_lcd_clocks(1);
 609         MOD_REG_FLD(DISPC_CONFIG, FLD_MASK(shift, 2), val << shift);
 610
 611         if (val != 0)
 612                 dispc_write_reg(tr_reg, ck->trans_key);
 613         dispc_write_reg(df_reg, ck->background);
 614         enable_lcd_clocks(0);
 615
 616         dispc.color_key = *ck;
 617
 618         return 0;
 619 }
 620
 621 static int omap_dispc_get_color_key(struct omapfb_color_key *ck)
 622 {
 623         *ck = dispc.color_key;
 624         return 0;
 625 }
 626
 627 static void load_palette(void)
 628 {
 629 }
 630
 631 static int omap_dispc_set_update_mode(enum omapfb_update_mode mode)
 632 {
 633         int r = 0;
 634
 635         if (mode != dispc.update_mode) {
 636                 switch (mode) {
 637                 case OMAPFB_AUTO_UPDATE:
 638                 case OMAPFB_MANUAL_UPDATE:
 639                         enable_lcd_clocks(1);
 640                         omap_dispc_enable_lcd_out(1);
 641                         dispc.update_mode = mode;
 642                         break;
 643                 case OMAPFB_UPDATE_DISABLED:
 644                         init_completion(&dispc.frame_done);
 645                         omap_dispc_enable_lcd_out(0);
 646                         if (!wait_for_completion_timeout(&dispc.frame_done,
 647                                         msecs_to_jiffies(500))) {
 648                                 dev_err(dispc.fbdev->dev,
 649                                          "timeout waiting for FRAME DONE\n");
 650                         }
 651                         dispc.update_mode = mode;
 652                         enable_lcd_clocks(0);
 653                         break;
 654                 default:
 655                         r = -EINVAL;
 656                 }
 657         }
 658
 659         return r;
 660 }
 661
 662 static unsigned long omap_dispc_get_caps(void)
 663 {
 664         return 0;
 665 }
 666
 667 static enum omapfb_update_mode omap_dispc_get_update_mode(void)
 668 {
 669         return dispc.update_mode;
 670 }
 671
 672 static void setup_color_conv_coef(void)
 673 {
 674         u32 mask = FLD_MASK(16, 11) | FLD_MASK(0, 11);
 675         int cf1_reg = DISPC_VID1_BASE + DISPC_VID_CONV_COEF0;
 676         int cf2_reg = DISPC_VID2_BASE + DISPC_VID_CONV_COEF0;
 677         int at1_reg = DISPC_VID1_BASE + DISPC_VID_ATTRIBUTES;
 678         int at2_reg = DISPC_VID2_BASE + DISPC_VID_ATTRIBUTES;
 679         const struct color_conv_coef {
 680                 int  ry,  rcr,  rcb,   gy,  gcr,  gcb,   by,  bcr,  bcb;
 681                 int  full_range;
 682         }  ctbl_bt601_5 = {
 683                     298,  409,    0,  298, -208, -100,  298,    0,  517, 0,
 684         };
 685 #if 0
 686         const struct color_conv_coef ctbl_bt601_5_full = {
 687                     256,  351,    0,  256, -179,  -86,  256,    0,  443, 1,
 688         }, ctbl_bt709 = {
 689                     298,  459,    0,  298, -137,  -55,  298,    0,  541, 0,
 690         }, ctbl_bt709_f = {
 691                     256,  394,    0,  256, -118,  -47,  256,    0,  465, 1,     },
 692 #endif
 693         const struct color_conv_coef *ct;
 694 #define CVAL(x, y)      (((x & 2047) << 16) | (y & 2047))
 695
 696         ct = &ctbl_bt601_5;
 697
 698         MOD_REG_FLD(cf1_reg,            mask,   CVAL(ct->rcr, ct->ry));
 699         MOD_REG_FLD(cf1_reg + 4,        mask,   CVAL(ct->gy,  ct->rcb));
 700         MOD_REG_FLD(cf1_reg + 8,        mask,   CVAL(ct->gcb, ct->gcr));
 701         MOD_REG_FLD(cf1_reg + 12,       mask,   CVAL(ct->bcr, ct->by));
 702         MOD_REG_FLD(cf1_reg + 16,       mask,   CVAL(0,       ct->bcb));
 703
 704         MOD_REG_FLD(cf2_reg,            mask,   CVAL(ct->rcr, ct->ry));
 705         MOD_REG_FLD(cf2_reg + 4,        mask,   CVAL(ct->gy,  ct->rcb));
 706         MOD_REG_FLD(cf2_reg + 8,        mask,   CVAL(ct->gcb, ct->gcr));
 707         MOD_REG_FLD(cf2_reg + 12,       mask,   CVAL(ct->bcr, ct->by));
 708         MOD_REG_FLD(cf2_reg + 16,       mask,   CVAL(0,       ct->bcb));
 709 #undef CVAL
 710
 711         MOD_REG_FLD(at1_reg, (1 << 11), ct->full_range);
 712         MOD_REG_FLD(at2_reg, (1 << 11), ct->full_range);
 713 }
 714
 715 static void calc_ck_div(int is_tft, int pck, int *lck_div, int *pck_div)
 716 {
 717         unsigned long fck, lck;
 718
 719         *lck_div = 1;
 720         pck = max(1, pck);
 721         fck = clk_get_rate(dispc.dss1_fck);
 722         lck = fck;
 723         *pck_div = (lck + pck - 1) / pck;
 724         if (is_tft)
 725                 *pck_div = max(2, *pck_div);
 726         else
 727                 *pck_div = max(3, *pck_div);
 728         if (*pck_div > 255) {
 729                 *pck_div = 255;
 730                 lck = pck * *pck_div;
 731                 *lck_div = fck / lck;
 732                 BUG_ON(*lck_div < 1);
 733                 if (*lck_div > 255) {
 734                         *lck_div = 255;
 735                         dev_warn(dispc.fbdev->dev, "pixclock %d kHz too low.\n",
 736                                  pck / 1000);
 737                 }
 738         }
 739 }
 740
 741 static void set_lcd_tft_mode(int enable)
 742 {
 743         u32 mask;
 744
 745         mask = 1 << 3;
 746         MOD_REG_FLD(DISPC_CONTROL, mask, enable ? mask : 0);
 747 }
 748
 749 static void set_lcd_timings(void)
 750 {
 751         u32 l;
 752         int lck_div, pck_div;
 753         struct lcd_panel *panel = dispc.fbdev->panel;
 754         int is_tft = panel->config & OMAP_LCDC_PANEL_TFT;
 755         unsigned long fck;
 756
 757         l = dispc_read_reg(DISPC_TIMING_H);
 758         l &= ~(FLD_MASK(0, 6) | FLD_MASK(8, 8) | FLD_MASK(20, 8));
 759         l |= ( max(1, (min(64,  panel->hsw))) - 1 ) << 0;
 760         l |= ( max(1, (min(256, panel->hfp))) - 1 ) << 8;
 761         l |= ( max(1, (min(256, panel->hbp))) - 1 ) << 20;
 762         dispc_write_reg(DISPC_TIMING_H, l);
 763
 764         l = dispc_read_reg(DISPC_TIMING_V);
 765         l &= ~(FLD_MASK(0, 6) | FLD_MASK(8, 8) | FLD_MASK(20, 8));
 766         l |= ( max(1, (min(64,  panel->vsw))) - 1 ) << 0;
 767         l |= ( max(0, (min(255, panel->vfp))) - 0 ) << 8;
 768         l |= ( max(0, (min(255, panel->vbp))) - 0 ) << 20;
 769         dispc_write_reg(DISPC_TIMING_V, l);
 770
 771         l = dispc_read_reg(DISPC_POL_FREQ);
 772         l &= ~FLD_MASK(12, 6);
 773         l |= (panel->config & OMAP_LCDC_SIGNAL_MASK) << 12;
 774         l |= panel->acb & 0xff;
 775         dispc_write_reg(DISPC_POL_FREQ, l);
 776
 777         calc_ck_div(is_tft, panel->pixel_clock * 1000, &lck_div, &pck_div);
 778
 779         l = dispc_read_reg(DISPC_DIVISOR);
 780         l &= ~(FLD_MASK(16, 8) | FLD_MASK(0, 8));
 781         l |= (lck_div << 16) | (pck_div << 0);
 782         dispc_write_reg(DISPC_DIVISOR, l);
 783
 784         /* update panel info with the exact clock */
 785         fck = clk_get_rate(dispc.dss1_fck);
 786         panel->pixel_clock = fck / lck_div / pck_div / 1000;
 787 }
 788
 789 int omap_dispc_request_irq(void (*callback)(void *data), void *data)
 790 {
 791         int r = 0;
 792
 793         BUG_ON(callback == NULL);
 794
 795         if (dispc.irq_callback)
 796                 r = -EBUSY;
 797         else {
 798                 dispc.irq_callback = callback;
 799                 dispc.irq_callback_data = data;
 800         }
 801
 802         return r;
 803 }
 804 EXPORT_SYMBOL(omap_dispc_request_irq);
 805
 806 void omap_dispc_enable_irqs(int irq_mask)
 807 {
 808         enable_lcd_clocks(1);
 809         dispc.enabled_irqs = irq_mask;
 810         irq_mask |= DISPC_IRQ_MASK_ERROR;
 811         MOD_REG_FLD(DISPC_IRQENABLE, 0x7fff, irq_mask);
 812         enable_lcd_clocks(0);
 813 }
 814 EXPORT_SYMBOL(omap_dispc_enable_irqs);
 815
 816 void omap_dispc_disable_irqs(int irq_mask)
 817 {
 818         enable_lcd_clocks(1);
 819         dispc.enabled_irqs &= ~irq_mask;
 820         irq_mask &= ~DISPC_IRQ_MASK_ERROR;
 821         MOD_REG_FLD(DISPC_IRQENABLE, 0x7fff, irq_mask);
 822         enable_lcd_clocks(0);
 823 }
 824 EXPORT_SYMBOL(omap_dispc_disable_irqs);
 825
 826 void omap_dispc_free_irq(void)
 827 {
 828         enable_lcd_clocks(1);
 829         omap_dispc_disable_irqs(DISPC_IRQ_MASK_ALL);
 830         dispc.irq_callback = NULL;
 831         dispc.irq_callback_data = NULL;
 832         enable_lcd_clocks(0);
 833 }
 834 EXPORT_SYMBOL(omap_dispc_free_irq);
 835
 836 static irqreturn_t omap_dispc_irq_handler(int irq, void *dev)
 837 {
 838         u32 stat = dispc_read_reg(DISPC_IRQSTATUS);
 839         static int jabber;
 840
 841         if (stat & DISPC_IRQ_FRAMEMASK)
 842                 complete(&dispc.frame_done);
 843
 844         if (stat & DISPC_IRQ_MASK_ERROR) {
 845                 if (jabber++ < 5) {
 846                         dev_err(dispc.fbdev->dev, "irq error status %04x\n",
 847                                 stat & 0x7fff);
 848                 } else {
 849                         dev_err(dispc.fbdev->dev, "disable irq\n");
 850                         dispc_write_reg(DISPC_IRQENABLE, 0);
 851                 }
 852         }
 853
 854         if ((stat & dispc.enabled_irqs) && dispc.irq_callback)
 855                 dispc.irq_callback(dispc.irq_callback_data);
 856
 857         dispc_write_reg(DISPC_IRQSTATUS, stat);
 858
 859         return IRQ_HANDLED;
 860 }
 861
 862 static int get_dss_clocks(void)
 863 {
 864         if (IS_ERR((dispc.dss_ick = clk_get(dispc.fbdev->dev, "dss_ick")))) {
 865                 dev_err(dispc.fbdev->dev, "can't get dss_ick");
 866                 return PTR_ERR(dispc.dss_ick);
 867         }
 868
 869         if (IS_ERR((dispc.dss1_fck = clk_get(dispc.fbdev->dev, "dss1_fck")))) {
 870                 dev_err(dispc.fbdev->dev, "can't get dss1_fck");
 871                 clk_put(dispc.dss_ick);
 872                 return PTR_ERR(dispc.dss1_fck);
 873         }
 874
 875         if (IS_ERR((dispc.dss_54m_fck =
 876                                 clk_get(dispc.fbdev->dev, "dss_54m_fck")))) {
 877                 dev_err(dispc.fbdev->dev, "can't get dss_54m_fck");
 878                 clk_put(dispc.dss_ick);
 879                 clk_put(dispc.dss1_fck);
 880                 return PTR_ERR(dispc.dss_54m_fck);
 881         }
 882
 883         return 0;
 884 }
 885
 886 static void put_dss_clocks(void)
 887 {
 888         clk_put(dispc.dss_54m_fck);
 889         clk_put(dispc.dss1_fck);
 890         clk_put(dispc.dss_ick);
 891 }
 892
 893 static void enable_lcd_clocks(int enable)
 894 {
 895         if (enable)
 896                 clk_enable(dispc.dss1_fck);
 897         else
 898                 clk_disable(dispc.dss1_fck);
 899 }
 900
 901 static void enable_interface_clocks(int enable)
 902 {
 903         if (enable)
 904                 clk_enable(dispc.dss_ick);
 905         else
 906                 clk_disable(dispc.dss_ick);
 907 }
 908
 909 static void enable_digit_clocks(int enable)
 910 {
 911         if (enable)
 912                 clk_enable(dispc.dss_54m_fck);
 913         else
 914                 clk_disable(dispc.dss_54m_fck);
 915 }
 916
 917 static void omap_dispc_suspend(void)
 918 {
 919         if (dispc.update_mode == OMAPFB_AUTO_UPDATE) {
 920                 init_completion(&dispc.frame_done);
 921                 omap_dispc_enable_lcd_out(0);
 922                 if (!wait_for_completion_timeout(&dispc.frame_done,
 923                                 msecs_to_jiffies(500))) {
 924                         dev_err(dispc.fbdev->dev,
 925                                 "timeout waiting for FRAME DONE\n");
 926                 }
 927                 enable_lcd_clocks(0);
 928         }
 929 }
 930
 931 static void omap_dispc_resume(void)
 932 {
 933         if (dispc.update_mode == OMAPFB_AUTO_UPDATE) {
 934                 enable_lcd_clocks(1);
 935                 if (!dispc.ext_mode) {
 936                         set_lcd_timings();
 937                         load_palette();
 938                 }
 939                 omap_dispc_enable_lcd_out(1);
 940         }
 941 }
 942
 943
 944 static int omap_dispc_update_window(struct fb_info *fbi,
 945                                  struct omapfb_update_window *win,
 946                                  void (*complete_callback)(void *arg),
 947                                  void *complete_callback_data)
 948 {
 949         return dispc.update_mode == OMAPFB_UPDATE_DISABLED ? -ENODEV : 0;
 950 }
 951
 952 static int mmap_kern(struct omapfb_mem_region *region)
 953 {
 954         struct vm_struct        *kvma;
 955         struct vm_area_struct   vma;
 956         pgprot_t                pgprot;
 957         unsigned long           vaddr;
 958
 959         kvma = get_vm_area(region->size, VM_IOREMAP);
 960         if (kvma == NULL) {
 961                 dev_err(dispc.fbdev->dev, "can't get kernel vm area\n");
 962                 return -ENOMEM;
 963         }
 964         vma.vm_mm = &init_mm;
 965
 966         vaddr = (unsigned long)kvma->addr;
 967
 968         pgprot = pgprot_writecombine(pgprot_kernel);
 969         vma.vm_start = vaddr;
 970         vma.vm_end = vaddr + region->size;
 971         if (io_remap_pfn_range(&vma, vaddr, region->paddr >> PAGE_SHIFT,
 972                            region->size, pgprot) < 0) {
 973                 dev_err(dispc.fbdev->dev, "kernel mmap for FBMEM failed\n");
 974                 return -EAGAIN;
 975         }
 976         region->vaddr = (void *)vaddr;
 977
 978         return 0;
 979 }
 980
 981 static void unmap_kern(struct omapfb_mem_region *region)
 982 {
 983         vunmap(region->vaddr);
 984 }
 985
 986 static int alloc_palette_ram(void)
 987 {
 988         dispc.palette_vaddr = dma_alloc_writecombine(dispc.fbdev->dev,
 989                 MAX_PALETTE_SIZE, &dispc.palette_paddr, GFP_KERNEL);
 990         if (dispc.palette_vaddr == NULL) {
 991                 dev_err(dispc.fbdev->dev, "failed to alloc palette memory\n");
 992                 return -ENOMEM;
 993         }
 994
 995         return 0;
 996 }
 997
 998 static void free_palette_ram(void)
 999 {
1000         dma_free_writecombine(dispc.fbdev->dev, MAX_PALETTE_SIZE,
1001                         dispc.palette_vaddr, dispc.palette_paddr);
1002 }
1003
1004 static int alloc_fbmem(struct omapfb_mem_region *region)
1005 {
1006         region->vaddr = dma_alloc_writecombine(dispc.fbdev->dev,
1007                         region->size, &region->paddr, GFP_KERNEL);
1008
1009         if (region->vaddr == NULL) {
1010                 dev_err(dispc.fbdev->dev, "unable to allocate FB DMA memory\n");
1011                 return -ENOMEM;
1012         }
1013
1014         return 0;
1015 }
1016
1017 static void free_fbmem(struct omapfb_mem_region *region)
1018 {
1019         dma_free_writecombine(dispc.fbdev->dev, region->size,
1020                               region->vaddr, region->paddr);
1021 }
1022
1023 static int setup_fbmem(struct omapfb_mem_desc *req_md)
1024 {
1025         struct omapfb_mem_region        *rg;
1026         int i;
1027         int r;
1028
1029         if (!req_md->region_cnt) {
1030                 dev_err(dispc.fbdev->dev, "no memory regions defined\n");
1031                 return -ENOENT;
1032         }
1033
1034         rg = &req_md->region[0];
1035
1036         for (i = 0; i < req_md->region_cnt; i++, rg++) {
1037                 if (rg->paddr) {
1038                         rg->alloc = 0;
1039                         if ((r = mmap_kern(rg)) < 0)
1040                                 return r;
1041                 } else {
1042                         rg->alloc = 1;
1043                         if ((r = alloc_fbmem(rg)) < 0)
1044                                 return r;
1045                 }
1046         }
1047
1048         dispc.mem_desc = *req_md;
1049
1050         return 0;
1051 }
1052
1053 static void cleanup_fbmem(void)
1054 {
1055         int i;
1056
1057         for (i = 0; i < dispc.mem_desc.region_cnt; i++) {
1058                 if (dispc.mem_desc.region[i].alloc)
1059                         free_fbmem(&dispc.mem_desc.region[i]);
1060                 else
1061                         unmap_kern(&dispc.mem_desc.region[i]);
1062         }
1063 }
1064
1065 static int omap_dispc_init(struct omapfb_device *fbdev, int ext_mode,
1066                            struct omapfb_mem_desc *req_vram)
1067 {
1068         int r;
1069         u32 l;
1070         struct lcd_panel *panel = fbdev->panel;
1071         int tmo = 10000;
1072         int skip_init = 0;
1073         int i;
1074
1075         memset(&dispc, 0, sizeof(dispc));
1076
1077         dispc.base = io_p2v(DISPC_BASE);
1078         dispc.fbdev = fbdev;
1079         dispc.ext_mode = ext_mode;
1080
1081         init_completion(&dispc.frame_done);
1082
1083         if ((r = get_dss_clocks()) < 0)
1084                 return r;
1085
1086         enable_interface_clocks(1);
1087         enable_lcd_clocks(1);
1088
1089 #ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT
1090         l = dispc_read_reg(DISPC_CONTROL);
1091         /* LCD enabled ? */
1092         if (l & 1) {
1093                 pr_info("omapfb: skipping hardware initialization\n");
1094                 skip_init = 1;
1095         }
1096 #endif
1097
1098         if (!skip_init) {
1099                 /* Reset monitoring works only w/ the 54M clk */
1100                 enable_digit_clocks(1);
1101
1102                 /* Soft reset */
1103                 MOD_REG_FLD(DISPC_SYSCONFIG, 1 << 1, 1 << 1);
1104
1105                 while (!(dispc_read_reg(DISPC_SYSSTATUS) & 1)) {
1106                         if (!--tmo) {
1107                                 dev_err(dispc.fbdev->dev, "soft reset failed\n");
1108                                 r = -ENODEV;
1109                                 enable_digit_clocks(0);
1110                                 goto fail1;
1111                         }
1112                 }
1113
1114                 enable_digit_clocks(0);
1115         }
1116
1117         /* Enable smart idle and autoidle */
1118         l = dispc_read_reg(DISPC_CONTROL);
1119         l &= ~((3 << 12) | (3 << 3));
1120         l |= (2 << 12) | (2 << 3) | (1 << 0);
1121         dispc_write_reg(DISPC_SYSCONFIG, l);
1122         omap_writel(1 << 0, DSS_BASE + DSS_SYSCONFIG);
1123
1124         /* Set functional clock autogating */
1125         l = dispc_read_reg(DISPC_CONFIG);
1126         l |= 1 << 9;
1127         dispc_write_reg(DISPC_CONFIG, l);
1128
1129         l = dispc_read_reg(DISPC_IRQSTATUS);
1130         dispc_write_reg(l, DISPC_IRQSTATUS);
1131
1132         /* Enable those that we handle always */
1133         omap_dispc_enable_irqs(DISPC_IRQ_FRAMEMASK);
1134
1135         if ((r = request_irq(INT_24XX_DSS_IRQ, omap_dispc_irq_handler,
1136                            0, MODULE_NAME, fbdev)) < 0) {
1137                 dev_err(dispc.fbdev->dev, "can't get DSS IRQ\n");
1138                 goto fail1;
1139         }
1140
1141         /* L3 firewall setting: enable access to OCM RAM */
1142         __raw_writel(0x402000b0, io_p2v(0x680050a0));
1143
1144         if ((r = alloc_palette_ram()) < 0)
1145                 goto fail2;
1146
1147         if ((r = setup_fbmem(req_vram)) < 0)
1148                 goto fail3;
1149
1150         if (!skip_init) {
1151                 for (i = 0; i < dispc.mem_desc.region_cnt; i++) {
1152                         memset(dispc.mem_desc.region[i].vaddr, 0,
1153                                 dispc.mem_desc.region[i].size);
1154                 }
1155
1156                 /* Set logic clock to fck, pixel clock to fck/2 for now */
1157                 MOD_REG_FLD(DISPC_DIVISOR, FLD_MASK(16, 8), 1 << 16);
1158                 MOD_REG_FLD(DISPC_DIVISOR, FLD_MASK(0, 8), 2 << 0);
1159
1160                 setup_plane_fifo(0, ext_mode);
1161                 setup_plane_fifo(1, ext_mode);
1162                 setup_plane_fifo(2, ext_mode);
1163
1164                 setup_color_conv_coef();
1165
1166                 set_lcd_tft_mode(panel->config & OMAP_LCDC_PANEL_TFT);
1167                 set_load_mode(DISPC_LOAD_FRAME_ONLY);
1168
1169                 if (!ext_mode) {
1170                         set_lcd_data_lines(panel->data_lines);
1171                         omap_dispc_set_lcd_size(panel->x_res, panel->y_res);
1172                         set_lcd_timings();
1173                 } else
1174                         set_lcd_data_lines(panel->bpp);
1175                 enable_rfbi_mode(ext_mode);
1176         }
1177
1178         l = dispc_read_reg(DISPC_REVISION);
1179         pr_info("omapfb: DISPC version %d.%d initialized\n",
1180                  l >> 4 & 0x0f, l & 0x0f);
1181         enable_lcd_clocks(0);
1182
1183         return 0;
1184 fail3:
1185         free_palette_ram();
1186 fail2:
1187         free_irq(INT_24XX_DSS_IRQ, fbdev);
1188 fail1:
1189         enable_lcd_clocks(0);
1190         enable_interface_clocks(0);
1191         put_dss_clocks();
1192
1193         return r;
1194 }
1195
1196 static void omap_dispc_cleanup(void)
1197 {
1198         int i;
1199
1200         omap_dispc_set_update_mode(OMAPFB_UPDATE_DISABLED);
1201         /* This will also disable clocks that are on */
1202         for (i = 0; i < dispc.mem_desc.region_cnt; i++)
1203                 omap_dispc_enable_plane(i, 0);
1204         cleanup_fbmem();
1205         free_palette_ram();
1206         free_irq(INT_24XX_DSS_IRQ, dispc.fbdev);
1207         enable_interface_clocks(0);
1208         put_dss_clocks();
1209 }
1210
1211 const struct lcd_ctrl omap2_int_ctrl = {
1212         .name                   = "internal",
1213         .init                   = omap_dispc_init,
1214         .cleanup                = omap_dispc_cleanup,
1215         .get_caps               = omap_dispc_get_caps,
1216         .set_update_mode        = omap_dispc_set_update_mode,
1217         .get_update_mode        = omap_dispc_get_update_mode,
1218         .update_window          = omap_dispc_update_window,
1219         .suspend                = omap_dispc_suspend,
1220         .resume                 = omap_dispc_resume,
1221         .setup_plane            = omap_dispc_setup_plane,
1222         .set_scale              = omap_dispc_set_scale,
1223         .enable_plane           = omap_dispc_enable_plane,
1224         .set_color_key          = omap_dispc_set_color_key,
1225         .get_color_key          = omap_dispc_get_color_key,
1226 };