2 * OMAP2 display controller support
4 * Copyright (C) 2005 Nokia Corporation
5 * Author: Imre Deak <imre.deak@nokia.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 #include <linux/kernel.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/vmalloc.h>
24 #include <linux/clk.h>
28 #include <asm/arch/sram.h>
29 #include <asm/arch/omapfb.h>
30 #include <asm/arch/board.h>
34 #define MODULE_NAME "dispc"
36 #define DSS_BASE 0x48050000
37 #define DSS_SYSCONFIG 0x0010
39 #define DISPC_BASE 0x48050400
42 #define DISPC_REVISION 0x0000
43 #define DISPC_SYSCONFIG 0x0010
44 #define DISPC_SYSSTATUS 0x0014
45 #define DISPC_IRQSTATUS 0x0018
46 #define DISPC_IRQENABLE 0x001C
47 #define DISPC_CONTROL 0x0040
48 #define DISPC_CONFIG 0x0044
49 #define DISPC_CAPABLE 0x0048
50 #define DISPC_DEFAULT_COLOR0 0x004C
51 #define DISPC_DEFAULT_COLOR1 0x0050
52 #define DISPC_TRANS_COLOR0 0x0054
53 #define DISPC_TRANS_COLOR1 0x0058
54 #define DISPC_LINE_STATUS 0x005C
55 #define DISPC_LINE_NUMBER 0x0060
56 #define DISPC_TIMING_H 0x0064
57 #define DISPC_TIMING_V 0x0068
58 #define DISPC_POL_FREQ 0x006C
59 #define DISPC_DIVISOR 0x0070
60 #define DISPC_SIZE_DIG 0x0078
61 #define DISPC_SIZE_LCD 0x007C
63 #define DISPC_DATA_CYCLE1 0x01D4
64 #define DISPC_DATA_CYCLE2 0x01D8
65 #define DISPC_DATA_CYCLE3 0x01DC
68 #define DISPC_GFX_BA0 0x0080
69 #define DISPC_GFX_BA1 0x0084
70 #define DISPC_GFX_POSITION 0x0088
71 #define DISPC_GFX_SIZE 0x008C
72 #define DISPC_GFX_ATTRIBUTES 0x00A0
73 #define DISPC_GFX_FIFO_THRESHOLD 0x00A4
74 #define DISPC_GFX_FIFO_SIZE_STATUS 0x00A8
75 #define DISPC_GFX_ROW_INC 0x00AC
76 #define DISPC_GFX_PIXEL_INC 0x00B0
77 #define DISPC_GFX_WINDOW_SKIP 0x00B4
78 #define DISPC_GFX_TABLE_BA 0x00B8
80 /* DISPC Video plane 1/2 */
81 #define DISPC_VID1_BASE 0x00BC
82 #define DISPC_VID2_BASE 0x014C
84 /* Offsets into DISPC_VID1/2_BASE */
85 #define DISPC_VID_BA0 0x0000
86 #define DISPC_VID_BA1 0x0004
87 #define DISPC_VID_POSITION 0x0008
88 #define DISPC_VID_SIZE 0x000C
89 #define DISPC_VID_ATTRIBUTES 0x0010
90 #define DISPC_VID_FIFO_THRESHOLD 0x0014
91 #define DISPC_VID_FIFO_SIZE_STATUS 0x0018
92 #define DISPC_VID_ROW_INC 0x001C
93 #define DISPC_VID_PIXEL_INC 0x0020
94 #define DISPC_VID_FIR 0x0024
95 #define DISPC_VID_PICTURE_SIZE 0x0028
96 #define DISPC_VID_ACCU0 0x002C
97 #define DISPC_VID_ACCU1 0x0030
99 /* 8 elements in 8 byte increments */
100 #define DISPC_VID_FIR_COEF_H0 0x0034
101 /* 8 elements in 8 byte increments */
102 #define DISPC_VID_FIR_COEF_HV0 0x0038
103 /* 5 elements in 4 byte increments */
104 #define DISPC_VID_CONV_COEF0 0x0074
106 #define DISPC_IRQ_FRAMEMASK 0x0001
107 #define DISPC_IRQ_VSYNC 0x0002
108 #define DISPC_IRQ_EVSYNC_EVEN 0x0004
109 #define DISPC_IRQ_EVSYNC_ODD 0x0008
110 #define DISPC_IRQ_ACBIAS_COUNT_STAT 0x0010
111 #define DISPC_IRQ_PROG_LINE_NUM 0x0020
112 #define DISPC_IRQ_GFX_FIFO_UNDERFLOW 0x0040
113 #define DISPC_IRQ_GFX_END_WIN 0x0080
114 #define DISPC_IRQ_PAL_GAMMA_MASK 0x0100
115 #define DISPC_IRQ_OCP_ERR 0x0200
116 #define DISPC_IRQ_VID1_FIFO_UNDERFLOW 0x0400
117 #define DISPC_IRQ_VID1_END_WIN 0x0800
118 #define DISPC_IRQ_VID2_FIFO_UNDERFLOW 0x1000
119 #define DISPC_IRQ_VID2_END_WIN 0x2000
120 #define DISPC_IRQ_SYNC_LOST 0x4000
122 #define DISPC_IRQ_MASK_ALL 0x7fff
124 #define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
125 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
126 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
129 #define RFBI_CONTROL 0x48050040
131 #define MAX_PALETTE_SIZE (256 * 16)
133 #define FLD_MASK(pos, len) (((1 << len) - 1) << pos)
135 #define MOD_REG_FLD(reg, mask, val) \
136 dispc_write_reg((reg), (dispc_read_reg(reg) & ~(mask)) | (val));
138 #define OMAP2_SRAM_START 0x40200000
139 /* Maximum size, in reality this is smaller if SRAM is partially locked. */
140 #define OMAP2_SRAM_SIZE 0xa0000 /* 640k */
142 /* We support the SDRAM / SRAM types. See OMAPFB_PLANE_MEMTYPE_* in omapfb.h */
143 #define DISPC_MEMTYPE_NUM 2
145 #define RESMAP_SIZE(_page_cnt) \
146 ((_page_cnt + (sizeof(unsigned long) * 8) - 1) / 8)
147 #define RESMAP_PTR(_res_map, _page_nr) \
148 (((_res_map)->map) + (_page_nr) / (sizeof(unsigned long) * 8))
149 #define RESMAP_MASK(_page_nr) \
150 (1 << ((_page_nr) & (sizeof(unsigned long) * 8 - 1)))
161 struct omapfb_mem_desc mem_desc;
162 struct resmap *res_map[DISPC_MEMTYPE_NUM];
163 atomic_t map_count[OMAPFB_PLANE_NUM];
165 dma_addr_t palette_paddr;
170 unsigned long enabled_irqs;
171 void (*irq_callback)(void *);
172 void *irq_callback_data;
173 struct completion frame_done;
175 int fir_hinc[OMAPFB_PLANE_NUM];
176 int fir_vinc[OMAPFB_PLANE_NUM];
178 struct clk *dss_ick, *dss1_fck;
179 struct clk *dss_54m_fck;
181 enum omapfb_update_mode update_mode;
182 struct omapfb_device *fbdev;
184 struct omapfb_color_key color_key;
187 static void enable_lcd_clocks(int enable);
189 static void inline dispc_write_reg(int idx, u32 val)
191 __raw_writel(val, dispc.base + idx);
194 static u32 inline dispc_read_reg(int idx)
196 u32 l = __raw_readl(dispc.base + idx);
200 /* Select RFBI or bypass mode */
201 static void enable_rfbi_mode(int enable)
205 l = dispc_read_reg(DISPC_CONTROL);
206 /* Enable RFBI, GPIO0/1 */
207 l &= ~((1 << 11) | (1 << 15) | (1 << 16));
208 l |= enable ? (1 << 11) : 0;
209 /* RFBI En: GPIO0/1=10 RFBI Dis: GPIO0/1=11 */
211 l |= enable ? 0 : (1 << 16);
212 dispc_write_reg(DISPC_CONTROL, l);
214 /* Set bypass mode in RFBI module */
215 l = __raw_readl(io_p2v(RFBI_CONTROL));
216 l |= enable ? 0 : (1 << 1);
217 __raw_writel(l, io_p2v(RFBI_CONTROL));
220 static void set_lcd_data_lines(int data_lines)
225 switch (data_lines) {
242 l = dispc_read_reg(DISPC_CONTROL);
245 dispc_write_reg(DISPC_CONTROL, l);
248 static void set_load_mode(int mode)
250 BUG_ON(mode & ~(DISPC_LOAD_CLUT_ONLY | DISPC_LOAD_FRAME_ONLY |
251 DISPC_LOAD_CLUT_ONCE_FRAME));
252 MOD_REG_FLD(DISPC_CONFIG, 0x03 << 1, mode << 1);
255 void omap_dispc_set_lcd_size(int x, int y)
257 BUG_ON((x > (1 << 11)) || (y > (1 << 11)));
258 enable_lcd_clocks(1);
259 MOD_REG_FLD(DISPC_SIZE_LCD, FLD_MASK(16, 11) | FLD_MASK(0, 11),
260 ((y - 1) << 16) | (x - 1));
261 enable_lcd_clocks(0);
263 EXPORT_SYMBOL(omap_dispc_set_lcd_size);
265 void omap_dispc_set_digit_size(int x, int y)
267 BUG_ON((x > (1 << 11)) || (y > (1 << 11)));
268 enable_lcd_clocks(1);
269 MOD_REG_FLD(DISPC_SIZE_DIG, FLD_MASK(16, 11) | FLD_MASK(0, 11),
270 ((y - 1) << 16) | (x - 1));
271 enable_lcd_clocks(0);
273 EXPORT_SYMBOL(omap_dispc_set_digit_size);
275 static void setup_plane_fifo(int plane, int ext_mode)
277 const u32 ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
278 DISPC_VID1_BASE + DISPC_VID_FIFO_THRESHOLD,
279 DISPC_VID2_BASE + DISPC_VID_FIFO_THRESHOLD };
280 const u32 fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
281 DISPC_VID1_BASE + DISPC_VID_FIFO_SIZE_STATUS,
282 DISPC_VID2_BASE + DISPC_VID_FIFO_SIZE_STATUS };
288 l = dispc_read_reg(fsz_reg[plane]);
297 MOD_REG_FLD(ftrs_reg[plane], FLD_MASK(16, 9) | FLD_MASK(0, 9),
301 void omap_dispc_enable_lcd_out(int enable)
303 enable_lcd_clocks(1);
304 MOD_REG_FLD(DISPC_CONTROL, 1, enable ? 1 : 0);
305 enable_lcd_clocks(0);
307 EXPORT_SYMBOL(omap_dispc_enable_lcd_out);
309 void omap_dispc_enable_digit_out(int enable)
311 enable_lcd_clocks(1);
312 MOD_REG_FLD(DISPC_CONTROL, 1 << 1, enable ? 1 << 1 : 0);
313 enable_lcd_clocks(0);
315 EXPORT_SYMBOL(omap_dispc_enable_digit_out);
317 static inline int _setup_plane(int plane, int channel_out,
318 u32 paddr, int screen_width,
319 int pos_x, int pos_y, int width, int height,
322 const u32 at_reg[] = { DISPC_GFX_ATTRIBUTES,
323 DISPC_VID1_BASE + DISPC_VID_ATTRIBUTES,
324 DISPC_VID2_BASE + DISPC_VID_ATTRIBUTES };
325 const u32 ba_reg[] = { DISPC_GFX_BA0, DISPC_VID1_BASE + DISPC_VID_BA0,
326 DISPC_VID2_BASE + DISPC_VID_BA0 };
327 const u32 ps_reg[] = { DISPC_GFX_POSITION,
328 DISPC_VID1_BASE + DISPC_VID_POSITION,
329 DISPC_VID2_BASE + DISPC_VID_POSITION };
330 const u32 sz_reg[] = { DISPC_GFX_SIZE,
331 DISPC_VID1_BASE + DISPC_VID_PICTURE_SIZE,
332 DISPC_VID2_BASE + DISPC_VID_PICTURE_SIZE };
333 const u32 ri_reg[] = { DISPC_GFX_ROW_INC,
334 DISPC_VID1_BASE + DISPC_VID_ROW_INC,
335 DISPC_VID2_BASE + DISPC_VID_ROW_INC };
336 const u32 vs_reg[]= { 0, DISPC_VID1_BASE + DISPC_VID_SIZE,
337 DISPC_VID2_BASE + DISPC_VID_SIZE };
339 int chout_shift, burst_shift;
348 dev_dbg(dispc.fbdev->dev, "plane %d channel %d paddr %#08x scr_width %d "
349 "pos_x %d pos_y %d width %d height %d color_mode %d\n",
350 plane, channel_out, paddr, screen_width, pos_x, pos_y,
351 width, height, color_mode);
356 case OMAPFB_PLANE_GFX:
360 case OMAPFB_PLANE_VID1:
361 case OMAPFB_PLANE_VID2:
370 switch (channel_out) {
371 case OMAPFB_CHANNEL_OUT_LCD:
374 case OMAPFB_CHANNEL_OUT_DIGIT:
382 switch (color_mode) {
383 case OMAPFB_COLOR_RGB565:
384 color_code = DISPC_RGB_16_BPP;
387 case OMAPFB_COLOR_YUV422:
390 color_code = DISPC_UYVY_422;
394 case OMAPFB_COLOR_YUY422:
397 color_code = DISPC_YUV2_422;
405 l = dispc_read_reg(at_reg[plane]);
408 l |= color_code << 1;
412 l &= ~(0x03 << burst_shift);
413 l |= DISPC_BURST_8x32 << burst_shift;
415 l &= ~(1 << chout_shift);
416 l |= chout_val << chout_shift;
418 dispc_write_reg(at_reg[plane], l);
420 dispc_write_reg(ba_reg[plane], paddr);
421 MOD_REG_FLD(ps_reg[plane],
422 FLD_MASK(16, 11) | FLD_MASK(0, 11), (pos_y << 16) | pos_x);
424 MOD_REG_FLD(sz_reg[plane], FLD_MASK(16, 11) | FLD_MASK(0, 11),
425 ((height - 1) << 16) | (width - 1));
428 /* Set video size if set_scale hasn't set it */
429 if (!dispc.fir_vinc[plane])
430 MOD_REG_FLD(vs_reg[plane],
431 FLD_MASK(16, 11), (height - 1) << 16);
432 if (!dispc.fir_hinc[plane])
433 MOD_REG_FLD(vs_reg[plane],
434 FLD_MASK(0, 11), width - 1);
437 dispc_write_reg(ri_reg[plane], (screen_width - width) * bpp / 8 + 1);
439 return height * screen_width * bpp / 8;
442 static int omap_dispc_setup_plane(int plane, int channel_out,
443 unsigned long offset,
445 int pos_x, int pos_y, int width, int height,
451 if ((unsigned)plane > dispc.mem_desc.region_cnt)
453 paddr = dispc.mem_desc.region[plane].paddr + offset;
454 enable_lcd_clocks(1);
455 r = _setup_plane(plane, channel_out, paddr,
457 pos_x, pos_y, width, height, color_mode);
458 enable_lcd_clocks(0);
462 static void write_firh_reg(int plane, int reg, u32 value)
467 base = DISPC_VID1_BASE + DISPC_VID_FIR_COEF_H0;
469 base = DISPC_VID2_BASE + DISPC_VID_FIR_COEF_H0;
470 dispc_write_reg(base + reg * 8, value);
473 static void write_firhv_reg(int plane, int reg, u32 value)
478 base = DISPC_VID1_BASE + DISPC_VID_FIR_COEF_HV0;
480 base = DISPC_VID2_BASE + DISPC_VID_FIR_COEF_HV0;
481 dispc_write_reg(base + reg * 8, value);
484 static void set_upsampling_coef_table(int plane)
486 const u32 coef[][2] = {
487 { 0x00800000, 0x00800000 },
488 { 0x0D7CF800, 0x037B02FF },
489 { 0x1E70F5FF, 0x0C6F05FE },
490 { 0x335FF5FE, 0x205907FB },
491 { 0xF74949F7, 0x00404000 },
492 { 0xF55F33FB, 0x075920FE },
493 { 0xF5701EFE, 0x056F0CFF },
494 { 0xF87C0DFF, 0x027B0300 },
498 for (i = 0; i < 8; i++) {
499 write_firh_reg(plane, i, coef[i][0]);
500 write_firhv_reg(plane, i, coef[i][1]);
504 static int omap_dispc_set_scale(int plane,
505 int orig_width, int orig_height,
506 int out_width, int out_height)
508 const u32 at_reg[] = { 0, DISPC_VID1_BASE + DISPC_VID_ATTRIBUTES,
509 DISPC_VID2_BASE + DISPC_VID_ATTRIBUTES };
510 const u32 vs_reg[] = { 0, DISPC_VID1_BASE + DISPC_VID_SIZE,
511 DISPC_VID2_BASE + DISPC_VID_SIZE };
512 const u32 fir_reg[] = { 0, DISPC_VID1_BASE + DISPC_VID_FIR,
513 DISPC_VID2_BASE + DISPC_VID_FIR };
519 if ((unsigned)plane > OMAPFB_PLANE_NUM)
522 if (plane == OMAPFB_PLANE_GFX &&
523 (out_width != orig_width || out_height != orig_height))
526 enable_lcd_clocks(1);
527 if (orig_width < out_width) {
530 * Currently you can only scale both dimensions in one way.
532 if (orig_height > out_height ||
533 orig_width * 8 < out_width ||
534 orig_height * 8 < out_height) {
535 enable_lcd_clocks(0);
538 set_upsampling_coef_table(plane);
539 } else if (orig_width > out_width) {
540 /* Downsampling not yet supported
543 enable_lcd_clocks(0);
546 if (!orig_width || orig_width == out_width)
549 fir_hinc = 1024 * orig_width / out_width;
550 if (!orig_height || orig_height == out_height)
553 fir_vinc = 1024 * orig_height / out_height;
554 dispc.fir_hinc[plane] = fir_hinc;
555 dispc.fir_vinc[plane] = fir_vinc;
557 MOD_REG_FLD(fir_reg[plane],
558 FLD_MASK(16, 12) | FLD_MASK(0, 12),
559 ((fir_vinc & 4095) << 16) |
562 dev_dbg(dispc.fbdev->dev, "out_width %d out_height %d orig_width %d "
563 "orig_height %d fir_hinc %d fir_vinc %d\n",
564 out_width, out_height, orig_width, orig_height,
567 MOD_REG_FLD(vs_reg[plane],
568 FLD_MASK(16, 11) | FLD_MASK(0, 11),
569 ((out_height - 1) << 16) | (out_width - 1));
571 l = dispc_read_reg(at_reg[plane]);
573 l |= fir_hinc ? (1 << 5) : 0;
574 l |= fir_vinc ? (1 << 6) : 0;
575 dispc_write_reg(at_reg[plane], l);
577 enable_lcd_clocks(0);
581 static int omap_dispc_enable_plane(int plane, int enable)
583 const u32 at_reg[] = { DISPC_GFX_ATTRIBUTES,
584 DISPC_VID1_BASE + DISPC_VID_ATTRIBUTES,
585 DISPC_VID2_BASE + DISPC_VID_ATTRIBUTES };
586 if ((unsigned int)plane > dispc.mem_desc.region_cnt)
589 enable_lcd_clocks(1);
590 MOD_REG_FLD(at_reg[plane], 1, enable ? 1 : 0);
591 enable_lcd_clocks(0);
596 static int omap_dispc_set_color_key(struct omapfb_color_key *ck)
601 switch (ck->channel_out) {
602 case OMAPFB_CHANNEL_OUT_LCD:
603 df_reg = DISPC_DEFAULT_COLOR0;
604 tr_reg = DISPC_TRANS_COLOR0;
607 case OMAPFB_CHANNEL_OUT_DIGIT:
608 df_reg = DISPC_DEFAULT_COLOR1;
609 tr_reg = DISPC_TRANS_COLOR1;
615 switch (ck->key_type) {
616 case OMAPFB_COLOR_KEY_DISABLED:
619 case OMAPFB_COLOR_KEY_GFX_DST:
622 case OMAPFB_COLOR_KEY_VID_SRC:
628 enable_lcd_clocks(1);
629 MOD_REG_FLD(DISPC_CONFIG, FLD_MASK(shift, 2), val << shift);
632 dispc_write_reg(tr_reg, ck->trans_key);
633 dispc_write_reg(df_reg, ck->background);
634 enable_lcd_clocks(0);
636 dispc.color_key = *ck;
641 static int omap_dispc_get_color_key(struct omapfb_color_key *ck)
643 *ck = dispc.color_key;
647 static void load_palette(void)
651 static int omap_dispc_set_update_mode(enum omapfb_update_mode mode)
655 if (mode != dispc.update_mode) {
657 case OMAPFB_AUTO_UPDATE:
658 case OMAPFB_MANUAL_UPDATE:
659 enable_lcd_clocks(1);
660 omap_dispc_enable_lcd_out(1);
661 dispc.update_mode = mode;
663 case OMAPFB_UPDATE_DISABLED:
664 init_completion(&dispc.frame_done);
665 omap_dispc_enable_lcd_out(0);
666 if (!wait_for_completion_timeout(&dispc.frame_done,
667 msecs_to_jiffies(500))) {
668 dev_err(dispc.fbdev->dev,
669 "timeout waiting for FRAME DONE\n");
671 dispc.update_mode = mode;
672 enable_lcd_clocks(0);
682 static void omap_dispc_get_caps(int plane, struct omapfb_caps *caps)
684 caps->ctrl |= OMAPFB_CAPS_PLANE_RELOCATE_MEM;
686 caps->ctrl |= OMAPFB_CAPS_PLANE_SCALE;
687 caps->plane_color |= (1 << OMAPFB_COLOR_RGB565) |
688 (1 << OMAPFB_COLOR_YUV422) |
689 (1 << OMAPFB_COLOR_YUY422);
691 caps->plane_color |= (1 << OMAPFB_COLOR_CLUT_8BPP) |
692 (1 << OMAPFB_COLOR_CLUT_4BPP) |
693 (1 << OMAPFB_COLOR_CLUT_2BPP) |
694 (1 << OMAPFB_COLOR_CLUT_1BPP) |
695 (1 << OMAPFB_COLOR_RGB444);
698 static enum omapfb_update_mode omap_dispc_get_update_mode(void)
700 return dispc.update_mode;
703 static void setup_color_conv_coef(void)
705 u32 mask = FLD_MASK(16, 11) | FLD_MASK(0, 11);
706 int cf1_reg = DISPC_VID1_BASE + DISPC_VID_CONV_COEF0;
707 int cf2_reg = DISPC_VID2_BASE + DISPC_VID_CONV_COEF0;
708 int at1_reg = DISPC_VID1_BASE + DISPC_VID_ATTRIBUTES;
709 int at2_reg = DISPC_VID2_BASE + DISPC_VID_ATTRIBUTES;
710 const struct color_conv_coef {
711 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
714 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
717 const struct color_conv_coef ctbl_bt601_5_full = {
718 256, 351, 0, 256, -179, -86, 256, 0, 443, 1,
720 298, 459, 0, 298, -137, -55, 298, 0, 541, 0,
722 256, 394, 0, 256, -118, -47, 256, 0, 465, 1, },
724 const struct color_conv_coef *ct;
725 #define CVAL(x, y) (((x & 2047) << 16) | (y & 2047))
729 MOD_REG_FLD(cf1_reg, mask, CVAL(ct->rcr, ct->ry));
730 MOD_REG_FLD(cf1_reg + 4, mask, CVAL(ct->gy, ct->rcb));
731 MOD_REG_FLD(cf1_reg + 8, mask, CVAL(ct->gcb, ct->gcr));
732 MOD_REG_FLD(cf1_reg + 12, mask, CVAL(ct->bcr, ct->by));
733 MOD_REG_FLD(cf1_reg + 16, mask, CVAL(0, ct->bcb));
735 MOD_REG_FLD(cf2_reg, mask, CVAL(ct->rcr, ct->ry));
736 MOD_REG_FLD(cf2_reg + 4, mask, CVAL(ct->gy, ct->rcb));
737 MOD_REG_FLD(cf2_reg + 8, mask, CVAL(ct->gcb, ct->gcr));
738 MOD_REG_FLD(cf2_reg + 12, mask, CVAL(ct->bcr, ct->by));
739 MOD_REG_FLD(cf2_reg + 16, mask, CVAL(0, ct->bcb));
742 MOD_REG_FLD(at1_reg, (1 << 11), ct->full_range);
743 MOD_REG_FLD(at2_reg, (1 << 11), ct->full_range);
746 static void calc_ck_div(int is_tft, int pck, int *lck_div, int *pck_div)
748 unsigned long fck, lck;
752 fck = clk_get_rate(dispc.dss1_fck);
754 *pck_div = (lck + pck - 1) / pck;
756 *pck_div = max(2, *pck_div);
758 *pck_div = max(3, *pck_div);
759 if (*pck_div > 255) {
761 lck = pck * *pck_div;
762 *lck_div = fck / lck;
763 BUG_ON(*lck_div < 1);
764 if (*lck_div > 255) {
766 dev_warn(dispc.fbdev->dev, "pixclock %d kHz too low.\n",
772 static void set_lcd_tft_mode(int enable)
777 MOD_REG_FLD(DISPC_CONTROL, mask, enable ? mask : 0);
780 static void set_lcd_timings(void)
783 int lck_div, pck_div;
784 struct lcd_panel *panel = dispc.fbdev->panel;
785 int is_tft = panel->config & OMAP_LCDC_PANEL_TFT;
788 l = dispc_read_reg(DISPC_TIMING_H);
789 l &= ~(FLD_MASK(0, 6) | FLD_MASK(8, 8) | FLD_MASK(20, 8));
790 l |= ( max(1, (min(64, panel->hsw))) - 1 ) << 0;
791 l |= ( max(1, (min(256, panel->hfp))) - 1 ) << 8;
792 l |= ( max(1, (min(256, panel->hbp))) - 1 ) << 20;
793 dispc_write_reg(DISPC_TIMING_H, l);
795 l = dispc_read_reg(DISPC_TIMING_V);
796 l &= ~(FLD_MASK(0, 6) | FLD_MASK(8, 8) | FLD_MASK(20, 8));
797 l |= ( max(1, (min(64, panel->vsw))) - 1 ) << 0;
798 l |= ( max(0, (min(255, panel->vfp))) - 0 ) << 8;
799 l |= ( max(0, (min(255, panel->vbp))) - 0 ) << 20;
800 dispc_write_reg(DISPC_TIMING_V, l);
802 l = dispc_read_reg(DISPC_POL_FREQ);
803 l &= ~FLD_MASK(12, 6);
804 l |= (panel->config & OMAP_LCDC_SIGNAL_MASK) << 12;
805 l |= panel->acb & 0xff;
806 dispc_write_reg(DISPC_POL_FREQ, l);
808 calc_ck_div(is_tft, panel->pixel_clock * 1000, &lck_div, &pck_div);
810 l = dispc_read_reg(DISPC_DIVISOR);
811 l &= ~(FLD_MASK(16, 8) | FLD_MASK(0, 8));
812 l |= (lck_div << 16) | (pck_div << 0);
813 dispc_write_reg(DISPC_DIVISOR, l);
815 /* update panel info with the exact clock */
816 fck = clk_get_rate(dispc.dss1_fck);
817 panel->pixel_clock = fck / lck_div / pck_div / 1000;
820 int omap_dispc_request_irq(void (*callback)(void *data), void *data)
824 BUG_ON(callback == NULL);
826 if (dispc.irq_callback)
829 dispc.irq_callback = callback;
830 dispc.irq_callback_data = data;
835 EXPORT_SYMBOL(omap_dispc_request_irq);
837 void omap_dispc_enable_irqs(int irq_mask)
839 enable_lcd_clocks(1);
840 dispc.enabled_irqs = irq_mask;
841 irq_mask |= DISPC_IRQ_MASK_ERROR;
842 MOD_REG_FLD(DISPC_IRQENABLE, 0x7fff, irq_mask);
843 enable_lcd_clocks(0);
845 EXPORT_SYMBOL(omap_dispc_enable_irqs);
847 void omap_dispc_disable_irqs(int irq_mask)
849 enable_lcd_clocks(1);
850 dispc.enabled_irqs &= ~irq_mask;
851 irq_mask &= ~DISPC_IRQ_MASK_ERROR;
852 MOD_REG_FLD(DISPC_IRQENABLE, 0x7fff, irq_mask);
853 enable_lcd_clocks(0);
855 EXPORT_SYMBOL(omap_dispc_disable_irqs);
857 void omap_dispc_free_irq(void)
859 enable_lcd_clocks(1);
860 omap_dispc_disable_irqs(DISPC_IRQ_MASK_ALL);
861 dispc.irq_callback = NULL;
862 dispc.irq_callback_data = NULL;
863 enable_lcd_clocks(0);
865 EXPORT_SYMBOL(omap_dispc_free_irq);
867 static irqreturn_t omap_dispc_irq_handler(int irq, void *dev)
869 u32 stat = dispc_read_reg(DISPC_IRQSTATUS);
871 if (stat & DISPC_IRQ_FRAMEMASK)
872 complete(&dispc.frame_done);
874 if (stat & DISPC_IRQ_MASK_ERROR) {
875 if (printk_ratelimit()) {
876 dev_err(dispc.fbdev->dev, "irq error status %04x\n",
881 if ((stat & dispc.enabled_irqs) && dispc.irq_callback)
882 dispc.irq_callback(dispc.irq_callback_data);
884 dispc_write_reg(DISPC_IRQSTATUS, stat);
889 static int get_dss_clocks(void)
891 if (IS_ERR((dispc.dss_ick = clk_get(dispc.fbdev->dev, "dss_ick")))) {
892 dev_err(dispc.fbdev->dev, "can't get dss_ick");
893 return PTR_ERR(dispc.dss_ick);
896 if (IS_ERR((dispc.dss1_fck = clk_get(dispc.fbdev->dev, "dss1_fck")))) {
897 dev_err(dispc.fbdev->dev, "can't get dss1_fck");
898 clk_put(dispc.dss_ick);
899 return PTR_ERR(dispc.dss1_fck);
902 if (IS_ERR((dispc.dss_54m_fck =
903 clk_get(dispc.fbdev->dev, "dss_54m_fck")))) {
904 dev_err(dispc.fbdev->dev, "can't get dss_54m_fck");
905 clk_put(dispc.dss_ick);
906 clk_put(dispc.dss1_fck);
907 return PTR_ERR(dispc.dss_54m_fck);
913 static void put_dss_clocks(void)
915 clk_put(dispc.dss_54m_fck);
916 clk_put(dispc.dss1_fck);
917 clk_put(dispc.dss_ick);
920 static void enable_lcd_clocks(int enable)
923 clk_enable(dispc.dss1_fck);
925 clk_disable(dispc.dss1_fck);
928 static void enable_interface_clocks(int enable)
931 clk_enable(dispc.dss_ick);
933 clk_disable(dispc.dss_ick);
936 static void enable_digit_clocks(int enable)
939 clk_enable(dispc.dss_54m_fck);
941 clk_disable(dispc.dss_54m_fck);
944 static void omap_dispc_suspend(void)
946 if (dispc.update_mode == OMAPFB_AUTO_UPDATE) {
947 init_completion(&dispc.frame_done);
948 omap_dispc_enable_lcd_out(0);
949 if (!wait_for_completion_timeout(&dispc.frame_done,
950 msecs_to_jiffies(500))) {
951 dev_err(dispc.fbdev->dev,
952 "timeout waiting for FRAME DONE\n");
954 enable_lcd_clocks(0);
958 static void omap_dispc_resume(void)
960 if (dispc.update_mode == OMAPFB_AUTO_UPDATE) {
961 enable_lcd_clocks(1);
962 if (!dispc.ext_mode) {
966 omap_dispc_enable_lcd_out(1);
971 static int omap_dispc_update_window(struct fb_info *fbi,
972 struct omapfb_update_window *win,
973 void (*complete_callback)(void *arg),
974 void *complete_callback_data)
976 return dispc.update_mode == OMAPFB_UPDATE_DISABLED ? -ENODEV : 0;
979 static int mmap_kern(struct omapfb_mem_region *region)
981 struct vm_struct *kvma;
982 struct vm_area_struct vma;
986 kvma = get_vm_area(region->size, VM_IOREMAP);
988 dev_err(dispc.fbdev->dev, "can't get kernel vm area\n");
991 vma.vm_mm = &init_mm;
993 vaddr = (unsigned long)kvma->addr;
995 pgprot = pgprot_writecombine(pgprot_kernel);
996 vma.vm_start = vaddr;
997 vma.vm_end = vaddr + region->size;
998 if (io_remap_pfn_range(&vma, vaddr, region->paddr >> PAGE_SHIFT,
999 region->size, pgprot) < 0) {
1000 dev_err(dispc.fbdev->dev, "kernel mmap for FBMEM failed\n");
1003 region->vaddr = (void *)vaddr;
1008 static void mmap_user_open(struct vm_area_struct *vma)
1010 int plane = (int)vma->vm_private_data;
1012 atomic_inc(&dispc.map_count[plane]);
1015 static void mmap_user_close(struct vm_area_struct *vma)
1017 int plane = (int)vma->vm_private_data;
1019 atomic_dec(&dispc.map_count[plane]);
1022 static struct vm_operations_struct mmap_user_ops = {
1023 .open = mmap_user_open,
1024 .close = mmap_user_close,
1027 static int omap_dispc_mmap_user(struct fb_info *info,
1028 struct vm_area_struct *vma)
1030 struct omapfb_plane_struct *plane = info->par;
1032 unsigned long start;
1035 if (vma->vm_end - vma->vm_start == 0)
1037 if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
1039 off = vma->vm_pgoff << PAGE_SHIFT;
1041 start = info->fix.smem_start;
1042 len = info->fix.smem_len;
1045 if ((vma->vm_end - vma->vm_start + off) > len)
1048 vma->vm_pgoff = off >> PAGE_SHIFT;
1049 vma->vm_flags |= VM_IO | VM_RESERVED;
1050 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
1051 vma->vm_ops = &mmap_user_ops;
1052 vma->vm_private_data = (void *)plane->idx;
1053 if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
1054 vma->vm_end - vma->vm_start, vma->vm_page_prot))
1056 /* vm_ops.open won't be called for mmap itself. */
1057 atomic_inc(&dispc.map_count[plane->idx]);
1061 static void unmap_kern(struct omapfb_mem_region *region)
1063 vunmap(region->vaddr);
1066 static int alloc_palette_ram(void)
1068 dispc.palette_vaddr = dma_alloc_writecombine(dispc.fbdev->dev,
1069 MAX_PALETTE_SIZE, &dispc.palette_paddr, GFP_KERNEL);
1070 if (dispc.palette_vaddr == NULL) {
1071 dev_err(dispc.fbdev->dev, "failed to alloc palette memory\n");
1078 static void free_palette_ram(void)
1080 dma_free_writecombine(dispc.fbdev->dev, MAX_PALETTE_SIZE,
1081 dispc.palette_vaddr, dispc.palette_paddr);
1084 static int alloc_fbmem(struct omapfb_mem_region *region)
1086 region->vaddr = dma_alloc_writecombine(dispc.fbdev->dev,
1087 region->size, ®ion->paddr, GFP_KERNEL);
1089 if (region->vaddr == NULL) {
1090 dev_err(dispc.fbdev->dev, "unable to allocate FB DMA memory\n");
1097 static void free_fbmem(struct omapfb_mem_region *region)
1099 dma_free_writecombine(dispc.fbdev->dev, region->size,
1100 region->vaddr, region->paddr);
1103 static struct resmap *init_resmap(unsigned long start, size_t size)
1106 struct resmap *res_map;
1108 page_cnt = PAGE_ALIGN(size) / PAGE_SIZE;
1110 kzalloc(sizeof(struct resmap) + RESMAP_SIZE(page_cnt), GFP_KERNEL);
1111 if (res_map == NULL)
1113 res_map->start = start;
1114 res_map->page_cnt = page_cnt;
1115 res_map->map = (unsigned long *)(res_map + 1);
1119 static void cleanup_resmap(struct resmap *res_map)
1124 static inline int resmap_mem_type(unsigned long start)
1126 if (start >= OMAP2_SRAM_START &&
1127 start < OMAP2_SRAM_START + OMAP2_SRAM_SIZE)
1128 return OMAPFB_MEMTYPE_SRAM;
1130 return OMAPFB_MEMTYPE_SDRAM;
1133 static inline int resmap_page_reserved(struct resmap *res_map, unsigned page_nr)
1135 return *RESMAP_PTR(res_map, page_nr) & RESMAP_MASK(page_nr) ? 1 : 0;
1138 static inline void resmap_reserve_page(struct resmap *res_map, unsigned page_nr)
1140 BUG_ON(resmap_page_reserved(res_map, page_nr));
1141 *RESMAP_PTR(res_map, page_nr) |= RESMAP_MASK(page_nr);
1144 static inline void resmap_free_page(struct resmap *res_map, unsigned page_nr)
1146 BUG_ON(!resmap_page_reserved(res_map, page_nr));
1147 *RESMAP_PTR(res_map, page_nr) &= ~RESMAP_MASK(page_nr);
1150 static void resmap_reserve_region(unsigned long start, size_t size)
1153 struct resmap *res_map;
1154 unsigned start_page;
1159 mtype = resmap_mem_type(start);
1160 res_map = dispc.res_map[mtype];
1161 dev_dbg(dispc.fbdev->dev, "reserve mem type %d start %08lx size %d\n",
1162 mtype, start, size);
1163 start_page = (start - res_map->start) / PAGE_SIZE;
1164 end_page = start_page + PAGE_ALIGN(size) / PAGE_SIZE;
1165 for (i = start_page; i < end_page; i++)
1166 resmap_reserve_page(res_map, i);
1169 static void resmap_free_region(unsigned long start, size_t size)
1171 struct resmap *res_map;
1172 unsigned start_page;
1177 mtype = resmap_mem_type(start);
1178 res_map = dispc.res_map[mtype];
1179 dev_dbg(dispc.fbdev->dev, "free mem type %d start %08lx size %d\n",
1180 mtype, start, size);
1181 start_page = (start - res_map->start) / PAGE_SIZE;
1182 end_page = start_page + PAGE_ALIGN(size) / PAGE_SIZE;
1183 for (i = start_page; i < end_page; i++)
1184 resmap_free_page(res_map, i);
1187 static unsigned long resmap_alloc_region(int mtype, size_t size)
1191 unsigned start_page;
1192 unsigned long start;
1193 struct resmap *res_map = dispc.res_map[mtype];
1195 BUG_ON(mtype >= DISPC_MEMTYPE_NUM || res_map == NULL || !size);
1197 size = PAGE_ALIGN(size) / PAGE_SIZE;
1200 for (i = 0; i < res_map->page_cnt; i++) {
1201 if (resmap_page_reserved(res_map, i)) {
1204 } else if (++total == size)
1210 start = res_map->start + start_page * PAGE_SIZE;
1211 resmap_reserve_region(start, size * PAGE_SIZE);
1216 /* Note that this will only work for user mappings, we don't deal with
1217 * kernel mappings here, so fbcon will keep using the old region.
1219 static int omap_dispc_setup_mem(int plane, size_t size, int mem_type,
1220 unsigned long *paddr)
1222 struct omapfb_mem_region *rg;
1223 unsigned long new_addr = 0;
1225 if ((unsigned)plane > dispc.mem_desc.region_cnt)
1227 if (mem_type >= DISPC_MEMTYPE_NUM)
1229 if (dispc.res_map[mem_type] == NULL)
1231 rg = &dispc.mem_desc.region[plane];
1232 if (size == rg->size && mem_type == rg->type)
1234 if (atomic_read(&dispc.map_count[plane]))
1237 resmap_free_region(rg->paddr, rg->size);
1239 new_addr = resmap_alloc_region(mem_type, size);
1241 /* Reallocate old region. */
1242 resmap_reserve_region(rg->paddr, rg->size);
1246 rg->paddr = new_addr;
1248 rg->type = mem_type;
1255 static int setup_fbmem(struct omapfb_mem_desc *req_md)
1257 struct omapfb_mem_region *rg;
1260 unsigned long mem_start[DISPC_MEMTYPE_NUM];
1261 unsigned long mem_end[DISPC_MEMTYPE_NUM];
1263 if (!req_md->region_cnt) {
1264 dev_err(dispc.fbdev->dev, "no memory regions defined\n");
1268 rg = &req_md->region[0];
1269 memset(mem_start, 0xff, sizeof(mem_start));
1270 memset(mem_end, 0, sizeof(mem_end));
1272 for (i = 0; i < req_md->region_cnt; i++, rg++) {
1276 if (rg->vaddr == NULL) {
1278 if ((r = mmap_kern(rg)) < 0)
1282 if (rg->type != OMAPFB_MEMTYPE_SDRAM) {
1283 dev_err(dispc.fbdev->dev,
1284 "unsupported memory type\n");
1287 rg->alloc = rg->map = 1;
1288 if ((r = alloc_fbmem(rg)) < 0)
1293 if (rg->paddr < mem_start[mtype])
1294 mem_start[mtype] = rg->paddr;
1295 if (rg->paddr + rg->size > mem_end[mtype])
1296 mem_end[mtype] = rg->paddr + rg->size;
1299 for (i = 0; i < DISPC_MEMTYPE_NUM; i++) {
1300 unsigned long start;
1302 if (mem_end[i] == 0)
1304 start = mem_start[i];
1305 size = mem_end[i] - start;
1306 dispc.res_map[i] = init_resmap(start, size);
1308 if (dispc.res_map[i] == NULL)
1310 /* Initial state is that everything is reserved. This
1311 * includes possible holes as well, which will never be
1314 resmap_reserve_region(start, size);
1317 dispc.mem_desc = *req_md;
1321 for (i = 0; i < DISPC_MEMTYPE_NUM; i++) {
1322 if (dispc.res_map[i] != NULL)
1323 cleanup_resmap(dispc.res_map[i]);
1328 static void cleanup_fbmem(void)
1330 struct omapfb_mem_region *rg;
1333 for (i = 0; i < DISPC_MEMTYPE_NUM; i++) {
1334 if (dispc.res_map[i] != NULL)
1335 cleanup_resmap(dispc.res_map[i]);
1337 rg = &dispc.mem_desc.region[0];
1338 for (i = 0; i < dispc.mem_desc.region_cnt; i++, rg++) {
1348 static int omap_dispc_init(struct omapfb_device *fbdev, int ext_mode,
1349 struct omapfb_mem_desc *req_vram)
1353 struct lcd_panel *panel = fbdev->panel;
1358 memset(&dispc, 0, sizeof(dispc));
1360 dispc.base = io_p2v(DISPC_BASE);
1361 dispc.fbdev = fbdev;
1362 dispc.ext_mode = ext_mode;
1364 init_completion(&dispc.frame_done);
1366 if ((r = get_dss_clocks()) < 0)
1369 enable_interface_clocks(1);
1370 enable_lcd_clocks(1);
1372 #ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT
1373 l = dispc_read_reg(DISPC_CONTROL);
1376 pr_info("omapfb: skipping hardware initialization\n");
1382 /* Reset monitoring works only w/ the 54M clk */
1383 enable_digit_clocks(1);
1386 MOD_REG_FLD(DISPC_SYSCONFIG, 1 << 1, 1 << 1);
1388 while (!(dispc_read_reg(DISPC_SYSSTATUS) & 1)) {
1390 dev_err(dispc.fbdev->dev, "soft reset failed\n");
1392 enable_digit_clocks(0);
1397 enable_digit_clocks(0);
1400 /* Enable smart idle and autoidle */
1401 l = dispc_read_reg(DISPC_CONTROL);
1402 l &= ~((3 << 12) | (3 << 3));
1403 l |= (2 << 12) | (2 << 3) | (1 << 0);
1404 dispc_write_reg(DISPC_SYSCONFIG, l);
1405 omap_writel(1 << 0, DSS_BASE + DSS_SYSCONFIG);
1407 /* Set functional clock autogating */
1408 l = dispc_read_reg(DISPC_CONFIG);
1410 dispc_write_reg(DISPC_CONFIG, l);
1412 l = dispc_read_reg(DISPC_IRQSTATUS);
1413 dispc_write_reg(l, DISPC_IRQSTATUS);
1415 /* Enable those that we handle always */
1416 omap_dispc_enable_irqs(DISPC_IRQ_FRAMEMASK);
1418 if ((r = request_irq(INT_24XX_DSS_IRQ, omap_dispc_irq_handler,
1419 0, MODULE_NAME, fbdev)) < 0) {
1420 dev_err(dispc.fbdev->dev, "can't get DSS IRQ\n");
1424 /* L3 firewall setting: enable access to OCM RAM */
1425 __raw_writel(0x402000b0, io_p2v(0x680050a0));
1427 if ((r = alloc_palette_ram()) < 0)
1430 if ((r = setup_fbmem(req_vram)) < 0)
1434 for (i = 0; i < dispc.mem_desc.region_cnt; i++) {
1435 memset(dispc.mem_desc.region[i].vaddr, 0,
1436 dispc.mem_desc.region[i].size);
1439 /* Set logic clock to fck, pixel clock to fck/2 for now */
1440 MOD_REG_FLD(DISPC_DIVISOR, FLD_MASK(16, 8), 1 << 16);
1441 MOD_REG_FLD(DISPC_DIVISOR, FLD_MASK(0, 8), 2 << 0);
1443 setup_plane_fifo(0, ext_mode);
1444 setup_plane_fifo(1, ext_mode);
1445 setup_plane_fifo(2, ext_mode);
1447 setup_color_conv_coef();
1449 set_lcd_tft_mode(panel->config & OMAP_LCDC_PANEL_TFT);
1450 set_load_mode(DISPC_LOAD_FRAME_ONLY);
1453 set_lcd_data_lines(panel->data_lines);
1454 omap_dispc_set_lcd_size(panel->x_res, panel->y_res);
1457 set_lcd_data_lines(panel->bpp);
1458 enable_rfbi_mode(ext_mode);
1461 l = dispc_read_reg(DISPC_REVISION);
1462 pr_info("omapfb: DISPC version %d.%d initialized\n",
1463 l >> 4 & 0x0f, l & 0x0f);
1464 enable_lcd_clocks(0);
1470 free_irq(INT_24XX_DSS_IRQ, fbdev);
1472 enable_lcd_clocks(0);
1473 enable_interface_clocks(0);
1479 static void omap_dispc_cleanup(void)
1483 omap_dispc_set_update_mode(OMAPFB_UPDATE_DISABLED);
1484 /* This will also disable clocks that are on */
1485 for (i = 0; i < dispc.mem_desc.region_cnt; i++)
1486 omap_dispc_enable_plane(i, 0);
1489 free_irq(INT_24XX_DSS_IRQ, dispc.fbdev);
1490 enable_interface_clocks(0);
1494 const struct lcd_ctrl omap2_int_ctrl = {
1496 .init = omap_dispc_init,
1497 .cleanup = omap_dispc_cleanup,
1498 .get_caps = omap_dispc_get_caps,
1499 .set_update_mode = omap_dispc_set_update_mode,
1500 .get_update_mode = omap_dispc_get_update_mode,
1501 .update_window = omap_dispc_update_window,
1502 .suspend = omap_dispc_suspend,
1503 .resume = omap_dispc_resume,
1504 .setup_plane = omap_dispc_setup_plane,
1505 .setup_mem = omap_dispc_setup_mem,
1506 .set_scale = omap_dispc_set_scale,
1507 .enable_plane = omap_dispc_enable_plane,
1508 .set_color_key = omap_dispc_set_color_key,
1509 .get_color_key = omap_dispc_get_color_key,
1510 .mmap = omap_dispc_mmap_user,