2 * linux/drivers/video/nvidia/nvidia.c - nVidia fb driver
4 * Copyright 2004 Antonino Daplas <adaplas@pol.net>
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
12 #include <linux/config.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/errno.h>
16 #include <linux/string.h>
18 #include <linux/tty.h>
19 #include <linux/slab.h>
20 #include <linux/delay.h>
22 #include <linux/init.h>
23 #include <linux/pci.h>
29 #include <asm/pci-bridge.h>
31 #ifdef CONFIG_PMAC_BACKLIGHT
32 #include <asm/backlight.h>
40 #ifndef CONFIG_PCI /* sanity check */
41 #error This driver requires PCI support.
44 #undef CONFIG_FB_NVIDIA_DEBUG
45 #ifdef CONFIG_FB_NVIDIA_DEBUG
46 #define NVTRACE printk
48 #define NVTRACE if (0) printk
51 #define NVTRACE_ENTER(...) NVTRACE("%s START\n", __FUNCTION__)
52 #define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __FUNCTION__)
54 #ifdef CONFIG_FB_NVIDIA_DEBUG
55 #define assert(expr) \
57 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
58 #expr,__FILE__,__FUNCTION__,__LINE__); \
65 #define PFX "nvidiafb: "
67 /* HW cursor parameters */
70 static struct pci_device_id nvidiafb_pci_tbl[] = {
71 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT,
72 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
73 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2,
74 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
75 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2,
76 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
77 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT_UNKNOWN,
78 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
79 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2,
80 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
81 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2,
82 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
83 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2,
84 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
85 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR,
86 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
87 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR,
88 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
89 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO,
90 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
91 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX,
92 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
93 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2,
94 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
95 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,
96 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
97 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR,
98 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
99 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS,
100 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
101 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2,
102 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
103 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA,
104 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
105 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,
106 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
107 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460,
108 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
109 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440,
110 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
111 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420,
112 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
113 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_SE,
114 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
115 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO,
116 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
117 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO,
118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
119 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_460_GO,
120 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
121 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32,
122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
123 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL,
124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
125 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64,
126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
127 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200,
128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
129 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
131 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL,
132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
133 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_410_GO_M16,
134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
135 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_8X,
136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
137 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440SE_8X,
138 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
139 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420_8X,
140 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
141 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_448_GO,
142 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
143 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_488_GO,
144 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
145 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_580_XGL,
146 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
147 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_MAC,
148 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
149 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_280_NVS,
150 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
151 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_380_XGL,
152 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
153 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2,
154 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
155 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,
156 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
157 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,
158 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
159 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,
160 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
161 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,
162 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
163 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600,
164 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
165 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400,
166 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
167 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200,
168 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
169 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL,
170 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
171 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL,
172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
173 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL,
174 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
175 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800,
176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
177 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800_8X,
178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
179 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800SE,
180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
181 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_4200_GO,
182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
183 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_980_XGL,
184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
185 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_780_XGL,
186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
187 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700_GOGL,
188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
189 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800_ULTRA,
190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
191 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800,
192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
193 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_2000,
194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
195 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1000,
196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
197 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600_ULTRA,
198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
199 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600,
200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
201 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600SE,
202 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
203 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5600,
204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
205 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5650,
206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
207 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO700,
208 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
209 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200,
210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
211 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_ULTRA,
212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
213 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_1,
214 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
215 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200SE,
216 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
217 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5200,
218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
219 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250,
220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
221 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250_32,
222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
223 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200,
224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
225 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_NVS_280_PCI,
226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
227 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_500,
228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
229 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5300,
230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
231 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5100,
232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
233 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900_ULTRA,
234 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
235 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900,
236 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
237 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900XT,
238 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
239 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5950_ULTRA,
240 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
241 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_3000,
242 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
243 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700_ULTRA,
244 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
245 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700,
246 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
247 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700LE,
248 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
249 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700VE,
250 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
251 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_1,
252 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
253 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_2,
254 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
255 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO1000,
256 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
257 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1100,
258 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
259 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5500,
260 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
261 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5100,
262 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
263 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_700,
264 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
265 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900ZT,
266 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
267 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_ULTRA,
268 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
269 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800,
270 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
271 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_LE,
272 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
273 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_GT,
274 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
275 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_4000,
276 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
277 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6600_GT,
278 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
279 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6600,
280 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
281 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6610_XL,
282 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
283 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_540,
284 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
285 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6200,
286 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
287 {PCI_VENDOR_ID_NVIDIA, 0x0252,
288 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
289 {PCI_VENDOR_ID_NVIDIA, 0x0313,
290 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
291 {PCI_VENDOR_ID_NVIDIA, 0x0316,
292 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
293 {PCI_VENDOR_ID_NVIDIA, 0x0317,
294 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
295 {PCI_VENDOR_ID_NVIDIA, 0x031D,
296 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
297 {PCI_VENDOR_ID_NVIDIA, 0x031E,
298 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
299 {PCI_VENDOR_ID_NVIDIA, 0x031F,
300 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
301 {PCI_VENDOR_ID_NVIDIA, 0x0329,
302 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
303 {PCI_VENDOR_ID_NVIDIA, 0x032F,
304 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
305 {PCI_VENDOR_ID_NVIDIA, 0x0345,
306 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
307 {PCI_VENDOR_ID_NVIDIA, 0x0349,
308 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
309 {PCI_VENDOR_ID_NVIDIA, 0x034B,
310 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
311 {PCI_VENDOR_ID_NVIDIA, 0x034F,
312 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
313 {PCI_VENDOR_ID_NVIDIA, 0x00c0,
314 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
315 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_6800A,
316 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
317 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_6800A_LE,
318 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
319 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_GO_6800,
320 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
321 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_GO_6800_ULTRA,
322 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
323 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_QUADRO_FX_GO1400,
324 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
325 {PCI_VENDOR_ID_NVIDIA, 0x00cd,
326 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
327 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_QUADRO_FX_1400,
328 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
329 {PCI_VENDOR_ID_NVIDIA, 0x0142,
330 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
331 {PCI_VENDOR_ID_NVIDIA, 0x0143,
332 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
333 {PCI_VENDOR_ID_NVIDIA, 0x0144,
334 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
335 {PCI_VENDOR_ID_NVIDIA, 0x0145,
336 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
337 {PCI_VENDOR_ID_NVIDIA, 0x0146,
338 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
339 {PCI_VENDOR_ID_NVIDIA, 0x0147,
340 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
341 {PCI_VENDOR_ID_NVIDIA, 0x0148,
342 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
343 {PCI_VENDOR_ID_NVIDIA, 0x0149,
344 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
345 {PCI_VENDOR_ID_NVIDIA, 0x014b,
346 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
347 {PCI_VENDOR_ID_NVIDIA, 0x14c,
348 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
349 {PCI_VENDOR_ID_NVIDIA, 0x014d,
350 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
351 {PCI_VENDOR_ID_NVIDIA, 0x0160,
352 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
353 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6200_TURBOCACHE,
354 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
355 {PCI_VENDOR_ID_NVIDIA, 0x0162,
356 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
357 {PCI_VENDOR_ID_NVIDIA, 0x0163,
358 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
359 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200,
360 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
361 {PCI_VENDOR_ID_NVIDIA, 0x0165,
362 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
363 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250,
364 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
365 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200_1,
366 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
367 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250_1,
368 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
369 {PCI_VENDOR_ID_NVIDIA, 0x0169,
370 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
371 {PCI_VENDOR_ID_NVIDIA, 0x016b,
372 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
373 {PCI_VENDOR_ID_NVIDIA, 0x016c,
374 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
375 {PCI_VENDOR_ID_NVIDIA, 0x016d,
376 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
377 {PCI_VENDOR_ID_NVIDIA, 0x016e,
378 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
379 {PCI_VENDOR_ID_NVIDIA, 0x0210,
380 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
381 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B,
382 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
383 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_LE,
384 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
385 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_GT,
386 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
387 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_7800_GT,
388 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
389 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_7800_GTX,
390 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
391 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_7800,
392 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
393 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_7800_GTX,
394 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
395 {PCI_VENDOR_ID_NVIDIA, 0x021d,
396 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
397 {PCI_VENDOR_ID_NVIDIA, 0x021e,
398 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
399 {PCI_VENDOR_ID_NVIDIA, 0x0220,
400 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
401 {PCI_VENDOR_ID_NVIDIA, 0x0221,
402 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
403 {PCI_VENDOR_ID_NVIDIA, 0x0222,
404 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
405 {PCI_VENDOR_ID_NVIDIA, 0x0228,
406 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
407 {0,} /* terminate list */
410 MODULE_DEVICE_TABLE(pci, nvidiafb_pci_tbl);
412 /* command line data, set in nvidiafb_setup() */
413 static int flatpanel __devinitdata = -1; /* Autodetect later */
414 static int forceCRTC __devinitdata = -1;
415 static int hwcur __devinitdata = 0;
416 static int noaccel __devinitdata = 0;
417 static int noscale __devinitdata = 0;
418 static int paneltweak __devinitdata = 0;
419 static int vram __devinitdata = 0;
421 static int nomtrr __devinitdata = 0;
424 static char *mode_option __devinitdata = NULL;
426 static struct fb_fix_screeninfo __devinitdata nvidiafb_fix = {
427 .type = FB_TYPE_PACKED_PIXELS,
432 static struct fb_var_screeninfo __devinitdata nvidiafb_default_var = {
442 .activate = FB_ACTIVATE_NOW,
452 .vmode = FB_VMODE_NONINTERLACED
458 #ifdef CONFIG_PMAC_BACKLIGHT
460 static int nvidia_backlight_levels[] = {
479 /* ------------------------------------------------------------------------- *
481 * Backlight operations
483 * ------------------------------------------------------------------------- */
485 static int nvidia_set_backlight_enable(int on, int level, void *data)
487 struct nvidia_par *par = (struct nvidia_par *)data;
488 u32 tmp_pcrt, tmp_pmc, fpcontrol;
490 tmp_pmc = NV_RD32(par->PMC, 0x10F0) & 0x0000FFFF;
491 tmp_pcrt = NV_RD32(par->PCRTC0, 0x081C) & 0xFFFFFFFC;
492 fpcontrol = NV_RD32(par->PRAMDAC, 0x0848) & 0xCFFFFFCC;
494 if (on && (level > BACKLIGHT_OFF)) {
496 tmp_pmc |= (1 << 31); // backlight bit
497 tmp_pmc |= nvidia_backlight_levels[level - 1] << 16;
501 fpcontrol |= par->fpSyncs;
503 fpcontrol |= 0x20000022;
505 NV_WR32(par->PCRTC0, 0x081C, tmp_pcrt);
506 NV_WR32(par->PMC, 0x10F0, tmp_pmc);
507 NV_WR32(par->PRAMDAC, 0x848, fpcontrol);
512 static int nvidia_set_backlight_level(int level, void *data)
514 return nvidia_set_backlight_enable(1, level, data);
517 static struct backlight_controller nvidia_backlight_controller = {
518 nvidia_set_backlight_enable,
519 nvidia_set_backlight_level
522 #endif /* CONFIG_PMAC_BACKLIGHT */
524 static void nvidiafb_load_cursor_image(struct nvidia_par *par, u8 * data8,
525 u16 bg, u16 fg, u32 w, u32 h)
527 u32 *data = (u32 *) data8;
533 for (i = 0; i < h; i++) {
537 for (j = 0; j < w / 2; j++) {
539 #if defined (__BIG_ENDIAN)
540 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
542 tmp |= (b & (1 << 31)) ? fg : bg;
545 tmp = (b & 1) ? fg : bg;
547 tmp |= (b & 1) ? fg << 16 : bg << 16;
550 NV_WR32(&par->CURSOR[k++], 0, tmp);
552 k += (MAX_CURS - w) / 2;
556 static void nvidia_write_clut(struct nvidia_par *par,
557 u8 regnum, u8 red, u8 green, u8 blue)
559 NVWriteDacMask(par, 0xff);
560 NVWriteDacWriteAddr(par, regnum);
561 NVWriteDacData(par, red);
562 NVWriteDacData(par, green);
563 NVWriteDacData(par, blue);
566 static void nvidia_read_clut(struct nvidia_par *par,
567 u8 regnum, u8 * red, u8 * green, u8 * blue)
569 NVWriteDacMask(par, 0xff);
570 NVWriteDacReadAddr(par, regnum);
571 *red = NVReadDacData(par);
572 *green = NVReadDacData(par);
573 *blue = NVReadDacData(par);
576 static int nvidia_panel_tweak(struct nvidia_par *par,
577 struct _riva_hw_state *state)
581 if (par->paneltweak) {
582 tweak = par->paneltweak;
584 /* begin flat panel hacks */
585 /* This is unfortunate, but some chips need this register
586 tweaked or else you get artifacts where adjacent pixels are
587 swapped. There are no hard rules for what to set here so all
588 we can do is experiment and apply hacks. */
590 if(((par->Chipset & 0xffff) == 0x0328) && (state->bpp == 32)) {
591 /* At least one NV34 laptop needs this workaround. */
595 if((par->Chipset & 0xfff0) == 0x0310) {
598 /* end flat panel hacks */
604 static void nvidia_save_vga(struct nvidia_par *par,
605 struct _riva_hw_state *state)
610 NVLockUnlock(par, 0);
612 NVUnloadStateExt(par, state);
614 state->misc_output = NVReadMiscOut(par);
616 for (i = 0; i < NUM_CRT_REGS; i++)
617 state->crtc[i] = NVReadCrtc(par, i);
619 for (i = 0; i < NUM_ATC_REGS; i++)
620 state->attr[i] = NVReadAttr(par, i);
622 for (i = 0; i < NUM_GRC_REGS; i++)
623 state->gra[i] = NVReadGr(par, i);
625 for (i = 0; i < NUM_SEQ_REGS; i++)
626 state->seq[i] = NVReadSeq(par, i);
632 static void nvidia_write_regs(struct nvidia_par *par)
634 struct _riva_hw_state *state = &par->ModeReg;
639 NVLoadStateExt(par, state);
641 NVWriteMiscOut(par, state->misc_output);
643 for (i = 1; i < NUM_SEQ_REGS; i++) {
645 printk(" SEQ[%02x] = %08x\n", i, state->seq[i]);
647 NVWriteSeq(par, i, state->seq[i]);
650 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */
651 NVWriteCrtc(par, 0x11, state->crtc[0x11] & ~0x80);
653 for (i = 0; i < NUM_CRT_REGS; i++) {
660 printk("CRTC[%02x] = %08x\n", i, state->crtc[i]);
662 NVWriteCrtc(par, i, state->crtc[i]);
666 for (i = 0; i < NUM_GRC_REGS; i++) {
668 printk(" GRA[%02x] = %08x\n", i, state->gra[i]);
670 NVWriteGr(par, i, state->gra[i]);
673 for (i = 0; i < NUM_ATC_REGS; i++) {
675 printk("ATTR[%02x] = %08x\n", i, state->attr[i]);
677 NVWriteAttr(par, i, state->attr[i]);
683 static void nvidia_vga_protect(struct nvidia_par *par, int on)
689 * Turn off screen and disable sequencer.
691 tmp = NVReadSeq(par, 0x01);
693 NVWriteSeq(par, 0x00, 0x01); /* Synchronous Reset */
694 NVWriteSeq(par, 0x01, tmp | 0x20); /* disable the display */
697 * Reenable sequencer, then turn on screen.
700 tmp = NVReadSeq(par, 0x01);
702 NVWriteSeq(par, 0x01, tmp & ~0x20); /* reenable display */
703 NVWriteSeq(par, 0x00, 0x03); /* End Reset */
709 static int nvidia_calc_regs(struct fb_info *info)
711 struct nvidia_par *par = info->par;
712 struct _riva_hw_state *state = &par->ModeReg;
713 int i, depth = fb_get_color_depth(&info->var, &info->fix);
714 int h_display = info->var.xres / 8 - 1;
715 int h_start = (info->var.xres + info->var.right_margin) / 8 - 1;
716 int h_end = (info->var.xres + info->var.right_margin +
717 info->var.hsync_len) / 8 - 1;
718 int h_total = (info->var.xres + info->var.right_margin +
719 info->var.hsync_len + info->var.left_margin) / 8 - 5;
720 int h_blank_s = h_display;
721 int h_blank_e = h_total + 4;
722 int v_display = info->var.yres - 1;
723 int v_start = info->var.yres + info->var.lower_margin - 1;
724 int v_end = (info->var.yres + info->var.lower_margin +
725 info->var.vsync_len) - 1;
726 int v_total = (info->var.yres + info->var.lower_margin +
727 info->var.vsync_len + info->var.upper_margin) - 2;
728 int v_blank_s = v_display;
729 int v_blank_e = v_total + 1;
732 * Set all CRTC values.
735 if (info->var.vmode & FB_VMODE_INTERLACED)
738 if (par->FlatPanel == 1) {
739 v_start = v_total - 3;
742 h_start = h_total - 5;
744 h_blank_e = h_total + 4;
747 state->crtc[0x0] = Set8Bits(h_total);
748 state->crtc[0x1] = Set8Bits(h_display);
749 state->crtc[0x2] = Set8Bits(h_blank_s);
750 state->crtc[0x3] = SetBitField(h_blank_e, 4: 0, 4:0)
752 state->crtc[0x4] = Set8Bits(h_start);
753 state->crtc[0x5] = SetBitField(h_blank_e, 5: 5, 7:7)
754 | SetBitField(h_end, 4: 0, 4:0);
755 state->crtc[0x6] = SetBitField(v_total, 7: 0, 7:0);
756 state->crtc[0x7] = SetBitField(v_total, 8: 8, 0:0)
757 | SetBitField(v_display, 8: 8, 1:1)
758 | SetBitField(v_start, 8: 8, 2:2)
759 | SetBitField(v_blank_s, 8: 8, 3:3)
761 | SetBitField(v_total, 9: 9, 5:5)
762 | SetBitField(v_display, 9: 9, 6:6)
763 | SetBitField(v_start, 9: 9, 7:7);
764 state->crtc[0x9] = SetBitField(v_blank_s, 9: 9, 5:5)
766 | ((info->var.vmode & FB_VMODE_DOUBLE) ? 0x80 : 0x00);
767 state->crtc[0x10] = Set8Bits(v_start);
768 state->crtc[0x11] = SetBitField(v_end, 3: 0, 3:0) | SetBit(5);
769 state->crtc[0x12] = Set8Bits(v_display);
770 state->crtc[0x13] = ((info->var.xres_virtual / 8) *
771 (info->var.bits_per_pixel / 8));
772 state->crtc[0x15] = Set8Bits(v_blank_s);
773 state->crtc[0x16] = Set8Bits(v_blank_e);
775 state->attr[0x10] = 0x01;
778 state->attr[0x11] = 0x00;
780 state->screen = SetBitField(h_blank_e, 6: 6, 4:4)
781 | SetBitField(v_blank_s, 10: 10, 3:3)
782 | SetBitField(v_start, 10: 10, 2:2)
783 | SetBitField(v_display, 10: 10, 1:1)
784 | SetBitField(v_total, 10: 10, 0:0);
786 state->horiz = SetBitField(h_total, 8: 8, 0:0)
787 | SetBitField(h_display, 8: 8, 1:1)
788 | SetBitField(h_blank_s, 8: 8, 2:2)
789 | SetBitField(h_start, 8: 8, 3:3);
791 state->extra = SetBitField(v_total, 11: 11, 0:0)
792 | SetBitField(v_display, 11: 11, 2:2)
793 | SetBitField(v_start, 11: 11, 4:4)
794 | SetBitField(v_blank_s, 11: 11, 6:6);
796 if (info->var.vmode & FB_VMODE_INTERLACED) {
797 h_total = (h_total >> 1) & ~1;
798 state->interlace = Set8Bits(h_total);
799 state->horiz |= SetBitField(h_total, 8: 8, 4:4);
801 state->interlace = 0xff; /* interlace off */
805 * Calculate the extended registers.
813 if (par->Architecture >= NV_ARCH_10)
814 par->CURSOR = (volatile u32 __iomem *)(info->screen_base +
817 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
818 state->misc_output &= ~0x40;
820 state->misc_output |= 0x40;
821 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
822 state->misc_output &= ~0x80;
824 state->misc_output |= 0x80;
826 NVCalcStateExt(par, state, i, info->var.xres_virtual,
827 info->var.xres, info->var.yres_virtual,
828 1000000000 / info->var.pixclock, info->var.vmode);
830 state->scale = NV_RD32(par->PRAMDAC, 0x00000848) & 0xfff000ff;
831 if (par->FlatPanel == 1) {
832 state->pixel |= (1 << 7);
834 if (!par->fpScaler || (par->fpWidth <= info->var.xres)
835 || (par->fpHeight <= info->var.yres)) {
836 state->scale |= (1 << 8);
839 if (!par->crtcSync_read) {
840 state->crtcSync = NV_RD32(par->PRAMDAC, 0x0828);
841 par->crtcSync_read = 1;
844 par->PanelTweak = nvidia_panel_tweak(par, state);
847 state->vpll = state->pll;
848 state->vpll2 = state->pll;
849 state->vpllB = state->pllB;
850 state->vpll2B = state->pllB;
852 VGA_WR08(par->PCIO, 0x03D4, 0x1C);
853 state->fifo = VGA_RD08(par->PCIO, 0x03D5) & ~(1<<5);
855 if (par->CRTCnumber) {
856 state->head = NV_RD32(par->PCRTC0, 0x00000860) & ~0x00001000;
857 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) | 0x00001000;
858 state->crtcOwner = 3;
859 state->pllsel |= 0x20000800;
860 state->vpll = NV_RD32(par->PRAMDAC0, 0x00000508);
861 if (par->twoStagePLL)
862 state->vpllB = NV_RD32(par->PRAMDAC0, 0x00000578);
863 } else if (par->twoHeads) {
864 state->head = NV_RD32(par->PCRTC0, 0x00000860) | 0x00001000;
865 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) & ~0x00001000;
866 state->crtcOwner = 0;
867 state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520);
868 if (par->twoStagePLL)
869 state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C);
872 state->cursorConfig = 0x00000100;
874 if (info->var.vmode & FB_VMODE_DOUBLE)
875 state->cursorConfig |= (1 << 4);
877 if (par->alphaCursor) {
878 if ((par->Chipset & 0x0ff0) != 0x0110)
879 state->cursorConfig |= 0x04011000;
881 state->cursorConfig |= 0x14011000;
882 state->general |= (1 << 29);
884 state->cursorConfig |= 0x02000000;
887 if ((par->Chipset & 0x0ff0) == 0x0110) {
888 state->dither = NV_RD32(par->PRAMDAC, 0x0528) &
891 state->dither |= 0x00010000;
893 state->dither = NV_RD32(par->PRAMDAC, 0x083C) & ~1;
901 state->displayV = info->var.xres;
906 static void nvidia_init_vga(struct fb_info *info)
908 struct nvidia_par *par = info->par;
909 struct _riva_hw_state *state = &par->ModeReg;
912 for (i = 0; i < 0x10; i++)
914 state->attr[0x10] = 0x41;
915 state->attr[0x11] = 0xff;
916 state->attr[0x12] = 0x0f;
917 state->attr[0x13] = 0x00;
918 state->attr[0x14] = 0x00;
920 memset(state->crtc, 0x00, NUM_CRT_REGS);
921 state->crtc[0x0a] = 0x20;
922 state->crtc[0x17] = 0xe3;
923 state->crtc[0x18] = 0xff;
924 state->crtc[0x28] = 0x40;
926 memset(state->gra, 0x00, NUM_GRC_REGS);
927 state->gra[0x05] = 0x40;
928 state->gra[0x06] = 0x05;
929 state->gra[0x07] = 0x0f;
930 state->gra[0x08] = 0xff;
932 state->seq[0x00] = 0x03;
933 state->seq[0x01] = 0x01;
934 state->seq[0x02] = 0x0f;
935 state->seq[0x03] = 0x00;
936 state->seq[0x04] = 0x0e;
938 state->misc_output = 0xeb;
941 static int nvidiafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
943 struct nvidia_par *par = info->par;
944 u8 data[MAX_CURS * MAX_CURS / 8];
945 int i, set = cursor->set;
948 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
951 NVShowHideCursor(par, 0);
953 if (par->cursor_reset) {
955 par->cursor_reset = 0;
958 if (set & FB_CUR_SETSIZE)
959 memset_io(par->CURSOR, 0, MAX_CURS * MAX_CURS * 2);
961 if (set & FB_CUR_SETPOS) {
964 yy = cursor->image.dy - info->var.yoffset;
965 xx = cursor->image.dx - info->var.xoffset;
969 NV_WR32(par->PRAMDAC, 0x0000300, temp);
972 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
973 u32 bg_idx = cursor->image.bg_color;
974 u32 fg_idx = cursor->image.fg_color;
975 u32 s_pitch = (cursor->image.width + 7) >> 3;
976 u32 d_pitch = MAX_CURS / 8;
977 u8 *dat = (u8 *) cursor->image.data;
978 u8 *msk = (u8 *) cursor->mask;
981 src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC);
984 switch (cursor->rop) {
986 for (i = 0; i < s_pitch * cursor->image.height; i++)
987 src[i] = dat[i] ^ msk[i];
991 for (i = 0; i < s_pitch * cursor->image.height; i++)
992 src[i] = dat[i] & msk[i];
996 fb_pad_aligned_buffer(data, d_pitch, src, s_pitch,
997 cursor->image.height);
999 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
1000 ((info->cmap.green[bg_idx] & 0xf8) << 2) |
1001 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1 << 15;
1003 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
1004 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
1005 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15;
1007 NVLockUnlock(par, 0);
1009 nvidiafb_load_cursor_image(par, data, bg, fg,
1010 cursor->image.width,
1011 cursor->image.height);
1017 NVShowHideCursor(par, 1);
1022 static int nvidiafb_set_par(struct fb_info *info)
1024 struct nvidia_par *par = info->par;
1028 NVLockUnlock(par, 1);
1029 if (!par->FlatPanel || (info->var.bits_per_pixel != 24) ||
1033 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1034 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1036 nvidia_init_vga(info);
1037 nvidia_calc_regs(info);
1039 NVLockUnlock(par, 0);
1040 if (par->twoHeads) {
1041 VGA_WR08(par->PCIO, 0x03D4, 0x44);
1042 VGA_WR08(par->PCIO, 0x03D5, par->ModeReg.crtcOwner);
1043 NVLockUnlock(par, 0);
1046 nvidia_vga_protect(par, 1);
1048 nvidia_write_regs(par);
1050 #if defined (__BIG_ENDIAN)
1051 /* turn on LFB swapping */
1055 VGA_WR08(par->PCIO, 0x3d4, 0x46);
1056 tmp = VGA_RD08(par->PCIO, 0x3d5);
1058 VGA_WR08(par->PCIO, 0x3d5, tmp);
1062 info->fix.line_length = (info->var.xres_virtual *
1063 info->var.bits_per_pixel) >> 3;
1064 if (info->var.accel_flags) {
1065 info->fbops->fb_imageblit = nvidiafb_imageblit;
1066 info->fbops->fb_fillrect = nvidiafb_fillrect;
1067 info->fbops->fb_copyarea = nvidiafb_copyarea;
1068 info->fbops->fb_sync = nvidiafb_sync;
1069 info->pixmap.scan_align = 4;
1070 info->flags &= ~FBINFO_HWACCEL_DISABLED;
1071 NVResetGraphics(info);
1073 info->fbops->fb_imageblit = cfb_imageblit;
1074 info->fbops->fb_fillrect = cfb_fillrect;
1075 info->fbops->fb_copyarea = cfb_copyarea;
1076 info->fbops->fb_sync = NULL;
1077 info->pixmap.scan_align = 1;
1078 info->flags |= FBINFO_HWACCEL_DISABLED;
1081 par->cursor_reset = 1;
1083 nvidia_vga_protect(par, 0);
1089 static int nvidiafb_setcolreg(unsigned regno, unsigned red, unsigned green,
1090 unsigned blue, unsigned transp,
1091 struct fb_info *info)
1093 struct nvidia_par *par = info->par;
1097 if (regno >= (1 << info->var.green.length))
1100 if (info->var.grayscale) {
1101 /* gray = 0.30*R + 0.59*G + 0.11*B */
1102 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
1105 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1106 ((u32 *) info->pseudo_palette)[regno] =
1107 (regno << info->var.red.offset) |
1108 (regno << info->var.green.offset) |
1109 (regno << info->var.blue.offset);
1112 switch (info->var.bits_per_pixel) {
1114 /* "transparent" stuff is completely ignored. */
1115 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
1118 if (info->var.green.length == 5) {
1119 for (i = 0; i < 8; i++) {
1120 nvidia_write_clut(par, regno * 8 + i, red >> 8,
1121 green >> 8, blue >> 8);
1127 for (i = 0; i < 8; i++) {
1128 nvidia_write_clut(par, regno * 8 + i,
1129 red >> 8, green >> 8,
1134 nvidia_read_clut(par, regno * 4, &r, &g, &b);
1136 for (i = 0; i < 4; i++)
1137 nvidia_write_clut(par, regno * 4 + i, r,
1142 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
1153 static int nvidiafb_check_var(struct fb_var_screeninfo *var,
1154 struct fb_info *info)
1156 struct nvidia_par *par = info->par;
1157 int memlen, vramlen, mode_valid = 0;
1162 var->transp.offset = 0;
1163 var->transp.length = 0;
1167 if (var->bits_per_pixel <= 8)
1168 var->bits_per_pixel = 8;
1169 else if (var->bits_per_pixel <= 16)
1170 var->bits_per_pixel = 16;
1172 var->bits_per_pixel = 32;
1174 switch (var->bits_per_pixel) {
1176 var->red.offset = 0;
1177 var->red.length = 8;
1178 var->green.offset = 0;
1179 var->green.length = 8;
1180 var->blue.offset = 0;
1181 var->blue.length = 8;
1182 var->transp.offset = 0;
1183 var->transp.length = 0;
1186 var->green.length = (var->green.length < 6) ? 5 : 6;
1187 var->red.length = 5;
1188 var->blue.length = 5;
1189 var->transp.length = 6 - var->green.length;
1190 var->blue.offset = 0;
1191 var->green.offset = 5;
1192 var->red.offset = 5 + var->green.length;
1193 var->transp.offset = (5 + var->red.offset) & 15;
1195 case 32: /* RGBA 8888 */
1196 var->red.offset = 16;
1197 var->red.length = 8;
1198 var->green.offset = 8;
1199 var->green.length = 8;
1200 var->blue.offset = 0;
1201 var->blue.length = 8;
1202 var->transp.length = 8;
1203 var->transp.offset = 24;
1207 var->red.msb_right = 0;
1208 var->green.msb_right = 0;
1209 var->blue.msb_right = 0;
1210 var->transp.msb_right = 0;
1212 if (!info->monspecs.hfmax || !info->monspecs.vfmax ||
1213 !info->monspecs.dclkmax || !fb_validate_mode(var, info))
1216 /* calculate modeline if supported by monitor */
1217 if (!mode_valid && info->monspecs.gtf) {
1218 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
1223 struct fb_videomode *mode;
1225 mode = fb_find_best_mode(var, &info->modelist);
1227 fb_videomode_to_var(var, mode);
1232 if (!mode_valid && info->monspecs.modedb_len)
1235 if (par->fpWidth && par->fpHeight && (par->fpWidth < var->xres ||
1236 par->fpHeight < var->yres))
1239 if (var->yres_virtual < var->yres)
1240 var->yres_virtual = var->yres;
1242 if (var->xres_virtual < var->xres)
1243 var->xres_virtual = var->xres;
1245 var->xres_virtual = (var->xres_virtual + 63) & ~63;
1247 vramlen = info->screen_size;
1248 pitch = ((var->xres_virtual * var->bits_per_pixel) + 7) / 8;
1249 memlen = pitch * var->yres_virtual;
1251 if (memlen > vramlen) {
1252 var->yres_virtual = vramlen / pitch;
1254 if (var->yres_virtual < var->yres) {
1255 var->yres_virtual = var->yres;
1256 var->xres_virtual = vramlen / var->yres_virtual;
1257 var->xres_virtual /= var->bits_per_pixel / 8;
1258 var->xres_virtual &= ~63;
1259 pitch = (var->xres_virtual *
1260 var->bits_per_pixel + 7) / 8;
1261 memlen = pitch * var->yres;
1263 if (var->xres_virtual < var->xres) {
1264 printk("nvidiafb: required video memory, "
1265 "%d bytes, for %dx%d-%d (virtual) "
1266 "is out of range\n",
1267 memlen, var->xres_virtual,
1268 var->yres_virtual, var->bits_per_pixel);
1274 if (var->accel_flags) {
1275 if (var->yres_virtual > 0x7fff)
1276 var->yres_virtual = 0x7fff;
1277 if (var->xres_virtual > 0x7fff)
1278 var->xres_virtual = 0x7fff;
1281 var->xres_virtual &= ~63;
1288 static int nvidiafb_pan_display(struct fb_var_screeninfo *var,
1289 struct fb_info *info)
1291 struct nvidia_par *par = info->par;
1294 total = info->var.yoffset * info->fix.line_length + info->var.xoffset;
1296 NVSetStartAddress(par, total);
1301 static int nvidiafb_blank(int blank, struct fb_info *info)
1303 struct nvidia_par *par = info->par;
1304 unsigned char tmp, vesa;
1306 tmp = NVReadSeq(par, 0x01) & ~0x20; /* screen on/off */
1307 vesa = NVReadCrtc(par, 0x1a) & ~0xc0; /* sync on/off */
1315 case FB_BLANK_UNBLANK:
1316 case FB_BLANK_NORMAL:
1318 case FB_BLANK_VSYNC_SUSPEND:
1321 case FB_BLANK_HSYNC_SUSPEND:
1324 case FB_BLANK_POWERDOWN:
1329 NVWriteSeq(par, 0x01, tmp);
1330 NVWriteCrtc(par, 0x1a, vesa);
1332 #ifdef CONFIG_PMAC_BACKLIGHT
1333 if (par->FlatPanel && _machine == _MACH_Pmac) {
1334 set_backlight_enable(!blank);
1343 static struct fb_ops nvidia_fb_ops = {
1344 .owner = THIS_MODULE,
1345 .fb_check_var = nvidiafb_check_var,
1346 .fb_set_par = nvidiafb_set_par,
1347 .fb_setcolreg = nvidiafb_setcolreg,
1348 .fb_pan_display = nvidiafb_pan_display,
1349 .fb_blank = nvidiafb_blank,
1350 .fb_fillrect = nvidiafb_fillrect,
1351 .fb_copyarea = nvidiafb_copyarea,
1352 .fb_imageblit = nvidiafb_imageblit,
1353 .fb_cursor = nvidiafb_cursor,
1354 .fb_sync = nvidiafb_sync,
1357 static int __devinit nvidia_set_fbinfo(struct fb_info *info)
1359 struct fb_monspecs *specs = &info->monspecs;
1360 struct fb_videomode modedb;
1361 struct nvidia_par *par = info->par;
1365 info->flags = FBINFO_DEFAULT
1366 | FBINFO_HWACCEL_IMAGEBLIT
1367 | FBINFO_HWACCEL_FILLRECT
1368 | FBINFO_HWACCEL_COPYAREA
1369 | FBINFO_HWACCEL_YPAN;
1371 fb_videomode_to_modelist(info->monspecs.modedb,
1372 info->monspecs.modedb_len, &info->modelist);
1373 fb_var_to_videomode(&modedb, &nvidiafb_default_var);
1375 if (specs->modedb != NULL) {
1376 /* get preferred timing */
1377 if (specs->misc & FB_MISC_1ST_DETAIL) {
1380 for (i = 0; i < specs->modedb_len; i++) {
1381 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
1382 modedb = specs->modedb[i];
1387 /* otherwise, get first mode in database */
1388 modedb = specs->modedb[0];
1391 fb_videomode_to_var(&nvidiafb_default_var, &modedb);
1392 nvidiafb_default_var.bits_per_pixel = 8;
1393 } else if (par->fpWidth && par->fpHeight) {
1397 snprintf(buf, 15, "%dx%dMR", par->fpWidth, par->fpHeight);
1398 fb_find_mode(&nvidiafb_default_var, info, buf, specs->modedb,
1399 specs->modedb_len, &modedb, 8);
1403 fb_find_mode(&nvidiafb_default_var, info, mode_option,
1404 specs->modedb, specs->modedb_len, &modedb, 8);
1406 info->var = nvidiafb_default_var;
1407 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1408 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1409 info->pseudo_palette = par->pseudo_palette;
1410 fb_alloc_cmap(&info->cmap, 256, 0);
1411 fb_destroy_modedb(info->monspecs.modedb);
1412 info->monspecs.modedb = NULL;
1414 /* maximize virtual vertical length */
1415 lpitch = info->var.xres_virtual *
1416 ((info->var.bits_per_pixel + 7) >> 3);
1417 info->var.yres_virtual = info->screen_size / lpitch;
1419 info->pixmap.scan_align = 4;
1420 info->pixmap.buf_align = 4;
1421 info->pixmap.access_align = 32;
1422 info->pixmap.size = 8 * 1024;
1423 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1426 info->fbops->fb_cursor = soft_cursor;
1428 info->var.accel_flags = (!noaccel);
1430 switch (par->Architecture) {
1432 info->fix.accel = FB_ACCEL_NV4;
1435 info->fix.accel = FB_ACCEL_NV_10;
1438 info->fix.accel = FB_ACCEL_NV_20;
1441 info->fix.accel = FB_ACCEL_NV_30;
1444 info->fix.accel = FB_ACCEL_NV_40;
1450 return nvidiafb_check_var(&info->var, info);
1453 static u32 __devinit nvidia_get_arch(struct pci_dev *pd)
1457 switch (pd->device & 0x0ff0) {
1458 case 0x0100: /* GeForce 256 */
1459 case 0x0110: /* GeForce2 MX */
1460 case 0x0150: /* GeForce2 */
1461 case 0x0170: /* GeForce4 MX */
1462 case 0x0180: /* GeForce4 MX (8x AGP) */
1463 case 0x01A0: /* nForce */
1464 case 0x01F0: /* nForce2 */
1467 case 0x0200: /* GeForce3 */
1468 case 0x0250: /* GeForce4 Ti */
1469 case 0x0280: /* GeForce4 Ti (8x AGP) */
1472 case 0x0300: /* GeForceFX 5800 */
1473 case 0x0310: /* GeForceFX 5600 */
1474 case 0x0320: /* GeForceFX 5200 */
1475 case 0x0330: /* GeForceFX 5900 */
1476 case 0x0340: /* GeForceFX 5700 */
1492 case 0x0020: /* TNT, TNT2 */
1495 default: /* unknown architecture */
1502 static int __devinit nvidiafb_probe(struct pci_dev *pd,
1503 const struct pci_device_id *ent)
1505 struct nvidia_par *par;
1506 struct fb_info *info;
1513 info = framebuffer_alloc(sizeof(struct nvidia_par), &pd->dev);
1518 par = (struct nvidia_par *)info->par;
1521 info->pixmap.addr = kmalloc(8 * 1024, GFP_KERNEL);
1523 if (info->pixmap.addr == NULL)
1526 memset(info->pixmap.addr, 0, 8 * 1024);
1528 if (pci_enable_device(pd)) {
1529 printk(KERN_ERR PFX "cannot enable PCI device\n");
1530 goto err_out_enable;
1533 if (pci_request_regions(pd, "nvidiafb")) {
1534 printk(KERN_ERR PFX "cannot request PCI regions\n");
1535 goto err_out_request;
1538 par->Architecture = nvidia_get_arch(pd);
1540 par->Chipset = (pd->vendor << 16) | pd->device;
1541 printk(KERN_INFO PFX "nVidia device/chipset %X\n", par->Chipset);
1543 if (par->Architecture == 0) {
1544 printk(KERN_ERR PFX "unknown NV_ARCH\n");
1545 goto err_out_free_base0;
1548 sprintf(nvidiafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
1550 par->FlatPanel = flatpanel;
1553 printk(KERN_INFO PFX "flatpanel support enabled\n");
1555 par->CRTCnumber = forceCRTC;
1556 par->FpScale = (!noscale);
1557 par->paneltweak = paneltweak;
1559 /* enable IO and mem if not already done */
1560 pci_read_config_word(pd, PCI_COMMAND, &cmd);
1561 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1562 pci_write_config_word(pd, PCI_COMMAND, cmd);
1564 nvidiafb_fix.mmio_start = pci_resource_start(pd, 0);
1565 nvidiafb_fix.smem_start = pci_resource_start(pd, 1);
1566 nvidiafb_fix.mmio_len = pci_resource_len(pd, 0);
1568 par->REGS = ioremap(nvidiafb_fix.mmio_start, nvidiafb_fix.mmio_len);
1571 printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
1572 goto err_out_free_base0;
1575 NVCommonSetup(info);
1577 par->FbAddress = nvidiafb_fix.smem_start;
1578 par->FbMapSize = par->RamAmountKBytes * 1024;
1579 if (vram && vram * 1024 * 1024 < par->FbMapSize)
1580 par->FbMapSize = vram * 1024 * 1024;
1582 /* Limit amount of vram to 64 MB */
1583 if (par->FbMapSize > 64 * 1024 * 1024)
1584 par->FbMapSize = 64 * 1024 * 1024;
1586 par->FbUsableSize = par->FbMapSize - (128 * 1024);
1587 par->ScratchBufferSize = (par->Architecture < NV_ARCH_10) ? 8 * 1024 :
1589 par->ScratchBufferStart = par->FbUsableSize - par->ScratchBufferSize;
1590 info->screen_base = ioremap(nvidiafb_fix.smem_start, par->FbMapSize);
1591 info->screen_size = par->FbUsableSize;
1592 nvidiafb_fix.smem_len = par->RamAmountKBytes * 1024;
1594 if (!info->screen_base) {
1595 printk(KERN_ERR PFX "cannot ioremap FB base\n");
1596 goto err_out_free_base1;
1599 par->FbStart = info->screen_base;
1603 par->mtrr.vram = mtrr_add(nvidiafb_fix.smem_start,
1604 par->RamAmountKBytes * 1024,
1605 MTRR_TYPE_WRCOMB, 1);
1606 if (par->mtrr.vram < 0) {
1607 printk(KERN_ERR PFX "unable to setup MTRR\n");
1609 par->mtrr.vram_valid = 1;
1610 /* let there be speed */
1611 printk(KERN_INFO PFX "MTRR set to ON\n");
1614 #endif /* CONFIG_MTRR */
1616 info->fbops = &nvidia_fb_ops;
1617 info->fix = nvidiafb_fix;
1619 if (nvidia_set_fbinfo(info) < 0) {
1620 printk(KERN_ERR PFX "error setting initial video mode\n");
1621 goto err_out_iounmap_fb;
1624 nvidia_save_vga(par, &par->SavedReg);
1626 if (register_framebuffer(info) < 0) {
1627 printk(KERN_ERR PFX "error registering nVidia framebuffer\n");
1628 goto err_out_iounmap_fb;
1631 pci_set_drvdata(pd, info);
1633 printk(KERN_INFO PFX
1634 "PCI nVidia %s framebuffer (%dMB @ 0x%lX)\n",
1636 par->FbMapSize / (1024 * 1024), info->fix.smem_start);
1637 #ifdef CONFIG_PMAC_BACKLIGHT
1638 if (par->FlatPanel && _machine == _MACH_Pmac)
1639 register_backlight_controller(&nvidia_backlight_controller,
1646 iounmap(info->screen_base);
1648 fb_destroy_modedb(info->monspecs.modedb);
1649 nvidia_delete_i2c_busses(par);
1652 pci_release_regions(pd);
1654 pci_disable_device(pd);
1656 kfree(info->pixmap.addr);
1658 framebuffer_release(info);
1663 static void __exit nvidiafb_remove(struct pci_dev *pd)
1665 struct fb_info *info = pci_get_drvdata(pd);
1666 struct nvidia_par *par = info->par;
1672 unregister_framebuffer(info);
1674 if (par->mtrr.vram_valid)
1675 mtrr_del(par->mtrr.vram, info->fix.smem_start,
1676 info->fix.smem_len);
1677 #endif /* CONFIG_MTRR */
1679 iounmap(info->screen_base);
1680 fb_destroy_modedb(info->monspecs.modedb);
1681 nvidia_delete_i2c_busses(par);
1683 pci_release_regions(pd);
1684 pci_disable_device(pd);
1685 kfree(info->pixmap.addr);
1686 framebuffer_release(info);
1687 pci_set_drvdata(pd, NULL);
1691 /* ------------------------------------------------------------------------- *
1695 * ------------------------------------------------------------------------- */
1698 static int __devinit nvidiafb_setup(char *options)
1703 if (!options || !*options)
1706 while ((this_opt = strsep(&options, ",")) != NULL) {
1707 if (!strncmp(this_opt, "forceCRTC", 9)) {
1713 forceCRTC = *p - '0';
1714 if (forceCRTC < 0 || forceCRTC > 1)
1716 } else if (!strncmp(this_opt, "flatpanel", 9)) {
1718 } else if (!strncmp(this_opt, "hwcur", 5)) {
1720 } else if (!strncmp(this_opt, "noaccel", 6)) {
1722 } else if (!strncmp(this_opt, "noscale", 7)) {
1724 } else if (!strncmp(this_opt, "paneltweak:", 11)) {
1725 paneltweak = simple_strtoul(this_opt+11, NULL, 0);
1726 } else if (!strncmp(this_opt, "vram:", 5)) {
1727 vram = simple_strtoul(this_opt+5, NULL, 0);
1729 } else if (!strncmp(this_opt, "nomtrr", 6)) {
1733 mode_option = this_opt;
1738 #endif /* !MODULE */
1740 static struct pci_driver nvidiafb_driver = {
1742 .id_table = nvidiafb_pci_tbl,
1743 .probe = nvidiafb_probe,
1744 .remove = __exit_p(nvidiafb_remove),
1747 /* ------------------------------------------------------------------------- *
1751 * ------------------------------------------------------------------------- */
1753 static int __devinit nvidiafb_init(void)
1756 char *option = NULL;
1758 if (fb_get_options("nvidiafb", &option))
1760 nvidiafb_setup(option);
1762 return pci_register_driver(&nvidiafb_driver);
1765 module_init(nvidiafb_init);
1768 static void __exit nvidiafb_exit(void)
1770 pci_unregister_driver(&nvidiafb_driver);
1773 module_exit(nvidiafb_exit);
1775 module_param(flatpanel, int, 0);
1776 MODULE_PARM_DESC(flatpanel,
1777 "Enables experimental flat panel support for some chipsets. "
1778 "(0 or 1=enabled) (default=0)");
1779 module_param(hwcur, int, 0);
1780 MODULE_PARM_DESC(hwcur,
1781 "Enables hardware cursor implementation. (0 or 1=enabled) "
1783 module_param(noaccel, int, 0);
1784 MODULE_PARM_DESC(noaccel,
1785 "Disables hardware acceleration. (0 or 1=disable) "
1787 module_param(noscale, int, 0);
1788 MODULE_PARM_DESC(noscale,
1789 "Disables screen scaleing. (0 or 1=disable) "
1790 "(default=0, do scaling)");
1791 module_param(paneltweak, int, 0);
1792 MODULE_PARM_DESC(paneltweak,
1793 "Tweak display settings for flatpanels. "
1794 "(default=0, no tweaks)");
1795 module_param(forceCRTC, int, 0);
1796 MODULE_PARM_DESC(forceCRTC,
1797 "Forces usage of a particular CRTC in case autodetection "
1798 "fails. (0 or 1) (default=autodetect)");
1799 module_param(vram, int, 0);
1800 MODULE_PARM_DESC(vram,
1801 "amount of framebuffer memory to remap in MiB"
1802 "(default=0 - remap entire memory)");
1804 module_param(nomtrr, bool, 0);
1805 MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) "
1809 MODULE_AUTHOR("Antonino Daplas");
1810 MODULE_DESCRIPTION("Framebuffer driver for nVidia graphics chipset");
1811 MODULE_LICENSE("GPL");