drivers/usb/musb/tusb6010_omap.c

   1 /*
   2  * TUSB6010 USB 2.0 OTG Dual Role controller OMAP DMA interface
   3  *
   4  * Copyright (C) 2006 Nokia Corporation
   5  * Tony Lindgren <tony@atomide.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11 #include <linux/module.h>
  12 #include <linux/kernel.h>
  13 #include <linux/errno.h>
  14 #include <linux/init.h>
  15 #include <linux/usb.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/dma-mapping.h>
  18 #include <asm/arch/dma.h>
  19 #include <asm/arch/mux.h>
  20
  21 #include "musbdefs.h"
  22
  23 /*
  24  * REVISIT: With TUSB2.0 only one dmareq line can be used at a time.
  25  * This should get fixed in hardware at some point.
  26  */
  27 #define BROKEN_DMAREQ
  28
  29 #ifdef BROKEN_DMAREQ
  30 #define dmareq_works()          0
  31 #else
  32 #define dmareq_works()          1
  33 #endif
  34
  35 #define to_chdat(c)             (struct tusb_omap_dma_ch *)(c)->pPrivateData
  36
  37 #define MAX_DMAREQ              5       /* REVISIT: Really 6, but req5 not OK */
  38
  39 struct tusb_omap_dma_ch {
  40         struct musb             *musb;
  41         void __iomem            *tusb_base;
  42         unsigned long           phys_offset;
  43         int                     epnum;
  44         u8                      tx;
  45         struct musb_hw_ep       *hw_ep;
  46
  47         int                     ch;
  48         s8                      dmareq;
  49         s8                      sync_dev;
  50
  51         struct tusb_omap_dma    *tusb_dma;
  52
  53         void __iomem            *dma_addr;
  54
  55         u32                     len;
  56         u16                     packet_sz;
  57         u16                     transfer_packet_sz;
  58         u32                     transfer_len;
  59         u32                     completed_len;
  60 };
  61
  62 struct tusb_omap_dma {
  63         struct dma_controller           controller;
  64         struct musb                     *musb;
  65         void __iomem                    *tusb_base;
  66
  67         int                             ch;
  68         s8                              dmareq;
  69         s8                              sync_dev;
  70 };
  71
  72 static int tusb_omap_dma_start(struct dma_controller *c)
  73 {
  74         struct tusb_omap_dma    *tusb_dma;
  75
  76         tusb_dma = container_of(c, struct tusb_omap_dma, controller);
  77
  78         // DBG(3, "ep%i ch: %i\n", chdat->epnum, chdat->ch);
  79
  80         return 0;
  81 }
  82
  83 static int tusb_omap_dma_stop(struct dma_controller *c)
  84 {
  85         struct tusb_omap_dma    *tusb_dma;
  86
  87         tusb_dma = container_of(c, struct tusb_omap_dma, controller);
  88
  89         // DBG(3, "ep%i ch: %i\n", chdat->epnum, chdat->ch);
  90
  91         return 0;
  92 }
  93
  94 #ifdef BROKEN_DMAREQ
  95
  96 /*
  97  * Allocate dmareq0 to the current channel unless it's already taken
  98  */
  99 static inline int tusb_omap_use_shared_dmareq(struct tusb_omap_dma_ch *chdat)
 100 {
 101         u32             reg = musb_readl(chdat->tusb_base, TUSB_DMA_EP_MAP);
 102
 103         if (reg != 0) {
 104                 DBG(3, "ep%i dmareq0 is busy for ep%i\n",
 105                         chdat->epnum, reg & 0xf);
 106                 return -EAGAIN;
 107         }
 108
 109         if (chdat->tx)
 110                 reg = (1 << 4) | chdat->epnum;
 111         else
 112                 reg = chdat->epnum;
 113
 114         musb_writel(chdat->tusb_base, TUSB_DMA_EP_MAP, reg);
 115
 116         return 0;
 117 }
 118
 119 static inline void tusb_omap_free_shared_dmareq(struct tusb_omap_dma_ch *chdat)
 120 {
 121         u32             reg = musb_readl(chdat->tusb_base, TUSB_DMA_EP_MAP);
 122
 123         if ((reg & 0xf) != chdat->epnum) {
 124                 printk(KERN_ERR "ep%i trying to release dmareq0 for ep%i\n",
 125                         chdat->epnum, reg & 0xf);
 126                 return;
 127         }
 128         musb_writel(chdat->tusb_base, TUSB_DMA_EP_MAP, 0);
 129 }
 130
 131 #else
 132 #define tusb_omap_use_shared_dmareq(x, y)       do {} while (0)
 133 #define tusb_omap_free_shared_dmareq(x, y)      do {} while (0)
 134 #endif
 135
 136 /*
 137  * See also musb_dma_completion in plat_uds.c and musb_g_[tx|rx]() in
 138  * musb_gadget.c.
 139  */
 140 static void tusb_omap_dma_cb(int lch, u16 ch_status, void *data)
 141 {
 142         struct dma_channel      *channel = (struct dma_channel *)data;
 143         struct tusb_omap_dma_ch *chdat = to_chdat(channel);
 144         struct tusb_omap_dma    *tusb_dma = chdat->tusb_dma;
 145         struct musb             *musb = chdat->musb;
 146         struct musb_hw_ep       *hw_ep = chdat->hw_ep;
 147         void __iomem            *ep_conf = hw_ep->conf;
 148         void __iomem            *musb_base = musb->pRegs;
 149         unsigned long           remaining, flags;
 150         int                     ch;
 151
 152         spin_lock_irqsave(&musb->Lock, flags);
 153
 154         if (dmareq_works())
 155                 ch = chdat->ch;
 156         else
 157                 ch = tusb_dma->ch;
 158
 159         if (ch_status != OMAP_DMA_BLOCK_IRQ)
 160                 printk(KERN_ERR "TUSB DMA error status: %i\n", ch_status);
 161
 162         DBG(2, "ep%i %s dma callback ch: %i status: %x\n",
 163                 chdat->epnum, chdat->tx ? "tx" : "rx",
 164                 ch, ch_status);
 165
 166         if (chdat->tx)
 167                 remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET);
 168         else
 169                 remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET);
 170
 171         remaining = TUSB_EP_CONFIG_XFR_SIZE(remaining);
 172         channel->dwActualLength = chdat->transfer_len - remaining;
 173
 174         DBG(2, "remaining %lu/%u\n", remaining, chdat->transfer_len);
 175
 176         if (!dmareq_works())
 177                 tusb_omap_free_shared_dmareq(chdat);
 178
 179         channel->bStatus = MGC_DMA_STATUS_FREE;
 180
 181         /* Handle only RX callbacks here. TX callbacks musb be handled based
 182          * on the TUSB DMA status interrupt.
 183          * REVISIT: Use both TUSB DMA status interrupt and OMAP DMA callback
 184          * interrupt for RX and TX.
 185          */
 186         if (!chdat->tx)
 187                 musb_dma_completion(musb, chdat->epnum, chdat->tx);
 188
 189         /* We musb terminate short tx transfers manually by setting TXPKTRDY.
 190          * REVISIT: This same problem may occur with other MUSB dma as well.
 191          * Easy to test with g_ether by pinging the MUSB board with ping -s54.
 192          */
 193         if ((chdat->transfer_len < chdat->packet_sz)
 194                         || (chdat->transfer_len % chdat->packet_sz != 0)) {
 195                 u16     csr;
 196
 197                 if (chdat->tx) {
 198                         DBG(2, "terminating short tx packet\n");
 199                         MGC_SelectEnd(musb_base, chdat->epnum);
 200                         csr = musb_readw(hw_ep->regs, MGC_O_HDRC_TXCSR);
 201                         csr |= MGC_M_TXCSR_MODE | MGC_M_TXCSR_TXPKTRDY
 202                                 | MGC_M_TXCSR_P_WZC_BITS;
 203                         musb_writew(hw_ep->regs, MGC_O_HDRC_TXCSR, csr);
 204                 }
 205         }
 206
 207         spin_unlock_irqrestore(&musb->Lock, flags);
 208 }
 209
 210 static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz,
 211                                 u8 rndis_mode, dma_addr_t dma_addr, u32 len)
 212 {
 213         struct tusb_omap_dma_ch         *chdat = to_chdat(channel);
 214         struct tusb_omap_dma            *tusb_dma = chdat->tusb_dma;
 215         struct musb                     *musb = chdat->musb;
 216         struct musb_hw_ep               *hw_ep = chdat->hw_ep;
 217         void __iomem                    *musb_base = musb->pRegs;
 218         void __iomem                    *ep_conf = hw_ep->conf;
 219         dma_addr_t                      fifo = hw_ep->fifo_sync;
 220         struct omap_dma_channel_params  dma_params;
 221         int                             src_burst, dst_burst;
 222         u16                             csr;
 223         int                             ch;
 224         s8                              dmareq;
 225         s8                              sync_dev;
 226
 227         if (unlikely(dma_addr & 0x1))
 228                 return FALSE;
 229         if (len < 32)
 230                 return FALSE;
 231         if ((len % 32 != 0))
 232                 return FALSE;
 233         else
 234                 chdat->transfer_len = len;
 235
 236         if (len < packet_sz)
 237                 chdat->transfer_packet_sz = chdat->transfer_len;
 238         else
 239                 chdat->transfer_packet_sz = packet_sz;
 240
 241         if (dmareq_works()) {
 242                 ch = chdat->ch;
 243                 dmareq = chdat->dmareq;
 244                 sync_dev = chdat->sync_dev;
 245         } else {
 246                 if (tusb_omap_use_shared_dmareq(chdat) != 0) {
 247                         DBG(3, "could not get dma for ep%i\n", chdat->epnum);
 248                         return FALSE;
 249                 }
 250                 if (tusb_dma->ch < 0) {
 251                         /* REVISIT: This should get blocked earlier, happens
 252                          * with MSC ErrorRecoveryTest
 253                          */
 254                         WARN_ON(1);
 255                         return FALSE;
 256                 }
 257
 258                 ch = tusb_dma->ch;
 259                 dmareq = tusb_dma->dmareq;
 260                 sync_dev = tusb_dma->sync_dev;
 261                 omap_set_dma_callback(ch, tusb_omap_dma_cb, channel);
 262         }
 263
 264         chdat->packet_sz = packet_sz;
 265         chdat->len = len;
 266         channel->dwActualLength = 0;
 267         chdat->dma_addr = (void __iomem *)dma_addr;
 268         channel->bStatus = MGC_DMA_STATUS_BUSY;
 269
 270         /* Since we're recycling dma areas, we need to clean or invalidate */
 271         if (chdat->tx) {
 272                 consistent_sync(phys_to_virt(dma_addr), len, DMA_TO_DEVICE);
 273         } else
 274                 consistent_sync(phys_to_virt(dma_addr), len, DMA_FROM_DEVICE);
 275
 276         /* Use 16-bit transfer if dma_addr is not 32-bit aligned */
 277         if ((dma_addr & 0x3) == 0) {
 278                 dma_params.data_type = OMAP_DMA_DATA_TYPE_S32;
 279                 dma_params.elem_count = 8;              /* Elements in frame */
 280         } else {
 281                 dma_params.data_type = OMAP_DMA_DATA_TYPE_S16;
 282                 dma_params.elem_count = 16;             /* Elements in frame */
 283                 fifo = hw_ep->fifo_async;
 284         }
 285
 286         dma_params.frame_count  = chdat->transfer_len / 32; /* Burst sz frame */
 287
 288         DBG(2, "ep%i %s dma ch%i dma: %08x len: %u(%u) packet_sz: %i(%i)\n",
 289                 chdat->epnum, chdat->tx ? "tx" : "rx",
 290                 ch, dma_addr, chdat->transfer_len, len,
 291                 chdat->transfer_packet_sz, packet_sz);
 292
 293         /*
 294          * Prepare omap DMA for transfer
 295          */
 296         if (chdat->tx) {
 297                 dma_params.src_amode    = OMAP_DMA_AMODE_POST_INC;
 298                 dma_params.src_start    = (unsigned long)dma_addr;
 299                 dma_params.src_ei       = 0;
 300                 dma_params.src_fi       = 0;
 301
 302                 dma_params.dst_amode    = OMAP_DMA_AMODE_DOUBLE_IDX;
 303                 dma_params.dst_start    = (unsigned long)fifo;
 304                 dma_params.dst_ei       = 1;
 305                 dma_params.dst_fi       = -31;          /* Loop 32 byte window */
 306
 307                 dma_params.trigger      = sync_dev;
 308                 dma_params.sync_mode    = OMAP_DMA_SYNC_FRAME;
 309                 dma_params.src_or_dst_synch     = 0;    /* Dest sync */
 310
 311                 src_burst = OMAP_DMA_DATA_BURST_16;     /* 16x32 read */
 312                 dst_burst = OMAP_DMA_DATA_BURST_8;      /* 8x32 write */
 313         } else {
 314                 dma_params.src_amode    = OMAP_DMA_AMODE_DOUBLE_IDX;
 315                 dma_params.src_start    = (unsigned long)fifo;
 316                 dma_params.src_ei       = 1;
 317                 dma_params.src_fi       = -31;          /* Loop 32 byte window */
 318
 319                 dma_params.dst_amode    = OMAP_DMA_AMODE_POST_INC;
 320                 dma_params.dst_start    = (unsigned long)dma_addr;
 321                 dma_params.dst_ei       = 0;
 322                 dma_params.dst_fi       = 0;
 323
 324                 dma_params.trigger      = sync_dev;
 325                 dma_params.sync_mode    = OMAP_DMA_SYNC_FRAME;
 326                 dma_params.src_or_dst_synch     = 1;    /* Source sync */
 327
 328                 src_burst = OMAP_DMA_DATA_BURST_8;      /* 8x32 read */
 329                 dst_burst = OMAP_DMA_DATA_BURST_16;     /* 16x32 write */
 330         }
 331
 332         DBG(2, "ep%i %s using %i-bit %s dma from 0x%08lx to 0x%08lx\n",
 333                 chdat->epnum, chdat->tx ? "tx" : "rx",
 334                 (dma_params.data_type == OMAP_DMA_DATA_TYPE_S32) ? 32 : 16,
 335                 ((dma_addr & 0x3) == 0) ? "sync" : "async",
 336                 dma_params.src_start, dma_params.dst_start);
 337
 338         omap_set_dma_params(ch, &dma_params);
 339         omap_set_dma_src_burst_mode(ch, src_burst);
 340         omap_set_dma_dest_burst_mode(ch, dst_burst);
 341         omap_set_dma_write_mode(ch, OMAP_DMA_WRITE_LAST_NON_POSTED);
 342
 343         /*
 344          * Prepare MUSB for DMA transfer
 345          */
 346         if (chdat->tx) {
 347                 MGC_SelectEnd(musb_base, chdat->epnum);
 348                 csr = musb_readw(hw_ep->regs, MGC_O_HDRC_TXCSR);
 349                 csr |= (MGC_M_TXCSR_AUTOSET | MGC_M_TXCSR_DMAENAB
 350                         | MGC_M_TXCSR_DMAMODE | MGC_M_TXCSR_MODE);
 351                 csr &= ~MGC_M_TXCSR_P_UNDERRUN;
 352                 musb_writew(hw_ep->regs, MGC_O_HDRC_TXCSR, csr);
 353         } else {
 354                 MGC_SelectEnd(musb_base, chdat->epnum);
 355                 csr = musb_readw(hw_ep->regs, MGC_O_HDRC_RXCSR);
 356                 csr |= MGC_M_RXCSR_DMAENAB;
 357                 csr &= ~(MGC_M_RXCSR_AUTOCLEAR | MGC_M_RXCSR_DMAMODE);
 358                 musb_writew(hw_ep->regs, MGC_O_HDRC_RXCSR,
 359                         csr | MGC_M_RXCSR_P_WZC_BITS);
 360         }
 361
 362         /*
 363          * Start DMA transfer
 364          */
 365         omap_start_dma(ch);
 366
 367         if (chdat->tx) {
 368                 /* Send transfer_packet_sz packets at a time */
 369                 musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET,
 370                         chdat->transfer_packet_sz);
 371
 372                 musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
 373                         TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len));
 374         } else {
 375                 /* Receive transfer_packet_sz packets at a time */
 376                 musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET,
 377                         chdat->transfer_packet_sz << 16);
 378
 379                 musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
 380                         TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len));
 381         }
 382
 383         return TRUE;
 384 }
 385
 386 static int tusb_omap_dma_abort(struct dma_channel *channel)
 387 {
 388         struct tusb_omap_dma_ch *chdat = to_chdat(channel);
 389         struct tusb_omap_dma    *tusb_dma = chdat->tusb_dma;
 390
 391         if (!dmareq_works()) {
 392                 if (tusb_dma->ch >= 0) {
 393                         omap_stop_dma(tusb_dma->ch);
 394                         omap_free_dma(tusb_dma->ch);
 395                         tusb_dma->ch = -1;
 396                 }
 397
 398                 tusb_dma->dmareq = -1;
 399                 tusb_dma->sync_dev = -1;
 400         }
 401
 402         channel->bStatus = MGC_DMA_STATUS_FREE;
 403
 404         return 0;
 405 }
 406
 407 static inline int tusb_omap_dma_allocate_dmareq(struct tusb_omap_dma_ch *chdat)
 408 {
 409         u32             reg = musb_readl(chdat->tusb_base, TUSB_DMA_EP_MAP);
 410         int             i, dmareq_nr = -1;
 411
 412         const int sync_dev[6] = {
 413                 OMAP24XX_DMA_EXT_DMAREQ0,
 414                 OMAP24XX_DMA_EXT_DMAREQ1,
 415                 OMAP24XX_DMA_EXT_DMAREQ2,
 416                 OMAP24XX_DMA_EXT_DMAREQ3,
 417                 OMAP24XX_DMA_EXT_DMAREQ4,
 418                 OMAP24XX_DMA_EXT_DMAREQ5,
 419         };
 420
 421         for (i = 0; i < MAX_DMAREQ; i++) {
 422                 int cur = (reg & (0xf << (i * 5))) >> (i * 5);
 423                 if (cur == 0) {
 424                         dmareq_nr = i;
 425                         break;
 426                 }
 427         }
 428
 429         if (dmareq_nr == -1)
 430                 return -EAGAIN;
 431
 432         reg |= (chdat->epnum << (dmareq_nr * 5));
 433         if (chdat->tx)
 434                 reg |= ((1 << 4) << (dmareq_nr * 5));
 435         musb_writel(chdat->tusb_base, TUSB_DMA_EP_MAP, reg);
 436
 437         chdat->dmareq = dmareq_nr;
 438         chdat->sync_dev = sync_dev[chdat->dmareq];
 439
 440         return 0;
 441 }
 442
 443 static inline void tusb_omap_dma_free_dmareq(struct tusb_omap_dma_ch *chdat)
 444 {
 445         u32 reg;
 446
 447         if (!chdat || chdat->dmareq < 0)
 448                 return;
 449
 450         reg = musb_readl(chdat->tusb_base, TUSB_DMA_EP_MAP);
 451         reg &= ~(0x1f << (chdat->dmareq * 5));
 452         musb_writel(chdat->tusb_base, TUSB_DMA_EP_MAP, reg);
 453
 454         chdat->dmareq = -1;
 455         chdat->sync_dev = -1;
 456 }
 457
 458 static struct dma_channel *dma_channel_pool[MAX_DMAREQ];
 459
 460 static struct dma_channel *
 461 tusb_omap_dma_allocate(struct dma_controller *c,
 462                 struct musb_hw_ep *hw_ep,
 463                 u8 tx)
 464 {
 465         int ret, i;
 466         const char              *dev_name;
 467         struct tusb_omap_dma    *tusb_dma;
 468         struct musb             *musb;
 469         void __iomem            *tusb_base;
 470         struct dma_channel      *channel = NULL;
 471         struct tusb_omap_dma_ch *chdat = NULL;
 472         u32                     reg;
 473
 474         tusb_dma = container_of(c, struct tusb_omap_dma, controller);
 475         musb = tusb_dma->musb;
 476         tusb_base = musb->ctrl_base;
 477
 478         reg = musb_readl(tusb_base, TUSB_DMA_INT_MASK);
 479         if (tx)
 480                 reg &= ~(1 << hw_ep->bLocalEnd);
 481         else
 482                 reg &= ~(1 << (hw_ep->bLocalEnd + 15));
 483         musb_writel(tusb_base, TUSB_DMA_INT_MASK, reg);
 484
 485         /* REVISIT: Why does dmareq5 not work? */
 486         if (hw_ep->bLocalEnd == 0) {
 487                 DBG(3, "Not allowing DMA for ep0 %s\n", tx ? "tx" : "rx");
 488                 return NULL;
 489         }
 490
 491         for (i = 0; i < MAX_DMAREQ; i++) {
 492                 struct dma_channel *ch = dma_channel_pool[i];
 493                 if (ch->bStatus == MGC_DMA_STATUS_UNKNOWN) {
 494                         ch->bStatus = MGC_DMA_STATUS_FREE;
 495                         channel = ch;
 496                         chdat = ch->pPrivateData;
 497                         break;
 498                 }
 499         }
 500
 501         if (!channel)
 502                 return NULL;
 503
 504         if (tx) {
 505                 chdat->tx = 1;
 506                 dev_name = "TUSB transmit";
 507         } else {
 508                 chdat->tx = 0;
 509                 dev_name = "TUSB receive";
 510         }
 511
 512         chdat->musb = tusb_dma->musb;
 513         chdat->tusb_base = tusb_dma->tusb_base;
 514         chdat->hw_ep = hw_ep;
 515         chdat->epnum = hw_ep->bLocalEnd;
 516         chdat->dmareq = -1;
 517         chdat->completed_len = 0;
 518         chdat->tusb_dma = tusb_dma;
 519
 520         channel->dwMaxLength = 0x7fffffff;
 521         channel->bDesiredMode = 0;
 522         channel->dwActualLength = 0;
 523
 524         if (dmareq_works()) {
 525                 ret = tusb_omap_dma_allocate_dmareq(chdat);
 526                 if (ret != 0)
 527                         goto free_dmareq;
 528
 529                 ret = omap_request_dma(chdat->sync_dev, dev_name,
 530                                 tusb_omap_dma_cb, channel, &chdat->ch);
 531                 if (ret != 0)
 532                         goto free_dmareq;
 533         } else if (tusb_dma->ch == -1) {
 534                 tusb_dma->dmareq = 0;
 535                 tusb_dma->sync_dev = OMAP24XX_DMA_EXT_DMAREQ0;
 536
 537                 /* Callback data gets set later in the shared dmareq case */
 538                 ret = omap_request_dma(tusb_dma->sync_dev, "TUSB shared",
 539                                 tusb_omap_dma_cb, NULL, &tusb_dma->ch);
 540                 if (ret != 0)
 541                         goto free_dmareq;
 542
 543                 chdat->dmareq = -1;
 544                 chdat->ch = -1;
 545         }
 546
 547         DBG(3, "ep%i %s dma: %s dma%i dmareq%i sync%i\n",
 548                 chdat->epnum,
 549                 chdat->tx ? "tx" : "rx",
 550                 chdat->ch >=0 ? "dedicated" : "shared",
 551                 chdat->ch >= 0 ? chdat->ch : tusb_dma->ch,
 552                 chdat->dmareq >= 0 ? chdat->dmareq : tusb_dma->dmareq,
 553                 chdat->sync_dev >= 0 ? chdat->sync_dev : tusb_dma->sync_dev);
 554
 555         return channel;
 556
 557 free_dmareq:
 558         tusb_omap_dma_free_dmareq(chdat);
 559
 560         DBG(3, "ep%i: Could not get a DMA channel\n", chdat->epnum);
 561         channel->bStatus = MGC_DMA_STATUS_UNKNOWN;
 562
 563         return NULL;
 564 }
 565
 566 static void tusb_omap_dma_release(struct dma_channel *channel)
 567 {
 568         struct tusb_omap_dma_ch *chdat = to_chdat(channel);
 569         struct musb             *musb = chdat->musb;
 570         void __iomem            *tusb_base = musb->ctrl_base;
 571         u32                     reg;
 572
 573         DBG(3, "ep%i ch%i\n", chdat->epnum, chdat->ch);
 574
 575         reg = musb_readl(tusb_base, TUSB_DMA_INT_MASK);
 576         if (chdat->tx)
 577                 reg |= (1 << chdat->epnum);
 578         else
 579                 reg |= (1 << (chdat->epnum + 15));
 580         musb_writel(tusb_base, TUSB_DMA_INT_MASK, reg);
 581
 582         reg = musb_readl(tusb_base, TUSB_DMA_INT_CLEAR);
 583         if (chdat->tx)
 584                 reg |= (1 << chdat->epnum);
 585         else
 586                 reg |= (1 << (chdat->epnum + 15));
 587         musb_writel(tusb_base, TUSB_DMA_INT_CLEAR, reg);
 588
 589         channel->bStatus = MGC_DMA_STATUS_UNKNOWN;
 590
 591         if (chdat->ch >= 0) {
 592                 omap_stop_dma(chdat->ch);
 593                 omap_free_dma(chdat->ch);
 594                 chdat->ch = -1;
 595         }
 596
 597         if (chdat->dmareq >= 0)
 598                 tusb_omap_dma_free_dmareq(chdat);
 599
 600         channel = NULL;
 601 }
 602
 603 static void tusb_omap_dma_cleanup(struct dma_controller *c)
 604 {
 605         struct tusb_omap_dma    *tusb_dma;
 606         int                     i;
 607
 608         tusb_dma = container_of(c, struct tusb_omap_dma, controller);
 609         for (i = 0; i < MAX_DMAREQ; i++) {
 610                 struct dma_channel *ch = dma_channel_pool[i];
 611                 if (ch) {
 612                         if (ch->pPrivateData)
 613                                 kfree(ch->pPrivateData);
 614                         kfree(ch);
 615                 }
 616         }
 617
 618         if (!dmareq_works() && tusb_dma && tusb_dma->ch >= 0)
 619                 omap_free_dma(tusb_dma->ch);
 620
 621         kfree(tusb_dma);
 622 }
 623
 624 static struct dma_controller *
 625 tusb_omap_dma_init(struct musb *musb, void __iomem *base)
 626 {
 627         void __iomem            *tusb_base = musb->ctrl_base;
 628         struct tusb_omap_dma    *tusb_dma;
 629         int                     i;
 630
 631         /* REVISIT: Get dmareq lines used from board-*.c */
 632
 633         musb_writel(musb->ctrl_base, TUSB_DMA_INT_MASK, 0x7fffffff);
 634         musb_writel(musb->ctrl_base, TUSB_DMA_EP_MAP, 0);
 635
 636         musb_writel(tusb_base, TUSB_DMA_REQ_CONF,
 637                 TUSB_DMA_REQ_CONF_BURST_SIZE(2)
 638                 | TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f)
 639                 | TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
 640
 641         tusb_dma = kzalloc(sizeof(struct tusb_omap_dma), GFP_KERNEL);
 642         if (!tusb_dma)
 643                 goto cleanup;
 644
 645         tusb_dma->musb = musb;
 646         tusb_dma->tusb_base = musb->ctrl_base;
 647
 648         tusb_dma->ch = -1;
 649         tusb_dma->dmareq = -1;
 650         tusb_dma->sync_dev = -1;
 651
 652         tusb_dma->controller.start = tusb_omap_dma_start;
 653         tusb_dma->controller.stop = tusb_omap_dma_stop;
 654         tusb_dma->controller.channel_alloc = tusb_omap_dma_allocate;
 655         tusb_dma->controller.channel_release = tusb_omap_dma_release;
 656         tusb_dma->controller.channel_program = tusb_omap_dma_program;
 657         tusb_dma->controller.channel_abort = tusb_omap_dma_abort;
 658         tusb_dma->controller.pPrivateData = tusb_dma;
 659
 660         for (i = 0; i < MAX_DMAREQ; i++) {
 661                 struct dma_channel      *ch;
 662                 struct tusb_omap_dma_ch *chdat;
 663
 664                 ch = kzalloc(sizeof(struct dma_channel), GFP_KERNEL);
 665                 if (!ch)
 666                         goto cleanup;
 667
 668                 dma_channel_pool[i] = ch;
 669
 670                 chdat = kzalloc(sizeof(struct tusb_omap_dma_ch), GFP_KERNEL);
 671                 if (!chdat)
 672                         goto cleanup;
 673
 674                 ch->bStatus = MGC_DMA_STATUS_UNKNOWN;
 675                 ch->pPrivateData = chdat;
 676         }
 677
 678         return &tusb_dma->controller;
 679
 680 cleanup:
 681         tusb_omap_dma_cleanup(&tusb_dma->controller);
 682
 683         return NULL;
 684 }
 685
 686 const struct dma_controller_factory dma_controller_factory = {
 687         .create =       tusb_omap_dma_init,
 688         .destroy =      tusb_omap_dma_cleanup,
 689 };