2 * TUSB6010 USB 2.0 OTG Dual Role controller OMAP DMA interface
4 * Copyright (C) 2006 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/errno.h>
14 #include <linux/init.h>
15 #include <linux/usb.h>
16 #include <linux/platform_device.h>
17 #include <linux/dma-mapping.h>
18 #include <asm/arch/dma.h>
19 #include <asm/arch/mux.h>
21 #include "musb_core.h"
24 * REVISIT: With TUSB2.0 only one dmareq line can be used at a time.
25 * This should get fixed in hardware at some point.
30 #define dmareq_works() 0
32 #define dmareq_works() 1
35 #define to_chdat(c) (struct tusb_omap_dma_ch *)(c)->private_data
37 #define MAX_DMAREQ 5 /* REVISIT: Really 6, but req5 not OK */
39 struct tusb_omap_dma_ch {
41 void __iomem *tusb_base;
42 unsigned long phys_offset;
45 struct musb_hw_ep *hw_ep;
51 struct tusb_omap_dma *tusb_dma;
53 void __iomem *dma_addr;
57 u16 transfer_packet_sz;
62 struct tusb_omap_dma {
63 struct dma_controller controller;
65 void __iomem *tusb_base;
72 static int tusb_omap_dma_start(struct dma_controller *c)
74 struct tusb_omap_dma *tusb_dma;
76 tusb_dma = container_of(c, struct tusb_omap_dma, controller);
78 // DBG(3, "ep%i ch: %i\n", chdat->epnum, chdat->ch);
83 static int tusb_omap_dma_stop(struct dma_controller *c)
85 struct tusb_omap_dma *tusb_dma;
87 tusb_dma = container_of(c, struct tusb_omap_dma, controller);
89 // DBG(3, "ep%i ch: %i\n", chdat->epnum, chdat->ch);
97 * Allocate dmareq0 to the current channel unless it's already taken
99 static inline int tusb_omap_use_shared_dmareq(struct tusb_omap_dma_ch *chdat)
101 u32 reg = musb_readl(chdat->tusb_base, TUSB_DMA_EP_MAP);
104 DBG(3, "ep%i dmareq0 is busy for ep%i\n",
105 chdat->epnum, reg & 0xf);
110 reg = (1 << 4) | chdat->epnum;
114 musb_writel(chdat->tusb_base, TUSB_DMA_EP_MAP, reg);
119 static inline void tusb_omap_free_shared_dmareq(struct tusb_omap_dma_ch *chdat)
121 u32 reg = musb_readl(chdat->tusb_base, TUSB_DMA_EP_MAP);
123 if ((reg & 0xf) != chdat->epnum) {
124 printk(KERN_ERR "ep%i trying to release dmareq0 for ep%i\n",
125 chdat->epnum, reg & 0xf);
128 musb_writel(chdat->tusb_base, TUSB_DMA_EP_MAP, 0);
132 #define tusb_omap_use_shared_dmareq(x, y) do {} while (0)
133 #define tusb_omap_free_shared_dmareq(x, y) do {} while (0)
137 * See also musb_dma_completion in plat_uds.c and musb_g_[tx|rx]() in
140 static void tusb_omap_dma_cb(int lch, u16 ch_status, void *data)
142 struct dma_channel *channel = (struct dma_channel *)data;
143 struct tusb_omap_dma_ch *chdat = to_chdat(channel);
144 struct tusb_omap_dma *tusb_dma = chdat->tusb_dma;
145 struct musb *musb = chdat->musb;
146 struct musb_hw_ep *hw_ep = chdat->hw_ep;
147 void __iomem *ep_conf = hw_ep->conf;
148 void __iomem *musb_base = musb->mregs;
149 unsigned long remaining, flags, pio;
152 spin_lock_irqsave(&musb->lock, flags);
159 if (ch_status != OMAP_DMA_BLOCK_IRQ)
160 printk(KERN_ERR "TUSB DMA error status: %i\n", ch_status);
162 DBG(2, "ep%i %s dma callback ch: %i status: %x\n",
163 chdat->epnum, chdat->tx ? "tx" : "rx",
167 remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET);
169 remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET);
171 remaining = TUSB_EP_CONFIG_XFR_SIZE(remaining);
173 /* HW issue #10: XFR_SIZE may get corrupt on async DMA */
174 if (unlikely(remaining > chdat->transfer_len)) {
175 WARN("Corrupt XFR_SIZE with async DMA: %lu\n", remaining);
179 channel->actual_len = chdat->transfer_len - remaining;
180 pio = chdat->len - channel->actual_len;
182 DBG(2, "DMA remaining %lu/%u\n", remaining, chdat->transfer_len);
184 /* Transfer remaining 1 - 31 bytes */
185 if (pio > 0 && pio < 32) {
188 DBG(2, "Using PIO for remaining %lu bytes\n", pio);
189 buf = phys_to_virt((u32)chdat->dma_addr) + chdat->transfer_len;
191 consistent_sync(phys_to_virt((u32)chdat->dma_addr),
192 chdat->transfer_len, DMA_TO_DEVICE);
193 musb_write_fifo(hw_ep, pio, buf);
195 musb_read_fifo(hw_ep, pio, buf);
196 consistent_sync(phys_to_virt((u32)chdat->dma_addr),
197 chdat->transfer_len, DMA_FROM_DEVICE);
199 channel->actual_len += pio;
203 tusb_omap_free_shared_dmareq(chdat);
205 channel->status = MUSB_DMA_STATUS_FREE;
207 /* Handle only RX callbacks here. TX callbacks musb be handled based
208 * on the TUSB DMA status interrupt.
209 * REVISIT: Use both TUSB DMA status interrupt and OMAP DMA callback
210 * interrupt for RX and TX.
213 musb_dma_completion(musb, chdat->epnum, chdat->tx);
215 /* We must terminate short tx transfers manually by setting TXPKTRDY.
216 * REVISIT: This same problem may occur with other MUSB dma as well.
217 * Easy to test with g_ether by pinging the MUSB board with ping -s54.
219 if ((chdat->transfer_len < chdat->packet_sz)
220 || (chdat->transfer_len % chdat->packet_sz != 0)) {
224 DBG(2, "terminating short tx packet\n");
225 musb_ep_select(musb_base, chdat->epnum);
226 csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
227 csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY
228 | MUSB_TXCSR_P_WZC_BITS;
229 musb_writew(hw_ep->regs, MUSB_TXCSR, csr);
233 spin_unlock_irqrestore(&musb->lock, flags);
236 static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz,
237 u8 rndis_mode, dma_addr_t dma_addr, u32 len)
239 struct tusb_omap_dma_ch *chdat = to_chdat(channel);
240 struct tusb_omap_dma *tusb_dma = chdat->tusb_dma;
241 struct musb *musb = chdat->musb;
242 struct musb_hw_ep *hw_ep = chdat->hw_ep;
243 void __iomem *musb_base = musb->mregs;
244 void __iomem *ep_conf = hw_ep->conf;
245 dma_addr_t fifo = hw_ep->fifo_sync;
246 struct omap_dma_channel_params dma_params;
247 int src_burst, dst_burst;
253 if (unlikely(dma_addr & 0x1) || (len < 32) || (len > packet_sz))
257 * HW issue #10: Async dma will eventually corrupt the XFR_SIZE
258 * register which will cause missed DMA interrupt. We could try to
259 * use a timer for the callback, but it is unsafe as the XFR_SIZE
260 * register is corrupt, and we won't know if the DMA worked.
265 chdat->transfer_len = len & ~0x1f;
268 chdat->transfer_packet_sz = chdat->transfer_len;
270 chdat->transfer_packet_sz = packet_sz;
272 if (dmareq_works()) {
274 dmareq = chdat->dmareq;
275 sync_dev = chdat->sync_dev;
277 if (tusb_omap_use_shared_dmareq(chdat) != 0) {
278 DBG(3, "could not get dma for ep%i\n", chdat->epnum);
281 if (tusb_dma->ch < 0) {
282 /* REVISIT: This should get blocked earlier, happens
283 * with MSC ErrorRecoveryTest
290 dmareq = tusb_dma->dmareq;
291 sync_dev = tusb_dma->sync_dev;
292 omap_set_dma_callback(ch, tusb_omap_dma_cb, channel);
295 chdat->packet_sz = packet_sz;
297 channel->actual_len = 0;
298 chdat->dma_addr = (void __iomem *)dma_addr;
299 channel->status = MUSB_DMA_STATUS_BUSY;
301 /* Since we're recycling dma areas, we need to clean or invalidate */
303 consistent_sync(phys_to_virt(dma_addr), len, DMA_TO_DEVICE);
305 consistent_sync(phys_to_virt(dma_addr), len, DMA_FROM_DEVICE);
307 /* Use 16-bit transfer if dma_addr is not 32-bit aligned */
308 if ((dma_addr & 0x3) == 0) {
309 dma_params.data_type = OMAP_DMA_DATA_TYPE_S32;
310 dma_params.elem_count = 8; /* Elements in frame */
312 dma_params.data_type = OMAP_DMA_DATA_TYPE_S16;
313 dma_params.elem_count = 16; /* Elements in frame */
314 fifo = hw_ep->fifo_async;
317 dma_params.frame_count = chdat->transfer_len / 32; /* Burst sz frame */
319 DBG(2, "ep%i %s dma ch%i dma: %08x len: %u(%u) packet_sz: %i(%i)\n",
320 chdat->epnum, chdat->tx ? "tx" : "rx",
321 ch, dma_addr, chdat->transfer_len, len,
322 chdat->transfer_packet_sz, packet_sz);
325 * Prepare omap DMA for transfer
328 dma_params.src_amode = OMAP_DMA_AMODE_POST_INC;
329 dma_params.src_start = (unsigned long)dma_addr;
330 dma_params.src_ei = 0;
331 dma_params.src_fi = 0;
333 dma_params.dst_amode = OMAP_DMA_AMODE_DOUBLE_IDX;
334 dma_params.dst_start = (unsigned long)fifo;
335 dma_params.dst_ei = 1;
336 dma_params.dst_fi = -31; /* Loop 32 byte window */
338 dma_params.trigger = sync_dev;
339 dma_params.sync_mode = OMAP_DMA_SYNC_FRAME;
340 dma_params.src_or_dst_synch = 0; /* Dest sync */
342 src_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 read */
343 dst_burst = OMAP_DMA_DATA_BURST_8; /* 8x32 write */
345 dma_params.src_amode = OMAP_DMA_AMODE_DOUBLE_IDX;
346 dma_params.src_start = (unsigned long)fifo;
347 dma_params.src_ei = 1;
348 dma_params.src_fi = -31; /* Loop 32 byte window */
350 dma_params.dst_amode = OMAP_DMA_AMODE_POST_INC;
351 dma_params.dst_start = (unsigned long)dma_addr;
352 dma_params.dst_ei = 0;
353 dma_params.dst_fi = 0;
355 dma_params.trigger = sync_dev;
356 dma_params.sync_mode = OMAP_DMA_SYNC_FRAME;
357 dma_params.src_or_dst_synch = 1; /* Source sync */
359 src_burst = OMAP_DMA_DATA_BURST_8; /* 8x32 read */
360 dst_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 write */
363 DBG(2, "ep%i %s using %i-bit %s dma from 0x%08lx to 0x%08lx\n",
364 chdat->epnum, chdat->tx ? "tx" : "rx",
365 (dma_params.data_type == OMAP_DMA_DATA_TYPE_S32) ? 32 : 16,
366 ((dma_addr & 0x3) == 0) ? "sync" : "async",
367 dma_params.src_start, dma_params.dst_start);
369 omap_set_dma_params(ch, &dma_params);
370 omap_set_dma_src_burst_mode(ch, src_burst);
371 omap_set_dma_dest_burst_mode(ch, dst_burst);
372 omap_set_dma_write_mode(ch, OMAP_DMA_WRITE_LAST_NON_POSTED);
375 * Prepare MUSB for DMA transfer
378 musb_ep_select(musb_base, chdat->epnum);
379 csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
380 csr |= (MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB
381 | MUSB_TXCSR_DMAMODE | MUSB_TXCSR_MODE);
382 csr &= ~MUSB_TXCSR_P_UNDERRUN;
383 musb_writew(hw_ep->regs, MUSB_TXCSR, csr);
385 musb_ep_select(musb_base, chdat->epnum);
386 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
387 csr |= MUSB_RXCSR_DMAENAB;
388 csr &= ~(MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAMODE);
389 musb_writew(hw_ep->regs, MUSB_RXCSR,
390 csr | MUSB_RXCSR_P_WZC_BITS);
399 /* Send transfer_packet_sz packets at a time */
400 musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET,
401 chdat->transfer_packet_sz);
403 musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
404 TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len));
406 /* Receive transfer_packet_sz packets at a time */
407 musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET,
408 chdat->transfer_packet_sz << 16);
410 musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
411 TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len));
417 static int tusb_omap_dma_abort(struct dma_channel *channel)
419 struct tusb_omap_dma_ch *chdat = to_chdat(channel);
420 struct tusb_omap_dma *tusb_dma = chdat->tusb_dma;
422 if (!dmareq_works()) {
423 if (tusb_dma->ch >= 0) {
424 omap_stop_dma(tusb_dma->ch);
425 omap_free_dma(tusb_dma->ch);
429 tusb_dma->dmareq = -1;
430 tusb_dma->sync_dev = -1;
433 channel->status = MUSB_DMA_STATUS_FREE;
438 static inline int tusb_omap_dma_allocate_dmareq(struct tusb_omap_dma_ch *chdat)
440 u32 reg = musb_readl(chdat->tusb_base, TUSB_DMA_EP_MAP);
441 int i, dmareq_nr = -1;
443 const int sync_dev[6] = {
444 OMAP24XX_DMA_EXT_DMAREQ0,
445 OMAP24XX_DMA_EXT_DMAREQ1,
446 OMAP24XX_DMA_EXT_DMAREQ2,
447 OMAP24XX_DMA_EXT_DMAREQ3,
448 OMAP24XX_DMA_EXT_DMAREQ4,
449 OMAP24XX_DMA_EXT_DMAREQ5,
452 for (i = 0; i < MAX_DMAREQ; i++) {
453 int cur = (reg & (0xf << (i * 5))) >> (i * 5);
463 reg |= (chdat->epnum << (dmareq_nr * 5));
465 reg |= ((1 << 4) << (dmareq_nr * 5));
466 musb_writel(chdat->tusb_base, TUSB_DMA_EP_MAP, reg);
468 chdat->dmareq = dmareq_nr;
469 chdat->sync_dev = sync_dev[chdat->dmareq];
474 static inline void tusb_omap_dma_free_dmareq(struct tusb_omap_dma_ch *chdat)
478 if (!chdat || chdat->dmareq < 0)
481 reg = musb_readl(chdat->tusb_base, TUSB_DMA_EP_MAP);
482 reg &= ~(0x1f << (chdat->dmareq * 5));
483 musb_writel(chdat->tusb_base, TUSB_DMA_EP_MAP, reg);
486 chdat->sync_dev = -1;
489 static struct dma_channel *dma_channel_pool[MAX_DMAREQ];
491 static struct dma_channel *
492 tusb_omap_dma_allocate(struct dma_controller *c,
493 struct musb_hw_ep *hw_ep,
497 const char *dev_name;
498 struct tusb_omap_dma *tusb_dma;
500 void __iomem *tusb_base;
501 struct dma_channel *channel = NULL;
502 struct tusb_omap_dma_ch *chdat = NULL;
505 tusb_dma = container_of(c, struct tusb_omap_dma, controller);
506 musb = tusb_dma->musb;
507 tusb_base = musb->ctrl_base;
509 reg = musb_readl(tusb_base, TUSB_DMA_INT_MASK);
511 reg &= ~(1 << hw_ep->epnum);
513 reg &= ~(1 << (hw_ep->epnum + 15));
514 musb_writel(tusb_base, TUSB_DMA_INT_MASK, reg);
516 /* REVISIT: Why does dmareq5 not work? */
517 if (hw_ep->epnum == 0) {
518 DBG(3, "Not allowing DMA for ep0 %s\n", tx ? "tx" : "rx");
522 for (i = 0; i < MAX_DMAREQ; i++) {
523 struct dma_channel *ch = dma_channel_pool[i];
524 if (ch->status == MUSB_DMA_STATUS_UNKNOWN) {
525 ch->status = MUSB_DMA_STATUS_FREE;
527 chdat = ch->private_data;
537 dev_name = "TUSB transmit";
540 dev_name = "TUSB receive";
543 chdat->musb = tusb_dma->musb;
544 chdat->tusb_base = tusb_dma->tusb_base;
545 chdat->hw_ep = hw_ep;
546 chdat->epnum = hw_ep->epnum;
548 chdat->completed_len = 0;
549 chdat->tusb_dma = tusb_dma;
551 channel->max_len = 0x7fffffff;
552 channel->desired_mode = 0;
553 channel->actual_len = 0;
555 if (dmareq_works()) {
556 ret = tusb_omap_dma_allocate_dmareq(chdat);
560 ret = omap_request_dma(chdat->sync_dev, dev_name,
561 tusb_omap_dma_cb, channel, &chdat->ch);
564 } else if (tusb_dma->ch == -1) {
565 tusb_dma->dmareq = 0;
566 tusb_dma->sync_dev = OMAP24XX_DMA_EXT_DMAREQ0;
568 /* Callback data gets set later in the shared dmareq case */
569 ret = omap_request_dma(tusb_dma->sync_dev, "TUSB shared",
570 tusb_omap_dma_cb, NULL, &tusb_dma->ch);
578 DBG(3, "ep%i %s dma: %s dma%i dmareq%i sync%i\n",
580 chdat->tx ? "tx" : "rx",
581 chdat->ch >=0 ? "dedicated" : "shared",
582 chdat->ch >= 0 ? chdat->ch : tusb_dma->ch,
583 chdat->dmareq >= 0 ? chdat->dmareq : tusb_dma->dmareq,
584 chdat->sync_dev >= 0 ? chdat->sync_dev : tusb_dma->sync_dev);
589 tusb_omap_dma_free_dmareq(chdat);
591 DBG(3, "ep%i: Could not get a DMA channel\n", chdat->epnum);
592 channel->status = MUSB_DMA_STATUS_UNKNOWN;
597 static void tusb_omap_dma_release(struct dma_channel *channel)
599 struct tusb_omap_dma_ch *chdat = to_chdat(channel);
600 struct musb *musb = chdat->musb;
601 void __iomem *tusb_base = musb->ctrl_base;
604 DBG(3, "ep%i ch%i\n", chdat->epnum, chdat->ch);
606 reg = musb_readl(tusb_base, TUSB_DMA_INT_MASK);
608 reg |= (1 << chdat->epnum);
610 reg |= (1 << (chdat->epnum + 15));
611 musb_writel(tusb_base, TUSB_DMA_INT_MASK, reg);
613 reg = musb_readl(tusb_base, TUSB_DMA_INT_CLEAR);
615 reg |= (1 << chdat->epnum);
617 reg |= (1 << (chdat->epnum + 15));
618 musb_writel(tusb_base, TUSB_DMA_INT_CLEAR, reg);
620 channel->status = MUSB_DMA_STATUS_UNKNOWN;
622 if (chdat->ch >= 0) {
623 omap_stop_dma(chdat->ch);
624 omap_free_dma(chdat->ch);
628 if (chdat->dmareq >= 0)
629 tusb_omap_dma_free_dmareq(chdat);
634 void dma_controller_destroy(struct dma_controller *c)
636 struct tusb_omap_dma *tusb_dma;
639 tusb_dma = container_of(c, struct tusb_omap_dma, controller);
640 for (i = 0; i < MAX_DMAREQ; i++) {
641 struct dma_channel *ch = dma_channel_pool[i];
643 if (ch->private_data)
644 kfree(ch->private_data);
649 if (!dmareq_works() && tusb_dma && tusb_dma->ch >= 0)
650 omap_free_dma(tusb_dma->ch);
655 struct dma_controller *__init
656 dma_controller_create(struct musb *musb, void __iomem *base)
658 void __iomem *tusb_base = musb->ctrl_base;
659 struct tusb_omap_dma *tusb_dma;
662 /* REVISIT: Get dmareq lines used from board-*.c */
664 musb_writel(musb->ctrl_base, TUSB_DMA_INT_MASK, 0x7fffffff);
665 musb_writel(musb->ctrl_base, TUSB_DMA_EP_MAP, 0);
667 musb_writel(tusb_base, TUSB_DMA_REQ_CONF,
668 TUSB_DMA_REQ_CONF_BURST_SIZE(2)
669 | TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f)
670 | TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
672 tusb_dma = kzalloc(sizeof(struct tusb_omap_dma), GFP_KERNEL);
676 tusb_dma->musb = musb;
677 tusb_dma->tusb_base = musb->ctrl_base;
680 tusb_dma->dmareq = -1;
681 tusb_dma->sync_dev = -1;
683 tusb_dma->controller.start = tusb_omap_dma_start;
684 tusb_dma->controller.stop = tusb_omap_dma_stop;
685 tusb_dma->controller.channel_alloc = tusb_omap_dma_allocate;
686 tusb_dma->controller.channel_release = tusb_omap_dma_release;
687 tusb_dma->controller.channel_program = tusb_omap_dma_program;
688 tusb_dma->controller.channel_abort = tusb_omap_dma_abort;
689 tusb_dma->controller.private_data = tusb_dma;
691 for (i = 0; i < MAX_DMAREQ; i++) {
692 struct dma_channel *ch;
693 struct tusb_omap_dma_ch *chdat;
695 ch = kzalloc(sizeof(struct dma_channel), GFP_KERNEL);
699 dma_channel_pool[i] = ch;
701 chdat = kzalloc(sizeof(struct tusb_omap_dma_ch), GFP_KERNEL);
705 ch->status = MUSB_DMA_STATUS_UNKNOWN;
706 ch->private_data = chdat;
709 return &tusb_dma->controller;
712 dma_controller_destroy(&tusb_dma->controller);