2 * TUSB6010 USB 2.0 OTG Dual Role controller
4 * Copyright (C) 2006 Nokia Corporation
5 * Jarkko Nikula <jarkko.nikula@nokia.com>
6 * Tony Lindgren <tony@atomide.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 * - Driver assumes that interface to external host (main CPU) is
14 * configured for NOR FLASH interface instead of VLYNQ serial
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/init.h>
22 #include <linux/usb.h>
23 #include <linux/irq.h>
24 #include <linux/platform_device.h>
26 #include "musb_core.h"
28 static void tusb_source_power(struct musb *musb, int is_on);
30 #define TUSB_REV_MAJOR(reg_val) ((reg_val >> 4) & 0xf)
31 #define TUSB_REV_MINOR(reg_val) (reg_val & 0xf)
34 * Checks the revision. We need to use the DMA register as 3.0 does not
35 * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV.
37 static u8 tusb_get_revision(struct musb *musb)
39 void __iomem *base = musb->ctrl_base;
43 rev = musb_readl(base, TUSB_DMA_CTRL_REV) & 0xff;
44 if (TUSB_REV_MAJOR(rev) == 3) {
45 die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(base, TUSB_DIDR1_HI));
46 if (die_id == TUSB_DIDR1_HI_REV_31)
53 static int __init tusb_print_revision(struct musb *musb)
55 void __iomem *base = musb->ctrl_base;
58 rev = tusb_get_revision(musb);
60 pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n",
62 TUSB_REV_MAJOR(musb_readl(base, TUSB_PRCM_REV)),
63 TUSB_REV_MINOR(musb_readl(base, TUSB_PRCM_REV)),
65 TUSB_REV_MAJOR(musb_readl(base, TUSB_INT_CTRL_REV)),
66 TUSB_REV_MINOR(musb_readl(base, TUSB_INT_CTRL_REV)),
68 TUSB_REV_MAJOR(musb_readl(base, TUSB_GPIO_REV)),
69 TUSB_REV_MINOR(musb_readl(base, TUSB_GPIO_REV)),
71 TUSB_REV_MAJOR(musb_readl(base, TUSB_DMA_CTRL_REV)),
72 TUSB_REV_MINOR(musb_readl(base, TUSB_DMA_CTRL_REV)),
74 TUSB_DIDR1_HI_CHIP_REV(musb_readl(base, TUSB_DIDR1_HI)),
76 TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev));
78 return tusb_get_revision(musb);
81 #define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \
82 | TUSB_PHY_OTG_CTRL_TESTM0)
85 * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0.
86 * Disables power detection in PHY for the duration of idle.
88 static void tusb_wbus_quirk(struct musb *musb, int enabled)
90 void __iomem *base = musb->ctrl_base;
91 static u32 phy_otg_ctrl = 0, phy_otg_ena = 0;
95 phy_otg_ctrl = musb_readl(base, TUSB_PHY_OTG_CTRL);
96 phy_otg_ena = musb_readl(base, TUSB_PHY_OTG_CTRL_ENABLE);
97 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT
98 | phy_otg_ena | WBUS_QUIRK_MASK;
99 musb_writel(base, TUSB_PHY_OTG_CTRL, tmp);
100 tmp = phy_otg_ena & ~WBUS_QUIRK_MASK;
101 tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2;
102 musb_writel(base, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
103 DBG(2, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
104 musb_readl(base, TUSB_PHY_OTG_CTRL),
105 musb_readl(base, TUSB_PHY_OTG_CTRL_ENABLE));
106 } else if (musb_readl(base, TUSB_PHY_OTG_CTRL_ENABLE)
107 & TUSB_PHY_OTG_CTRL_TESTM2) {
108 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl;
109 musb_writel(base, TUSB_PHY_OTG_CTRL, tmp);
110 tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena;
111 musb_writel(base, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
112 DBG(2, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
113 musb_readl(base, TUSB_PHY_OTG_CTRL),
114 musb_readl(base, TUSB_PHY_OTG_CTRL_ENABLE));
121 * TUSB 6010 may use a parallel bus that doesn't support byte ops;
122 * so both loading and unloading FIFOs need explicit byte counts.
126 tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len)
132 for (i = 0; i < (len >> 2); i++) {
133 memcpy(&val, buf, 4);
134 musb_writel(fifo, 0, val);
140 /* Write the rest 1 - 3 bytes to FIFO */
141 memcpy(&val, buf, len);
142 musb_writel(fifo, 0, val);
146 static inline void tusb_fifo_read_unaligned(void __iomem *fifo,
147 void __iomem *buf, u16 len)
153 for (i = 0; i < (len >> 2); i++) {
154 val = musb_readl(fifo, 0);
155 memcpy(buf, &val, 4);
161 /* Read the rest 1 - 3 bytes from FIFO */
162 val = musb_readl(fifo, 0);
163 memcpy(buf, &val, len);
167 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
169 void __iomem *ep_conf = hw_ep->conf;
170 void __iomem *fifo = hw_ep->fifo;
171 u8 epnum = hw_ep->epnum;
175 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
176 'T', epnum, fifo, len, buf);
179 musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
180 TUSB_EP_CONFIG_XFR_SIZE(len));
182 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX |
183 TUSB_EP0_CONFIG_XFR_SIZE(len));
185 if (likely((0x01 & (unsigned long) buf) == 0)) {
187 /* Best case is 32bit-aligned destination address */
188 if ((0x02 & (unsigned long) buf) == 0) {
190 writesl(fifo, buf, len >> 2);
191 buf += (len & ~0x03);
199 /* Cannot use writesw, fifo is 32-bit */
200 for (i = 0; i < (len >> 2); i++) {
201 val = (u32)(*(u16 *)buf);
203 val |= (*(u16 *)buf) << 16;
205 musb_writel(fifo, 0, val);
213 tusb_fifo_write_unaligned(fifo, buf, len);
216 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
218 void __iomem *ep_conf = hw_ep->conf;
219 void __iomem *fifo = hw_ep->fifo;
220 u8 epnum = hw_ep->epnum;
222 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
223 'R', epnum, fifo, len, buf);
226 musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
227 TUSB_EP_CONFIG_XFR_SIZE(len));
229 musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len));
231 if (likely((0x01 & (unsigned long) buf) == 0)) {
233 /* Best case is 32bit-aligned destination address */
234 if ((0x02 & (unsigned long) buf) == 0) {
236 readsl(fifo, buf, len >> 2);
237 buf += (len & ~0x03);
245 /* Cannot use readsw, fifo is 32-bit */
246 for (i = 0; i < (len >> 2); i++) {
247 val = musb_readl(fifo, 0);
248 *(u16 *)buf = (u16)(val & 0xffff);
250 *(u16 *)buf = (u16)(val >> 16);
259 tusb_fifo_read_unaligned(fifo, buf, len);
262 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
264 /* This is used by gadget drivers, and OTG transceiver logic, allowing
265 * at most mA current to be drawn from VBUS during a Default-B session
266 * (that is, while VBUS exceeds 4.4V). In Default-A (including pure host
267 * mode), or low power Default-B sessions, something else supplies power.
268 * Caller must take care of locking.
270 static int tusb_draw_power(struct otg_transceiver *x, unsigned mA)
272 struct musb *musb = container_of(x, struct musb, xceiv);
273 void __iomem *base = musb->ctrl_base;
277 * Keep clock active when enabled. Note that this is not tied to
278 * drawing VBUS, as with OTG mA can be less than musb->min_power.
280 if (musb->set_clock) {
282 musb->set_clock(musb->clock, 1);
284 musb->set_clock(musb->clock, 0);
287 /* tps65030 seems to consume max 100mA, with maybe 60mA available
288 * (measured on one board) for things other than tps and tusb.
290 * Boards sharing the CPU clock with CLKIN will need to prevent
291 * certain idle sleep states while the USB link is active.
293 * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }.
294 * The actual current usage would be very board-specific. For now,
295 * it's simpler to just use an aggregate (also board-specific).
297 if (x->default_a || mA < (musb->min_power << 1))
300 reg = musb_readl(base, TUSB_PRCM_MNGMT);
302 musb->is_bus_powered = 1;
303 reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN;
305 musb->is_bus_powered = 0;
306 reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
308 musb_writel(base, TUSB_PRCM_MNGMT, reg);
310 DBG(2, "draw max %d mA VBUS\n", mA);
315 #define tusb_draw_power NULL
318 /* workaround for issue 13: change clock during chip idle
319 * (to be fixed in rev3 silicon) ... symptoms include disconnect
320 * or looping suspend/resume cycles
322 static void tusb_set_clock_source(struct musb *musb, unsigned mode)
324 void __iomem *base = musb->ctrl_base;
327 reg = musb_readl(base, TUSB_PRCM_CONF);
328 reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3);
330 /* 0 = refclk (clkin, XI)
331 * 1 = PHY 60 MHz (internal PLL)
336 reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3);
338 musb_writel(base, TUSB_PRCM_CONF, reg);
340 // FIXME tusb6010_platform_retime(mode == 0);
344 * Idle TUSB6010 until next wake-up event; NOR access always wakes.
345 * Other code ensures that we idle unless we're connected _and_ the
346 * USB link is not suspended ... and tells us the relevant wakeup
347 * events. SW_EN for voltage is handled separately.
349 void tusb_allow_idle(struct musb *musb, u32 wakeup_enables)
351 void __iomem *base = musb->ctrl_base;
354 if ((wakeup_enables & TUSB_PRCM_WBUS)
355 && (tusb_get_revision(musb) == TUSB_REV_30))
356 tusb_wbus_quirk(musb, 1);
358 tusb_set_clock_source(musb, 0);
360 wakeup_enables |= TUSB_PRCM_WNORCS;
361 musb_writel(base, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables);
363 /* REVISIT writeup of WID implies that if WID set and ID is grounded,
364 * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared.
365 * Presumably that's mostly to save power, hence WID is immaterial ...
368 reg = musb_readl(base, TUSB_PRCM_MNGMT);
369 /* issue 4: when driving vbus, use hipower (vbus_det) comparator */
370 if (is_host_active(musb)) {
371 reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
372 reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
374 reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
375 reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
377 reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE;
378 musb_writel(base, TUSB_PRCM_MNGMT, reg);
380 DBG(6, "idle, wake on %02x\n", wakeup_enables);
384 * Updates cable VBUS status. Caller must take care of locking.
386 int musb_platform_get_vbus_status(struct musb *musb)
388 void __iomem *base = musb->ctrl_base;
389 u32 otg_stat, prcm_mngmt;
392 otg_stat = musb_readl(base, TUSB_DEV_OTG_STAT);
393 prcm_mngmt = musb_readl(base, TUSB_PRCM_MNGMT);
395 /* Temporarily enable VBUS detection if it was disabled for
396 * suspend mode. Unless it's enabled otg_stat and devctl will
397 * not show correct VBUS state.
399 if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) {
400 u32 tmp = prcm_mngmt;
401 tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
402 musb_writel(base, TUSB_PRCM_MNGMT, tmp);
403 otg_stat = musb_readl(base, TUSB_DEV_OTG_STAT);
404 musb_writel(base, TUSB_PRCM_MNGMT, prcm_mngmt);
407 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID)
413 static struct timer_list musb_idle_timer;
415 static void musb_do_idle(unsigned long _musb)
417 struct musb *musb = (void *)_musb;
420 spin_lock_irqsave(&musb->lock, flags);
422 switch (musb->xceiv.state) {
423 case OTG_STATE_A_WAIT_BCON:
424 case OTG_STATE_A_WAIT_VRISE:
425 case OTG_STATE_A_IDLE:
426 if ((musb->a_wait_bcon != 0)
427 && (musb->idle_timeout == 0
428 || time_after(jiffies, musb->idle_timeout))) {
429 DBG(4, "Nothing connected %s, turning off VBUS\n",
430 otg_state_string(musb));
431 tusb_source_power(musb, 0);
432 musb->xceiv.state = OTG_STATE_A_IDLE;
440 if (!musb->is_active) {
443 /* wait until khubd handles port change status */
444 if (is_host_active(musb) && (musb->port1_status >> 16))
447 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
448 if (is_peripheral_enabled(musb) && !musb->gadget_driver)
451 wakeups = TUSB_PRCM_WHOSTDISCON
454 if (is_otg_enabled(musb))
455 wakeups |= TUSB_PRCM_WID;
458 wakeups = TUSB_PRCM_WHOSTDISCON | TUSB_PRCM_WBUS;
460 tusb_allow_idle(musb, wakeups);
463 spin_unlock_irqrestore(&musb->lock, flags);
467 * Maybe put TUSB6010 into idle mode mode depending on USB link status,
468 * like "disconnected" or "suspended". We'll be woken out of it by
469 * connect, resume, or disconnect.
471 * Needs to be called as the last function everywhere where there is
472 * register access to TUSB6010 because of NOR flash wake-up.
473 * Caller should own controller spinlock.
475 * Delay because peripheral enables D+ pullup 3msec after SE0, and
476 * we don't want to treat that full speed J as a wakeup event.
477 * ... peripherals must draw only suspend current after 10 msec.
479 void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
481 unsigned long default_timeout = jiffies + msecs_to_jiffies(3);
482 static unsigned long last_timer = 0;
485 timeout = default_timeout;
487 if (musb->is_active) {
488 DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
489 del_timer(&musb_idle_timer);
490 last_timer = jiffies;
494 if (time_after(last_timer, timeout)) {
495 if (!timer_pending(&musb_idle_timer))
496 last_timer = timeout;
498 DBG(4, "Longer idle timer already pending, ignoring\n");
502 last_timer = timeout;
504 DBG(4, "%s inactive, for idle timer for %lu ms\n",
505 otg_state_string(musb),
506 (unsigned long)jiffies_to_msecs(timeout - jiffies));
507 mod_timer(&musb_idle_timer, timeout);
510 /* ticks of 60 MHz clock */
511 #define DEVCLOCK 60000000
512 #define OTG_TIMER_MS(msecs) ((msecs) \
513 ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \
514 | TUSB_DEV_OTG_TIMER_ENABLE) \
517 static void tusb_source_power(struct musb *musb, int is_on)
519 void __iomem *base = musb->ctrl_base;
520 u32 conf, prcm, timer;
523 /* HDRC controls CPEN, but beware current surges during device
524 * connect. They can trigger transient overcurrent conditions
525 * that must be ignored.
528 prcm = musb_readl(base, TUSB_PRCM_MNGMT);
529 conf = musb_readl(base, TUSB_DEV_CONF);
530 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
534 musb->set_clock(musb->clock, 1);
536 timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE);
537 musb->xceiv.default_a = 1;
538 musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
539 devctl |= MUSB_DEVCTL_SESSION;
541 conf |= TUSB_DEV_CONF_USB_HOST_MODE;
548 /* If ID pin is grounded, we want to be a_idle */
549 otg_stat = musb_readl(base, TUSB_DEV_OTG_STAT);
550 if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) {
551 switch (musb->xceiv.state) {
552 case OTG_STATE_A_WAIT_VFALL:
555 case OTG_STATE_A_WAIT_VRISE:
557 musb->xceiv.state = OTG_STATE_A_WAIT_VFALL;
561 musb->xceiv.state = OTG_STATE_A_IDLE;
563 musb->xceiv.default_a = 1;
567 musb->xceiv.default_a = 0;
568 musb->xceiv.state = OTG_STATE_B_IDLE;
572 devctl &= ~MUSB_DEVCTL_SESSION;
573 conf &= ~TUSB_DEV_CONF_USB_HOST_MODE;
575 musb->set_clock(musb->clock, 0);
577 prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
579 musb_writel(base, TUSB_PRCM_MNGMT, prcm);
580 musb_writel(base, TUSB_DEV_OTG_TIMER, timer);
581 musb_writel(base, TUSB_DEV_CONF, conf);
582 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
584 DBG(1, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
585 otg_state_string(musb),
586 musb_readb(musb->mregs, MUSB_DEVCTL),
587 musb_readl(base, TUSB_DEV_OTG_STAT),
592 * Sets the mode to OTG, peripheral or host by changing the ID detection.
593 * Caller must take care of locking.
595 * Note that if a mini-A cable is plugged in the ID line will stay down as
596 * the weak ID pull-up is not able to pull the ID up.
598 * REVISIT: It would be possible to add support for changing between host
599 * and peripheral modes in non-OTG configurations by reconfiguring hardware
600 * and then setting musb->board_mode. For now, only support OTG mode.
602 void musb_platform_set_mode(struct musb *musb, u8 musb_mode)
604 void __iomem *base = musb->ctrl_base;
605 u32 otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf;
607 if (musb->board_mode != MUSB_OTG) {
608 ERR("Changing mode currently only supported in OTG mode\n");
612 otg_stat = musb_readl(base, TUSB_DEV_OTG_STAT);
613 phy_otg_ctrl = musb_readl(base, TUSB_PHY_OTG_CTRL);
614 phy_otg_ena = musb_readl(base, TUSB_PHY_OTG_CTRL_ENABLE);
615 dev_conf = musb_readl(base, TUSB_DEV_CONF);
619 #ifdef CONFIG_USB_MUSB_HDRC_HCD
620 case MUSB_HOST: /* Disable PHY ID detect, ground ID */
621 phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
622 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
623 dev_conf |= TUSB_DEV_CONF_ID_SEL;
624 dev_conf &= ~TUSB_DEV_CONF_SOFT_ID;
628 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
629 case MUSB_PERIPHERAL: /* Disable PHY ID detect, keep ID pull-up on */
630 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
631 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
632 dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
636 #ifdef CONFIG_USB_MUSB_OTG
637 case MUSB_OTG: /* Use PHY ID detection */
638 phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
639 phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
640 dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
645 DBG(2, "Trying to set unknown mode %i\n", musb_mode);
648 musb_writel(base, TUSB_PHY_OTG_CTRL,
649 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl);
650 musb_writel(base, TUSB_PHY_OTG_CTRL_ENABLE,
651 TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena);
652 musb_writel(base, TUSB_DEV_CONF, dev_conf);
654 otg_stat = musb_readl(base, TUSB_DEV_OTG_STAT);
655 if ((musb_mode == MUSB_PERIPHERAL) &&
656 !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS))
657 INFO("Cannot be peripheral with mini-A cable "
658 "otg_stat: %08x\n", otg_stat);
661 static inline unsigned long
662 tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *base)
664 u32 otg_stat = musb_readl(base, TUSB_DEV_OTG_STAT);
665 unsigned long idle_timeout = 0;
668 if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) {
671 if (is_otg_enabled(musb))
672 default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS);
674 default_a = is_host_enabled(musb);
675 DBG(2, "Default-%c\n", default_a ? 'A' : 'B');
676 musb->xceiv.default_a = default_a;
677 tusb_source_power(musb, default_a);
679 /* Don't allow idling immediately */
681 idle_timeout = jiffies + (HZ * 3);
684 /* VBUS state change */
685 if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) {
687 /* B-dev state machine: no vbus ~= disconnect */
688 if ((is_otg_enabled(musb) && !musb->xceiv.default_a)
689 || !is_host_enabled(musb)) {
690 #ifdef CONFIG_USB_MUSB_HDRC_HCD
691 // ? musb_root_disconnect(musb);
692 musb->port1_status &=
693 ~(USB_PORT_STAT_CONNECTION
694 | USB_PORT_STAT_ENABLE
695 | USB_PORT_STAT_LOW_SPEED
696 | USB_PORT_STAT_HIGH_SPEED
701 if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
702 DBG(1, "Forcing disconnect (no interrupt)\n");
703 if (musb->xceiv.state != OTG_STATE_B_IDLE) {
704 /* INTR_DISCONNECT can hide... */
705 musb->xceiv.state = OTG_STATE_B_IDLE;
706 musb->int_usb |= MUSB_INTR_DISCONNECT;
710 DBG(2, "vbus change, %s, otg %03x\n",
711 otg_state_string(musb), otg_stat);
712 idle_timeout = jiffies + (1 * HZ);
713 schedule_work(&musb->irq_work);
715 } else /* A-dev state machine */ {
718 DBG(2, "vbus change, %s, otg %03x\n",
719 otg_state_string(musb), otg_stat);
721 switch (musb->xceiv.state) {
722 case OTG_STATE_A_IDLE:
723 DBG(2, "Got SRP, turning on VBUS\n");
724 devctl = musb_readb(musb->mregs,
726 devctl |= MUSB_DEVCTL_SESSION;
727 musb_writeb(musb->mregs, MUSB_DEVCTL,
729 musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
731 /* CONNECT can wake if a_wait_bcon is set */
732 if (musb->a_wait_bcon != 0)
738 * OPT FS A TD.4.6 needs few seconds for
741 idle_timeout = jiffies + (2 * HZ);
744 case OTG_STATE_A_WAIT_VRISE:
745 /* ignore; A-session-valid < VBUS_VALID/2,
746 * we monitor this with the timer
749 case OTG_STATE_A_WAIT_VFALL:
750 /* REVISIT this irq triggers during short
751 * spikes causet by enumeration ...
753 if (musb->vbuserr_retry) {
754 musb->vbuserr_retry--;
755 tusb_source_power(musb, 1);
758 = VBUSERR_RETRY_COUNT;
759 tusb_source_power(musb, 0);
768 /* OTG timer expiration */
769 if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) {
772 DBG(4, "%s timer, %03x\n", otg_state_string(musb), otg_stat);
774 switch (musb->xceiv.state) {
775 case OTG_STATE_A_WAIT_VRISE:
776 /* VBUS has probably been valid for a while now,
777 * but may well have bounced out of range a bit
779 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
780 if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
781 if ((devctl & MUSB_DEVCTL_VBUS)
782 != MUSB_DEVCTL_VBUS) {
783 DBG(2, "devctl %02x\n", devctl);
786 musb->xceiv.state = OTG_STATE_A_WAIT_BCON;
787 /* CONNECT can wake if a_wait_bcon is set */
788 if (musb->a_wait_bcon != 0)
792 idle_timeout = jiffies
793 + msecs_to_jiffies(musb->a_wait_bcon);
795 /* REVISIT report overcurrent to hub? */
796 ERR("vbus too slow, devctl %02x\n", devctl);
797 tusb_source_power(musb, 0);
800 case OTG_STATE_A_WAIT_BCON:
801 if (musb->a_wait_bcon != 0)
802 idle_timeout = jiffies
803 + msecs_to_jiffies(musb->a_wait_bcon);
805 case OTG_STATE_A_SUSPEND:
807 case OTG_STATE_B_WAIT_ACON:
817 static irqreturn_t tusb_interrupt(int irq, void *__hci)
819 struct musb *musb = __hci;
820 void __iomem *base = musb->ctrl_base;
821 unsigned long flags, idle_timeout = 0;
822 u32 int_mask, int_src;
824 spin_lock_irqsave(&musb->lock, flags);
826 /* Mask all interrupts to allow using both edge and level GPIO irq */
827 int_mask = musb_readl(base, TUSB_INT_MASK);
828 musb_writel(base, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
830 int_src = musb_readl(base, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
831 DBG(3, "TUSB IRQ %08x\n", int_src);
833 musb->int_usb = (u8) int_src;
835 /* Acknowledge wake-up source interrupts */
836 if (int_src & TUSB_INT_SRC_DEV_WAKEUP) {
840 if (tusb_get_revision(musb) == TUSB_REV_30)
841 tusb_wbus_quirk(musb, 0);
843 /* there are issues re-locking the PLL on wakeup ... */
845 /* work around issue 8 */
846 for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) {
847 musb_writel(base, TUSB_SCRATCH_PAD, 0);
848 musb_writel(base, TUSB_SCRATCH_PAD, i);
849 reg = musb_readl(base, TUSB_SCRATCH_PAD);
852 DBG(6, "TUSB NOR not ready\n");
855 /* work around issue 13 (2nd half) */
856 tusb_set_clock_source(musb, 1);
858 reg = musb_readl(base, TUSB_PRCM_WAKEUP_SOURCE);
859 musb_writel(base, TUSB_PRCM_WAKEUP_CLEAR, reg);
860 if (reg & ~TUSB_PRCM_WNORCS) {
862 schedule_work(&musb->irq_work);
864 DBG(3, "wake %sactive %02x\n",
865 musb->is_active ? "" : "in", reg);
867 // REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS
870 if (int_src & TUSB_INT_SRC_USB_IP_CONN)
871 del_timer(&musb_idle_timer);
873 /* OTG state change reports (annoyingly) not issued by Mentor core */
874 if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG
875 | TUSB_INT_SRC_OTG_TIMEOUT
876 | TUSB_INT_SRC_ID_STATUS_CHNG))
877 idle_timeout = tusb_otg_ints(musb, int_src, base);
879 /* TX dma callback must be handled here, RX dma callback is
880 * handled in tusb_omap_dma_cb.
882 if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) {
883 u32 dma_src = musb_readl(base, TUSB_DMA_INT_SRC);
884 u32 real_dma_src = musb_readl(base, TUSB_DMA_INT_MASK);
886 DBG(3, "DMA IRQ %08x\n", dma_src);
887 real_dma_src = ~real_dma_src & dma_src;
888 if (tusb_dma_omap() && real_dma_src) {
889 int tx_source = (real_dma_src & 0xffff);
892 for (i = 1; i <= 15; i++) {
893 if (tx_source & (1 << i)) {
894 DBG(3, "completing ep%i %s\n", i, "tx");
895 musb_dma_completion(musb, i, 1);
899 musb_writel(base, TUSB_DMA_INT_CLEAR, dma_src);
902 /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB * interrupts */
903 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) {
904 u32 musb_src = musb_readl(base, TUSB_USBIP_INT_SRC);
906 musb_writel(base, TUSB_USBIP_INT_CLEAR, musb_src);
907 musb->int_rx = (((musb_src >> 16) & 0xffff) << 1);
908 musb->int_tx = (musb_src & 0xffff);
910 musb->int_rx = musb->int_tx = 0;
912 if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff))
913 musb_interrupt(musb);
915 /* Acknowledge TUSB interrupts. Clear only non-reserved bits */
916 musb_writel(base, TUSB_INT_SRC_CLEAR,
917 int_src & ~TUSB_INT_MASK_RESERVED_BITS);
919 musb_platform_try_idle(musb, idle_timeout);
921 musb_writel(base, TUSB_INT_MASK, int_mask);
922 spin_unlock_irqrestore(&musb->lock, flags);
930 * Enables TUSB6010. Caller must take care of locking.
932 * - Check what is unnecessary in MGC_HdrcStart()
934 void musb_platform_enable(struct musb * musb)
936 void __iomem *base = musb->ctrl_base;
938 /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF.
939 * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */
940 musb_writel(base, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF);
942 /* Setup TUSB interrupt, disable DMA and GPIO interrupts */
943 musb_writel(base, TUSB_USBIP_INT_MASK, 0);
944 musb_writel(base, TUSB_DMA_INT_MASK, 0x7fffffff);
945 musb_writel(base, TUSB_GPIO_INT_MASK, 0x1ff);
947 /* Clear all subsystem interrups */
948 musb_writel(base, TUSB_USBIP_INT_CLEAR, 0x7fffffff);
949 musb_writel(base, TUSB_DMA_INT_CLEAR, 0x7fffffff);
950 musb_writel(base, TUSB_GPIO_INT_CLEAR, 0x1ff);
952 /* Acknowledge pending interrupt(s) */
953 musb_writel(base, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS);
955 /* Only 0 clock cycles for minimum interrupt de-assertion time and
956 * interrupt polarity active low seems to work reliably here */
957 musb_writel(base, TUSB_INT_CTRL_CONF,
958 TUSB_INT_CTRL_CONF_INT_RELCYC(0));
960 set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW);
962 /* maybe force into the Default-A OTG state machine */
963 if (!(musb_readl(base, TUSB_DEV_OTG_STAT)
964 & TUSB_DEV_OTG_STAT_ID_STATUS))
965 musb_writel(base, TUSB_INT_SRC_SET,
966 TUSB_INT_SRC_ID_STATUS_CHNG);
968 if (is_dma_capable() && dma_off)
969 printk(KERN_WARNING "%s %s: dma not reactivated\n",
970 __FILE__, __FUNCTION__);
976 * Disables TUSB6010. Caller must take care of locking.
978 void musb_platform_disable(struct musb *musb)
980 void __iomem *base = musb->ctrl_base;
982 /* FIXME stop DMA, IRQs, timers, ... */
984 /* disable all IRQs */
985 musb_writel(base, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
986 musb_writel(base, TUSB_USBIP_INT_MASK, 0);
987 musb_writel(base, TUSB_DMA_INT_MASK, 0x7fffffff);
988 musb_writel(base, TUSB_GPIO_INT_MASK, 0x1ff);
990 del_timer(&musb_idle_timer);
992 if (is_dma_capable() && !dma_off) {
993 printk(KERN_WARNING "%s %s: dma still active\n",
994 __FILE__, __FUNCTION__);
1000 * Sets up TUSB6010 CPU interface specific signals and registers
1001 * Note: Settings optimized for OMAP24xx
1003 static void __init tusb_setup_cpu_interface(struct musb *musb)
1005 void __iomem *base = musb->ctrl_base;
1008 * Disable GPIO[5:0] pullups (used as output DMA requests)
1009 * Don't disable GPIO[7:6] as they are needed for wake-up.
1011 musb_writel(base, TUSB_PULLUP_1_CTRL, 0x0000003F);
1013 /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */
1014 musb_writel(base, TUSB_PULLUP_2_CTRL, 0x01FFFFFF);
1016 /* Turn GPIO[5:0] to DMAREQ[5:0] signals */
1017 musb_writel(base, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f));
1019 /* Burst size 16x16 bits, all six DMA requests enabled, DMA request
1020 * de-assertion time 2 system clocks p 62 */
1021 musb_writel(base, TUSB_DMA_REQ_CONF,
1022 TUSB_DMA_REQ_CONF_BURST_SIZE(2) |
1023 TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) |
1024 TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
1026 /* Set 0 wait count for synchronous burst access */
1027 musb_writel(base, TUSB_WAIT_COUNT, 1);
1030 static int __init tusb_start(struct musb *musb)
1032 void __iomem *base = musb->ctrl_base;
1034 unsigned long flags;
1037 if (musb->board_set_power)
1038 ret = musb->board_set_power(1);
1040 printk(KERN_ERR "tusb: Cannot enable TUSB6010\n");
1044 spin_lock_irqsave(&musb->lock, flags);
1046 if (musb_readl(base, TUSB_PROD_TEST_RESET) !=
1047 TUSB_PROD_TEST_RESET_VAL) {
1048 printk(KERN_ERR "tusb: Unable to detect TUSB6010\n");
1052 ret = tusb_print_revision(musb);
1054 printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n",
1059 /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when
1060 * NOR FLASH interface is used */
1061 musb_writel(base, TUSB_VLYNQ_CTRL, 8);
1063 /* Select PHY free running 60MHz as a system clock */
1064 tusb_set_clock_source(musb, 1);
1066 /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for
1067 * power saving, enable VBus detect and session end comparators,
1068 * enable IDpullup, enable VBus charging */
1069 musb_writel(base, TUSB_PRCM_MNGMT,
1070 TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) |
1071 TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN |
1072 TUSB_PRCM_MNGMT_OTG_SESS_END_EN |
1073 TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN |
1074 TUSB_PRCM_MNGMT_OTG_ID_PULLUP);
1075 tusb_setup_cpu_interface(musb);
1077 /* simplify: always sense/pullup ID pins, as if in OTG mode */
1078 reg = musb_readl(base, TUSB_PHY_OTG_CTRL_ENABLE);
1079 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1080 musb_writel(base, TUSB_PHY_OTG_CTRL_ENABLE, reg);
1082 reg = musb_readl(base, TUSB_PHY_OTG_CTRL);
1083 reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
1084 musb_writel(base, TUSB_PHY_OTG_CTRL, reg);
1086 spin_unlock_irqrestore(&musb->lock, flags);
1091 spin_unlock_irqrestore(&musb->lock, flags);
1093 if (musb->board_set_power)
1094 musb->board_set_power(0);
1099 int __init musb_platform_init(struct musb *musb)
1101 struct platform_device *pdev;
1102 struct resource *mem;
1106 pdev = to_platform_device(musb->controller);
1108 /* dma address for async dma */
1109 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1110 musb->async = mem->start;
1112 /* dma address for sync dma */
1113 mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1115 pr_debug("no sync dma resource?\n");
1118 musb->sync = mem->start;
1120 sync = ioremap(mem->start, mem->end - mem->start + 1);
1122 pr_debug("ioremap for sync failed\n");
1125 musb->sync_va = sync;
1127 /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400,
1128 * FIFOs at 0x600, TUSB at 0x800
1130 musb->mregs += TUSB_BASE_OFFSET;
1132 ret = tusb_start(musb);
1134 printk(KERN_ERR "Could not start tusb6010 (%d)\n",
1138 musb->isr = tusb_interrupt;
1140 if (is_host_enabled(musb))
1141 musb->board_set_vbus = tusb_source_power;
1142 if (is_peripheral_enabled(musb))
1143 musb->xceiv.set_power = tusb_draw_power;
1145 setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
1150 int musb_platform_exit(struct musb *musb)
1152 del_timer_sync(&musb_idle_timer);
1154 if (musb->board_set_power)
1155 musb->board_set_power(0);
1157 iounmap(musb->sync_va);