1 /*****************************************************************
2 * Copyright 2005 Mentor Graphics Corporation
3 * Copyright (C) 2005-2006 by Texas Instruments
4 * Copyright (C) 2006 by Nokia Corporation
6 * This file is part of the Inventra Controller Driver for Linux.
8 * The Inventra Controller Driver for Linux is free software; you
9 * can redistribute it and/or modify it under the terms of the GNU
10 * General Public License version 2 as published by the Free Software
13 * The Inventra Controller Driver for Linux is distributed in
14 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
15 * without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 * License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with The Inventra Controller Driver for Linux ; if not,
21 * write to the Free Software Foundation, Inc., 59 Temple Place,
22 * Suite 330, Boston, MA 02111-1307 USA
24 * ANY DOWNLOAD, USE, REPRODUCTION, MODIFICATION OR DISTRIBUTION
25 * OF THIS DRIVER INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE
26 * OF THOSE TERMS.THIS DRIVER IS PROVIDED "AS IS" AND MENTOR GRAPHICS
27 * MAKES NO WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THIS DRIVER.
28 * MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES
29 * OF MERCHANTABILITY; FITNESS FOR A PARTICULAR PURPOSE AND
30 * NON-INFRINGEMENT. MENTOR GRAPHICS DOES NOT PROVIDE SUPPORT
31 * SERVICES OR UPDATES FOR THIS DRIVER, EVEN IF YOU ARE A MENTOR
32 * GRAPHICS SUPPORT CUSTOMER.
33 ******************************************************************/
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - <asm/arch/hdrc_cnf.h> for SOC or family details
86 * - platform_device for addressing, irq, and platform_data
87 * - platform_data is mostly for board-specific informarion
89 * Most of the conditional compilation will (someday) vanish.
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/platform_device.h>
100 #include <linux/clk.h>
105 #include <asm/arch/hardware.h>
106 #include <asm/arch/memory.h>
107 #include <asm/mach-types.h>
110 #include "musbdefs.h"
113 #ifdef CONFIG_ARCH_DAVINCI
120 unsigned debug = MUSB_DEBUG;
121 module_param(debug, uint, 0);
122 MODULE_PARM_DESC(debug, "initial debug message level");
124 #define MUSB_VERSION_SUFFIX "/dbg"
127 const char *otg_state_string(struct musb *musb)
131 snprintf(buf, sizeof buf, "otg-%d", musb->xceiv.state);
136 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
137 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
139 #define MUSB_VERSION_BASE "2.2a/db-0.5.2"
141 #ifndef MUSB_VERSION_SUFFIX
142 #define MUSB_VERSION_SUFFIX ""
144 #define MUSB_VERSION MUSB_VERSION_BASE MUSB_VERSION_SUFFIX
146 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
148 const char musb_driver_name[] = "musb_hdrc";
150 MODULE_DESCRIPTION(DRIVER_INFO);
151 MODULE_AUTHOR(DRIVER_AUTHOR);
152 MODULE_LICENSE("GPL");
155 /*-------------------------------------------------------------------------*/
157 static inline struct musb *dev_to_musb(struct device *dev)
159 #ifdef CONFIG_USB_MUSB_HDRC_HCD
160 /* usbcore insists dev->driver_data is a "struct hcd *" */
161 return hcd_to_musb(dev_get_drvdata(dev));
163 return dev_get_drvdata(dev);
167 /*-------------------------------------------------------------------------*/
169 #ifndef CONFIG_USB_TUSB6010
171 * Load an endpoint's FIFO
173 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 wCount, const u8 *pSource)
175 void __iomem *fifo = hw_ep->fifo;
177 prefetch((u8 *)pSource);
179 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
180 'T', hw_ep->bLocalEnd, fifo, wCount, pSource);
182 /* we can't assume unaligned reads work */
183 if (likely((0x01 & (unsigned long) pSource) == 0)) {
186 /* best case is 32bit-aligned source address */
187 if ((0x02 & (unsigned long) pSource) == 0) {
189 writesl(fifo, pSource + index, wCount >> 2);
190 index += wCount & ~0x03;
193 musb_writew(fifo, 0, *(u16*)&pSource[index]);
198 writesw(fifo, pSource + index, wCount >> 1);
199 index += wCount & ~0x01;
203 musb_writeb(fifo, 0, pSource[index]);
206 writesb(fifo, pSource, wCount);
211 * Unload an endpoint's FIFO
213 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 wCount, u8 *pDest)
215 void __iomem *fifo = hw_ep->fifo;
217 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
218 'R', hw_ep->bLocalEnd, fifo, wCount, pDest);
220 /* we can't assume unaligned writes work */
221 if (likely((0x01 & (unsigned long) pDest) == 0)) {
224 /* best case is 32bit-aligned destination address */
225 if ((0x02 & (unsigned long) pDest) == 0) {
227 readsl(fifo, pDest, wCount >> 2);
228 index = wCount & ~0x03;
231 *(u16*)&pDest[index] = musb_readw(fifo, 0);
236 readsw(fifo, pDest, wCount >> 1);
237 index = wCount & ~0x01;
241 pDest[index] = musb_readb(fifo, 0);
244 readsb(fifo, pDest, wCount);
248 #endif /* normal PIO */
251 /*-------------------------------------------------------------------------*/
253 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
254 static const u8 musb_test_packet[53] = {
255 /* implicit SYNC then DATA0 to start */
258 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
260 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
262 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
263 /* JJJJJJJKKKKKKK x8 */
264 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
266 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
267 /* JKKKKKKK x10, JK */
268 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
270 /* implicit CRC16 then EOP to end */
273 void musb_load_testpacket(struct musb *musb)
275 void __iomem *regs = musb->aLocalEnd[0].regs;
277 MGC_SelectEnd(musb->pRegs, 0);
278 musb_write_fifo(musb->control_ep,
279 sizeof(musb_test_packet), musb_test_packet);
280 musb_writew(regs, MGC_O_HDRC_CSR0, MGC_M_CSR0_TXPKTRDY);
283 /*-------------------------------------------------------------------------*/
286 * Interrupt Service Routine to record USB "global" interrupts.
287 * Since these do not happen often and signify things of
288 * paramount importance, it seems OK to check them individually;
289 * the order of the tests is specified in the manual
291 * @param pThis instance pointer
292 * @param bIntrUSB register contents
297 #define STAGE0_MASK (MGC_M_INTR_RESUME | MGC_M_INTR_SESSREQ \
298 | MGC_M_INTR_VBUSERROR | MGC_M_INTR_CONNECT \
301 static irqreturn_t musb_stage0_irq(struct musb * pThis, u8 bIntrUSB,
304 irqreturn_t handled = IRQ_NONE;
305 #ifdef CONFIG_USB_MUSB_HDRC_HCD
306 void __iomem *pBase = pThis->pRegs;
309 DBG(3, "<== Power=%02x, DevCtl=%02x, bIntrUSB=0x%x\n", power, devctl,
312 /* in host mode, the peripheral may issue remote wakeup.
313 * in peripheral mode, the host may resume the link.
314 * spurious RESUME irqs happen too, paired with SUSPEND.
316 if (bIntrUSB & MGC_M_INTR_RESUME) {
317 handled = IRQ_HANDLED;
318 DBG(3, "RESUME (%s)\n", otg_state_string(pThis));
320 if (devctl & MGC_M_DEVCTL_HM) {
321 #ifdef CONFIG_USB_MUSB_HDRC_HCD
322 switch (pThis->xceiv.state) {
323 case OTG_STATE_A_SUSPEND:
324 /* remote wakeup? later, GetPortStatus
325 * will stop RESUME signaling
327 if (power & MGC_M_POWER_RESUME) {
328 power &= ~MGC_M_POWER_SUSPENDM;
329 musb_writeb(pBase, MGC_O_HDRC_POWER,
330 power | MGC_M_POWER_RESUME);
332 pThis->port1_status |=
333 (USB_PORT_STAT_C_SUSPEND << 16)
334 | MUSB_PORT_STAT_RESUME;
335 pThis->rh_timer = jiffies
336 + msecs_to_jiffies(20);
338 pThis->xceiv.state = OTG_STATE_A_HOST;
339 pThis->is_active = 1;
340 usb_hcd_resume_root_hub(
343 } else if (power & MGC_M_POWER_SUSPENDM) {
345 pThis->int_usb &= ~MGC_M_INTR_SUSPEND;
348 case OTG_STATE_B_WAIT_ACON:
349 pThis->xceiv.state = OTG_STATE_B_PERIPHERAL;
350 pThis->is_active = 1;
351 MUSB_DEV_MODE(pThis);
354 WARN("bogus %s RESUME (%s)\n",
356 otg_state_string(pThis));
360 switch (pThis->xceiv.state) {
361 #ifdef CONFIG_USB_MUSB_HDRC_HCD
362 case OTG_STATE_A_SUSPEND:
363 /* possibly DISCONNECT is upcoming */
364 pThis->xceiv.state = OTG_STATE_A_HOST;
365 usb_hcd_resume_root_hub(musb_to_hcd(pThis));
368 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
369 case OTG_STATE_B_WAIT_ACON:
370 case OTG_STATE_B_PERIPHERAL:
371 /* disconnect while suspended? we may
372 * not get a disconnect irq...
374 if ((devctl & MGC_M_DEVCTL_VBUS)
375 != (3 << MGC_S_DEVCTL_VBUS)) {
376 pThis->int_usb |= MGC_M_INTR_DISCONNECT;
377 pThis->int_usb &= ~MGC_M_INTR_SUSPEND;
380 musb_g_resume(pThis);
382 case OTG_STATE_B_IDLE:
383 pThis->int_usb &= ~MGC_M_INTR_SUSPEND;
387 WARN("bogus %s RESUME (%s)\n",
389 otg_state_string(pThis));
394 #ifdef CONFIG_USB_MUSB_HDRC_HCD
395 /* see manual for the order of the tests */
396 if (bIntrUSB & MGC_M_INTR_SESSREQ) {
397 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(pThis));
399 /* IRQ arrives from ID pin sense or (later, if VBUS power
400 * is removed) SRP. responses are time critical:
401 * - turn on VBUS (with silicon-specific mechanism)
402 * - go through A_WAIT_VRISE
403 * - ... to A_WAIT_BCON.
404 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
406 musb_writeb(pBase, MGC_O_HDRC_DEVCTL, MGC_M_DEVCTL_SESSION);
407 pThis->bEnd0Stage = MGC_END0_START;
408 pThis->xceiv.state = OTG_STATE_A_IDLE;
409 MUSB_HST_MODE(pThis);
410 musb_set_vbus(pThis, 1);
412 handled = IRQ_HANDLED;
415 if (bIntrUSB & MGC_M_INTR_VBUSERROR) {
418 /* During connection as an A-Device, we may see a short
419 * current spikes causing voltage drop, because of cable
420 * and peripheral capacitance combined with vbus draw.
421 * (So: less common with truly self-powered devices, where
422 * vbus doesn't act like a power supply.)
424 * Such spikes are short; usually less than ~500 usec, max
425 * of ~2 msec. That is, they're not sustained overcurrent
426 * errors, though they're reported using VBUSERROR irqs.
428 * Workarounds: (a) hardware: use self powered devices.
429 * (b) software: ignore non-repeated VBUS errors.
431 * REVISIT: do delays from lots of DEBUG_KERNEL checks
432 * make trouble here, keeping VBUS < 4.4V ?
434 switch (pThis->xceiv.state) {
435 case OTG_STATE_A_HOST:
436 /* recovery is dicey once we've gotten past the
437 * initial stages of enumeration, but if VBUS
438 * stayed ok at the other end of the link, and
439 * another reset is due (at least for high speed,
440 * to redo the chirp etc), it might work OK...
442 case OTG_STATE_A_WAIT_BCON:
443 case OTG_STATE_A_WAIT_VRISE:
444 if (pThis->vbuserr_retry) {
445 pThis->vbuserr_retry--;
447 devctl |= MGC_M_DEVCTL_SESSION;
448 musb_writeb(pBase, MGC_O_HDRC_DEVCTL, devctl);
450 pThis->port1_status |=
451 (1 << USB_PORT_FEAT_OVER_CURRENT)
452 | (1 << USB_PORT_FEAT_C_OVER_CURRENT);
459 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
460 otg_state_string(pThis),
463 switch (devctl & MGC_M_DEVCTL_VBUS) {
464 case 0 << MGC_S_DEVCTL_VBUS:
465 s = "<SessEnd"; break;
466 case 1 << MGC_S_DEVCTL_VBUS:
467 s = "<AValid"; break;
468 case 2 << MGC_S_DEVCTL_VBUS:
469 s = "<VBusValid"; break;
470 //case 3 << MGC_S_DEVCTL_VBUS:
474 VBUSERR_RETRY_COUNT - pThis->vbuserr_retry,
475 pThis->port1_status);
477 /* go through A_WAIT_VFALL then start a new session */
479 musb_set_vbus(pThis, 0);
480 handled = IRQ_HANDLED;
483 if (bIntrUSB & MGC_M_INTR_CONNECT) {
484 struct usb_hcd *hcd = musb_to_hcd(pThis);
486 handled = IRQ_HANDLED;
487 pThis->is_active = 1;
488 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
490 pThis->bEnd0Stage = MGC_END0_START;
492 #ifdef CONFIG_USB_MUSB_OTG
493 /* flush endpoints when transitioning from Device Mode */
494 if (is_peripheral_active(pThis)) {
495 // REVISIT HNP; just force disconnect
497 pThis->bDelayPortPowerOff = FALSE;
499 pThis->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
500 |USB_PORT_STAT_HIGH_SPEED
501 |USB_PORT_STAT_ENABLE
503 pThis->port1_status |= USB_PORT_STAT_CONNECTION
504 |(USB_PORT_STAT_C_CONNECTION << 16);
506 /* high vs full speed is just a guess until after reset */
507 if (devctl & MGC_M_DEVCTL_LSDEV)
508 pThis->port1_status |= USB_PORT_STAT_LOW_SPEED;
511 usb_hcd_poll_rh_status(hcd);
513 usb_hcd_resume_root_hub(hcd);
515 MUSB_HST_MODE(pThis);
517 /* indicate new connection to OTG machine */
518 switch (pThis->xceiv.state) {
519 case OTG_STATE_B_WAIT_ACON:
520 pThis->xceiv.state = OTG_STATE_B_HOST;
523 if ((devctl & MGC_M_DEVCTL_VBUS)
524 == (3 << MGC_S_DEVCTL_VBUS))
525 pThis->xceiv.state = OTG_STATE_A_HOST;
528 DBG(1, "CONNECT (%s) devctl %02x\n",
529 otg_state_string(pThis), devctl);
531 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
533 /* mentor saves a bit: bus reset and babble share the same irq.
534 * only host sees babble; only peripheral sees bus reset.
536 if (bIntrUSB & MGC_M_INTR_RESET) {
537 if (devctl & MGC_M_DEVCTL_HM) {
540 /* REVISIT it's unclear how to handle this. Mentor's
541 * code stopped the whole USB host, which is clearly
542 * very wrong. Docs say (15.1) that babble ends the
543 * current sesssion, so shutdown _with restart_ would
544 * be appropriate ... except that seems to be wrong,
545 * at least some lowspeed enumerations trigger the
546 * babbles without aborting the session!
548 * (A "babble" IRQ seems quite pointless...)
552 DBG(1, "BUS RESET\n");
555 schedule_work(&pThis->irq_work);
558 handled = IRQ_HANDLED;
565 * Interrupt Service Routine to record USB "global" interrupts.
566 * Since these do not happen often and signify things of
567 * paramount importance, it seems OK to check them individually;
568 * the order of the tests is specified in the manual
570 * @param pThis instance pointer
571 * @param bIntrUSB register contents
575 static irqreturn_t musb_stage2_irq(struct musb * pThis, u8 bIntrUSB,
578 irqreturn_t handled = IRQ_NONE;
581 /* REVISIT ... this would be for multiplexing periodic endpoints, or
582 * supporting transfer phasing to prevent exceeding ISO bandwidth
583 * limits of a given frame or microframe.
585 * It's not needed for peripheral side, which dedicates endpoints;
586 * though it _might_ use SOF irqs for other purposes.
588 * And it's not currently needed for host side, which also dedicates
589 * endpoints, relies on TX/RX interval registers, and isn't claimed
590 * to support ISO transfers yet.
592 if (bIntrUSB & MGC_M_INTR_SOF) {
593 void __iomem *pBase = pThis->pRegs;
594 struct musb_hw_ep *ep;
598 DBG(6, "START_OF_FRAME\n");
599 handled = IRQ_HANDLED;
601 /* start any periodic Tx transfers waiting for current frame */
602 wFrame = musb_readw(pBase, MGC_O_HDRC_FRAME);
603 ep = pThis->aLocalEnd;
604 for (bEnd = 1; (bEnd < pThis->bEndCount)
605 && (pThis->wEndMask >= (1 << bEnd));
607 // FIXME handle framecounter wraps (12 bits)
608 // eliminate duplicated StartUrb logic
609 if (ep->dwWaitFrame >= wFrame) {
611 printk("SOF --> periodic TX%s on %d\n",
612 ep->tx_channel ? " DMA" : "",
615 musb_h_tx_start(pThis, bEnd);
617 cppi_hostdma_start(pThis, bEnd);
619 } /* end of for loop */
623 if ((bIntrUSB & MGC_M_INTR_DISCONNECT) && !pThis->bIgnoreDisconnect) {
624 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
625 otg_state_string(pThis),
626 MUSB_MODE(pThis), devctl);
627 handled = IRQ_HANDLED;
629 switch (pThis->xceiv.state) {
630 #ifdef CONFIG_USB_MUSB_HDRC_HCD
631 case OTG_STATE_A_HOST:
632 case OTG_STATE_A_SUSPEND:
633 musb_root_disconnect(pThis);
636 #ifdef CONFIG_USB_MUSB_OTG
637 case OTG_STATE_A_PERIPHERAL:
638 case OTG_STATE_B_HOST:
639 musb_root_disconnect(pThis);
641 case OTG_STATE_B_WAIT_ACON:
643 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
644 case OTG_STATE_B_PERIPHERAL:
645 musb_g_disconnect(pThis);
649 WARN("unhandled DISCONNECT transition (%s)\n",
650 otg_state_string(pThis));
654 schedule_work(&pThis->irq_work);
657 if (bIntrUSB & MGC_M_INTR_SUSPEND) {
658 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
659 otg_state_string(pThis), devctl, power);
660 handled = IRQ_HANDLED;
662 switch (pThis->xceiv.state) {
663 case OTG_STATE_B_PERIPHERAL:
664 musb_g_suspend(pThis);
665 pThis->is_active = is_otg_enabled(pThis)
666 && pThis->xceiv.gadget->b_hnp_enable;
667 if (pThis->is_active) {
668 pThis->xceiv.state = OTG_STATE_B_WAIT_ACON;
669 /* REVISIT timeout for b_ase0_brst, etc */
672 case OTG_STATE_A_HOST:
673 pThis->xceiv.state = OTG_STATE_A_SUSPEND;
674 pThis->is_active = is_otg_enabled(pThis)
675 && pThis->xceiv.host->b_hnp_enable;
678 /* "should not happen" */
679 pThis->is_active = 0;
688 /*-------------------------------------------------------------------------*/
691 * Program the HDRC to start (enable interrupts, dma, etc.).
693 void musb_start(struct musb *musb)
695 void __iomem *regs = musb->pRegs;
696 u8 devctl = musb_readb(regs, MGC_O_HDRC_DEVCTL);
698 DBG(2, "<== devctl %02x\n", devctl);
700 /* Set INT enable registers, enable interrupts */
701 musb_writew(regs, MGC_O_HDRC_INTRTXE, musb->wEndMask);
702 musb_writew(regs, MGC_O_HDRC_INTRRXE, musb->wEndMask & 0xfffe);
703 musb_writeb(regs, MGC_O_HDRC_INTRUSBE, 0xf7);
705 musb_writeb(regs, MGC_O_HDRC_TESTMODE, 0);
707 /* put into basic highspeed mode and start session */
708 musb_writeb(regs, MGC_O_HDRC_POWER, MGC_M_POWER_ISOUPDATE
709 | MGC_M_POWER_SOFTCONN
711 /* ENSUSPEND wedges tusb */
712 // | MGC_M_POWER_ENSUSPEND
716 devctl = musb_readb(regs, MGC_O_HDRC_DEVCTL);
717 devctl &= ~MGC_M_DEVCTL_SESSION;
719 if (is_otg_enabled(musb)) {
720 /* session started after:
721 * (a) ID-grounded irq, host mode;
722 * (b) vbus present/connect IRQ, peripheral mode;
723 * (c) peripheral initiates, using SRP
725 if ((devctl & MGC_M_DEVCTL_VBUS) == MGC_M_DEVCTL_VBUS)
728 devctl |= MGC_M_DEVCTL_SESSION;
730 } else if (is_host_enabled(musb)) {
731 /* assume ID pin is hard-wired to ground */
732 devctl |= MGC_M_DEVCTL_SESSION;
734 } else /* peripheral is enabled */ {
735 if ((devctl & MGC_M_DEVCTL_VBUS) == MGC_M_DEVCTL_VBUS)
738 musb_platform_enable(musb);
739 musb_writeb(regs, MGC_O_HDRC_DEVCTL, devctl);
743 static void musb_generic_disable(struct musb *pThis)
745 void __iomem *pBase = pThis->pRegs;
748 /* disable interrupts */
749 musb_writeb(pBase, MGC_O_HDRC_INTRUSBE, 0);
750 musb_writew(pBase, MGC_O_HDRC_INTRTX, 0);
751 musb_writew(pBase, MGC_O_HDRC_INTRRX, 0);
754 musb_writeb(pBase, MGC_O_HDRC_DEVCTL, 0);
756 /* flush pending interrupts */
757 temp = musb_readb(pBase, MGC_O_HDRC_INTRUSB);
758 temp = musb_readw(pBase, MGC_O_HDRC_INTRTX);
759 temp = musb_readw(pBase, MGC_O_HDRC_INTRRX);
764 * Make the HDRC stop (disable interrupts, etc.);
765 * reversible by musb_start
766 * called on gadget driver unregister
767 * with controller locked, irqs blocked
768 * acts as a NOP unless some role activated the hardware
770 void musb_stop(struct musb *musb)
772 /* stop IRQs, timers, ... */
773 musb_platform_disable(musb);
774 musb_generic_disable(musb);
775 DBG(3, "HDRC disabled\n");
778 * - mark host and/or peripheral drivers unusable/inactive
779 * - disable DMA (and enable it in HdrcStart)
780 * - make sure we can musb_start() after musb_stop(); with
781 * OTG mode, gadget driver module rmmod/modprobe cycles that
784 musb_platform_try_idle(musb);
787 static void musb_shutdown(struct platform_device *pdev)
789 struct musb *musb = dev_to_musb(&pdev->dev);
792 spin_lock_irqsave(&musb->Lock, flags);
793 musb_platform_disable(musb);
794 musb_generic_disable(musb);
795 spin_unlock_irqrestore(&musb->Lock, flags);
797 /* FIXME power down */
801 /*-------------------------------------------------------------------------*/
804 * The silicon either has hard-wired endpoint configurations, or else
805 * "dynamic fifo" sizing. The driver has support for both, though at this
806 * writing only the dynamic sizing is very well tested. We use normal
807 * idioms to so both modes are compile-tested, but dead code elimination
808 * leaves only the relevant one in the object file.
810 * We don't currently use dynamic fifo setup capability to do anything
811 * more than selecting one of a bunch of predefined configurations.
813 #ifdef MUSB_C_DYNFIFO_DEF
814 #define can_dynfifo() 1
816 #define can_dynfifo() 0
819 #ifdef CONFIG_USB_TUSB6010
820 static ushort __initdata fifo_mode = 4;
822 static ushort __initdata fifo_mode = 2;
825 /* "modprobe ... fifo_mode=1" etc */
826 module_param(fifo_mode, ushort, 0);
827 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
830 #define DYN_FIFO_SIZE (1<<(MUSB_C_RAM_BITS+2))
832 enum fifo_style { FIFO_RXTX, FIFO_TX, FIFO_RX } __attribute__ ((packed));
833 enum buf_mode { BUF_SINGLE, BUF_DOUBLE } __attribute__ ((packed));
837 enum fifo_style style;
843 * tables defining fifo_mode values. define more if you like.
844 * for host side, make sure both halves of ep1 are set up.
847 /* mode 0 - fits in 2KB */
848 static struct fifo_cfg __initdata mode_0_cfg[] = {
849 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
850 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
851 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
852 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
853 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
856 /* mode 1 - fits in 4KB */
857 static struct fifo_cfg __initdata mode_1_cfg[] = {
858 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
859 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
860 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
861 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
862 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
865 /* mode 2 - fits in 4KB */
866 static struct fifo_cfg __initdata mode_2_cfg[] = {
867 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
868 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
869 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
870 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
871 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
872 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
875 /* mode 3 - fits in 4KB */
876 static struct fifo_cfg __initdata mode_3_cfg[] = {
877 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
878 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
879 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
880 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
881 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
882 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
885 /* mode 4 - fits in 16KB */
886 static struct fifo_cfg __initdata mode_4_cfg[] = {
887 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
888 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
889 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
890 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
891 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
892 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
893 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
894 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
895 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
896 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
897 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
898 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
899 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
900 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
901 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
902 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
903 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
904 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
905 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 512, },
906 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 512, },
907 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 512, },
908 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 512, },
909 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 512, },
910 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 512, },
911 { .hw_ep_num = 13, .style = FIFO_TX, .maxpacket = 512, },
912 { .hw_ep_num = 13, .style = FIFO_RX, .maxpacket = 512, },
913 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
914 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
919 * configure a fifo; for non-shared endpoints, this may be called
920 * once for a tx fifo and once for an rx fifo.
922 * returns negative errno or offset for next fifo.
925 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
926 const struct fifo_cfg *cfg, u16 offset)
928 void __iomem *mbase = musb->pRegs;
930 u16 maxpacket = cfg->maxpacket;
931 u16 c_off = offset >> 3;
934 /* expect hw_ep has already been zero-initialized */
936 size = ffs(max(maxpacket, (u16) 8)) - 1;
937 maxpacket = 1 << size;
940 if (cfg->mode == BUF_DOUBLE) {
941 if ((offset + (maxpacket << 1)) > DYN_FIFO_SIZE)
943 c_size |= MGC_M_FIFOSZ_DPB;
945 if ((offset + maxpacket) > DYN_FIFO_SIZE)
949 /* configure the FIFO */
950 musb_writeb(mbase, MGC_O_HDRC_INDEX, hw_ep->bLocalEnd);
952 #ifdef CONFIG_USB_MUSB_HDRC_HCD
953 /* EP0 reserved endpoint for control, bidirectional;
954 * EP1 reserved for bulk, two unidirection halves.
956 if (hw_ep->bLocalEnd == 1)
957 musb->bulk_ep = hw_ep;
958 /* REVISIT error check: be sure ep0 can both rx and tx ... */
960 switch (cfg->style) {
962 musb_writeb(mbase, MGC_O_HDRC_TXFIFOSZ, c_size);
963 musb_writew(mbase, MGC_O_HDRC_TXFIFOADD, c_off);
964 hw_ep->tx_double_buffered = !!(c_size & MGC_M_FIFOSZ_DPB);
965 hw_ep->wMaxPacketSizeTx = maxpacket;
968 musb_writeb(mbase, MGC_O_HDRC_RXFIFOSZ, c_size);
969 musb_writew(mbase, MGC_O_HDRC_RXFIFOADD, c_off);
970 hw_ep->rx_double_buffered = !!(c_size & MGC_M_FIFOSZ_DPB);
971 hw_ep->wMaxPacketSizeRx = maxpacket;
974 musb_writeb(mbase, MGC_O_HDRC_TXFIFOSZ, c_size);
975 musb_writew(mbase, MGC_O_HDRC_TXFIFOADD, c_off);
976 hw_ep->rx_double_buffered = !!(c_size & MGC_M_FIFOSZ_DPB);
977 hw_ep->wMaxPacketSizeRx = maxpacket;
979 musb_writeb(mbase, MGC_O_HDRC_RXFIFOSZ, c_size);
980 musb_writew(mbase, MGC_O_HDRC_RXFIFOADD, c_off);
981 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
982 hw_ep->wMaxPacketSizeTx = maxpacket;
984 hw_ep->bIsSharedFifo = TRUE;
988 /* NOTE rx and tx endpoint irqs aren't managed separately,
989 * which happens to be ok
991 musb->wEndMask |= (1 << hw_ep->bLocalEnd);
993 return offset + (maxpacket << ((c_size & MGC_M_FIFOSZ_DPB) ? 1 : 0));
996 static struct fifo_cfg __initdata ep0_cfg = {
997 .style = FIFO_RXTX, .maxpacket = 64,
1000 static int __init ep_config_from_table(struct musb *musb)
1002 const struct fifo_cfg *cfg;
1005 struct musb_hw_ep *hw_ep = musb->aLocalEnd;
1007 switch (fifo_mode) {
1013 n = ARRAY_SIZE(mode_0_cfg);
1017 n = ARRAY_SIZE(mode_1_cfg);
1021 n = ARRAY_SIZE(mode_2_cfg);
1025 n = ARRAY_SIZE(mode_3_cfg);
1029 n = ARRAY_SIZE(mode_4_cfg);
1033 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1034 musb_driver_name, fifo_mode);
1037 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1038 // assert(offset > 0)
1040 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1041 * be better than static MUSB_C_NUM_EPS and DYN_FIFO_SIZE...
1044 for (i = 0; i < n; i++) {
1045 u8 epn = cfg->hw_ep_num;
1047 if (epn >= MUSB_C_NUM_EPS) {
1048 pr_debug( "%s: invalid ep %d\n",
1049 musb_driver_name, epn);
1052 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1054 pr_debug( "%s: mem overrun, ep %d\n",
1055 musb_driver_name, epn);
1059 musb->bEndCount = max(epn, musb->bEndCount);
1062 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1064 n + 1, MUSB_C_NUM_EPS * 2 - 1,
1065 offset, DYN_FIFO_SIZE);
1067 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1068 if (!musb->bulk_ep) {
1069 pr_debug( "%s: missing bulk\n", musb_driver_name);
1079 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1080 * @param pThis the controller
1082 static int __init ep_config_from_hw(struct musb *musb)
1085 struct musb_hw_ep *pEnd;
1086 void *pBase = musb->pRegs;
1088 DBG(2, "<== static silicon ep config\n");
1090 /* FIXME pick up ep0 maxpacket size */
1092 for (bEnd = 1; bEnd < MUSB_C_NUM_EPS; bEnd++) {
1093 MGC_SelectEnd(pBase, bEnd);
1094 pEnd = musb->aLocalEnd + bEnd;
1096 /* read from core using indexed model */
1097 reg = musb_readb(pEnd->regs, 0x10 + MGC_O_HDRC_FIFOSIZE);
1099 /* 0's returned when no more endpoints */
1103 musb->wEndMask |= (1 << bEnd);
1105 pEnd->wMaxPacketSizeTx = 1 << (reg & 0x0f);
1107 /* shared TX/RX FIFO? */
1108 if ((reg & 0xf0) == 0xf0) {
1109 pEnd->wMaxPacketSizeRx = pEnd->wMaxPacketSizeTx;
1110 pEnd->bIsSharedFifo = TRUE;
1113 pEnd->wMaxPacketSizeRx = 1 << ((reg & 0xf0) >> 4);
1114 pEnd->bIsSharedFifo = FALSE;
1117 /* FIXME set up pEnd->{rx,tx}_double_buffered */
1119 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1120 /* pick an RX/TX endpoint for bulk */
1121 if (pEnd->wMaxPacketSizeTx < 512
1122 || pEnd->wMaxPacketSizeRx < 512)
1125 /* REVISIT: this algorithm is lazy, we should at least
1126 * try to pick a double buffered endpoint.
1130 musb->bulk_ep = pEnd;
1134 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1135 if (!musb->bulk_ep) {
1136 pr_debug( "%s: missing bulk\n", musb_driver_name);
1144 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1146 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1147 * configure endpoints, or take their config from silicon
1149 static int __init musb_core_init(u16 wType, struct musb *pThis)
1156 u16 wRelease, wRelMajor, wRelMinor;
1157 char aInfo[78], aRevision[32], aDate[12];
1158 void __iomem *pBase = pThis->pRegs;
1162 /* log core options (read using indexed model) */
1163 MGC_SelectEnd(pBase, 0);
1164 reg = musb_readb(pBase, 0x10 + MGC_O_HDRC_CONFIGDATA);
1166 strcpy(aInfo, (reg & MGC_M_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1167 if (reg & MGC_M_CONFIGDATA_DYNFIFO) {
1168 strcat(aInfo, ", dyn FIFOs");
1170 if (reg & MGC_M_CONFIGDATA_MPRXE) {
1171 strcat(aInfo, ", bulk combine");
1173 pThis->bBulkCombine = TRUE;
1175 strcat(aInfo, " (X)"); /* no driver support */
1178 if (reg & MGC_M_CONFIGDATA_MPTXE) {
1179 strcat(aInfo, ", bulk split");
1181 pThis->bBulkSplit = TRUE;
1183 strcat(aInfo, " (X)"); /* no driver support */
1186 if (reg & MGC_M_CONFIGDATA_HBRXE) {
1187 strcat(aInfo, ", HB-ISO Rx");
1188 strcat(aInfo, " (X)"); /* no driver support */
1190 if (reg & MGC_M_CONFIGDATA_HBTXE) {
1191 strcat(aInfo, ", HB-ISO Tx");
1192 strcat(aInfo, " (X)"); /* no driver support */
1194 if (reg & MGC_M_CONFIGDATA_SOFTCONE) {
1195 strcat(aInfo, ", SoftConn");
1198 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1199 musb_driver_name, reg, aInfo);
1202 dwData = musb_readl(pBase, 0x404);
1203 sprintf(aDate, "%04d-%02x-%02x", (dwData & 0xffff),
1204 (dwData >> 16) & 0xff, (dwData >> 24) & 0xff);
1205 /* FIXME ID2 and ID3 are unused */
1206 dwData = musb_readl(pBase, 0x408);
1207 printk("ID2=%lx\n", (long unsigned)dwData);
1208 dwData = musb_readl(pBase, 0x40c);
1209 printk("ID3=%lx\n", (long unsigned)dwData);
1210 reg = musb_readb(pBase, 0x400);
1211 wType = ('M' == reg) ? MUSB_CONTROLLER_MHDRC : MUSB_CONTROLLER_HDRC;
1215 if (MUSB_CONTROLLER_MHDRC == wType) {
1216 pThis->bIsMultipoint = 1;
1219 pThis->bIsMultipoint = 0;
1221 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1222 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1224 "%s: kernel must blacklist external hubs\n",
1230 /* log release info */
1231 wRelease = musb_readw(pBase, MGC_O_HDRC_HWVERS);
1232 wRelMajor = (wRelease >> 10) & 0x1f;
1233 wRelMinor = wRelease & 0x3ff;
1234 snprintf(aRevision, 32, "%d.%d%s", wRelMajor,
1235 wRelMinor, (wRelease & 0x8000) ? "RC" : "");
1236 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1237 musb_driver_name, type, aRevision, aDate);
1240 pThis->aLocalEnd[0].wMaxPacketSizeTx = MGC_END0_FIFOSIZE;
1241 pThis->aLocalEnd[0].wMaxPacketSizeRx = MGC_END0_FIFOSIZE;
1243 /* discover endpoint configuration */
1244 pThis->bEndCount = 1;
1245 pThis->wEndMask = 1;
1247 if (reg & MGC_M_CONFIGDATA_DYNFIFO) {
1249 status = ep_config_from_table(pThis);
1251 ERR("reconfigure software for Dynamic FIFOs\n");
1256 status = ep_config_from_hw(pThis);
1258 ERR("reconfigure software for static FIFOs\n");
1266 /* finish init, and print endpoint config */
1267 for (i = 0; i < pThis->bEndCount; i++) {
1268 struct musb_hw_ep *hw_ep = pThis->aLocalEnd + i;
1270 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + pBase;
1271 #ifdef CONFIG_USB_TUSB6010
1272 hw_ep->fifo_async = pThis->async + 0x400 + MUSB_FIFO_OFFSET(i);
1273 hw_ep->fifo_sync = pThis->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1275 hw_ep->conf = pBase - 0x400 + TUSB_EP0_CONF;
1277 hw_ep->conf = pBase + 0x400 + (((i - 1) & 0xf) << 2);
1280 hw_ep->regs = MGC_END_OFFSET(i, 0) + pBase;
1281 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1282 hw_ep->target_regs = MGC_BUSCTL_OFFSET(i, 0) + pBase;
1283 hw_ep->rx_reinit = 1;
1284 hw_ep->tx_reinit = 1;
1287 if (hw_ep->wMaxPacketSizeTx) {
1289 "%s: hw_ep %d%s, %smax %d\n",
1290 musb_driver_name, i,
1291 hw_ep->bIsSharedFifo ? "shared" : "tx",
1292 hw_ep->tx_double_buffered
1293 ? "doublebuffer, " : "",
1294 hw_ep->wMaxPacketSizeTx);
1296 if (hw_ep->wMaxPacketSizeRx && !hw_ep->bIsSharedFifo) {
1298 "%s: hw_ep %d%s, %smax %d\n",
1299 musb_driver_name, i,
1301 hw_ep->rx_double_buffered
1302 ? "doublebuffer, " : "",
1303 hw_ep->wMaxPacketSizeRx);
1305 if (!(hw_ep->wMaxPacketSizeTx || hw_ep->wMaxPacketSizeRx))
1306 DBG(1, "hw_ep %d not configured\n", i);
1312 /*-------------------------------------------------------------------------*/
1314 #ifdef CONFIG_ARCH_OMAP243X
1316 static irqreturn_t generic_interrupt(int irq, void *__hci)
1318 unsigned long flags;
1319 irqreturn_t retval = IRQ_NONE;
1320 struct musb *musb = __hci;
1322 spin_lock_irqsave(&musb->Lock, flags);
1324 musb->int_usb = musb_readb(musb->pRegs, MGC_O_HDRC_INTRUSB);
1325 musb->int_tx = musb_readw(musb->pRegs, MGC_O_HDRC_INTRTX);
1326 musb->int_rx = musb_readw(musb->pRegs, MGC_O_HDRC_INTRRX);
1328 if (musb->int_usb || musb->int_tx || musb->int_rx)
1329 retval = musb_interrupt(musb);
1331 spin_unlock_irqrestore(&musb->Lock, flags);
1333 /* REVISIT we sometimes get spurious IRQs on g_ep0
1336 if (retval != IRQ_HANDLED)
1337 DBG(5, "spurious?\n");
1343 #define generic_interrupt NULL
1347 * handle all the irqs defined by the HDRC core. for now we expect: other
1348 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1349 * will be assigned, and the irq will already have been acked.
1351 * called in irq context with spinlock held, irqs blocked
1353 irqreturn_t musb_interrupt(struct musb *musb)
1355 irqreturn_t retval = IRQ_NONE;
1360 devctl = musb_readb(musb->pRegs, MGC_O_HDRC_DEVCTL);
1361 power = musb_readb(musb->pRegs, MGC_O_HDRC_POWER);
1363 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
1364 (devctl & MGC_M_DEVCTL_HM) ? "host" : "peripheral",
1365 musb->int_usb, musb->int_tx, musb->int_rx);
1367 /* the core can interrupt us for multiple reasons; docs have
1368 * a generic interrupt flowchart to follow
1370 if (musb->int_usb & STAGE0_MASK)
1371 retval |= musb_stage0_irq(musb, musb->int_usb,
1374 /* "stage 1" is handling endpoint irqs */
1376 /* handle endpoint 0 first */
1377 if (musb->int_tx & 1) {
1378 if (devctl & MGC_M_DEVCTL_HM)
1379 retval |= musb_h_ep0_irq(musb);
1381 retval |= musb_g_ep0_irq(musb);
1384 /* RX on endpoints 1-15 */
1385 reg = musb->int_rx >> 1;
1389 // MGC_SelectEnd(musb->pRegs, ep_num);
1390 /* REVISIT just retval = ep->rx_irq(...) */
1391 retval = IRQ_HANDLED;
1392 if (devctl & MGC_M_DEVCTL_HM) {
1393 if (is_host_capable())
1394 musb_host_rx(musb, ep_num);
1396 if (is_peripheral_capable())
1397 musb_g_rx(musb, ep_num);
1405 /* TX on endpoints 1-15 */
1406 reg = musb->int_tx >> 1;
1410 // MGC_SelectEnd(musb->pRegs, ep_num);
1411 /* REVISIT just retval |= ep->tx_irq(...) */
1412 retval = IRQ_HANDLED;
1413 if (devctl & MGC_M_DEVCTL_HM) {
1414 if (is_host_capable())
1415 musb_host_tx(musb, ep_num);
1417 if (is_peripheral_capable())
1418 musb_g_tx(musb, ep_num);
1425 /* finish handling "global" interrupts after handling fifos */
1427 retval |= musb_stage2_irq(musb,
1428 musb->int_usb, devctl, power);
1434 #ifndef CONFIG_USB_INVENTRA_FIFO
1435 static int __initdata use_dma = 1;
1437 /* "modprobe ... use_dma=0" etc */
1438 module_param(use_dma, bool, 0);
1439 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1441 void musb_dma_completion(struct musb *musb, u8 bLocalEnd, u8 bTransmit)
1443 u8 devctl = musb_readb(musb->pRegs, MGC_O_HDRC_DEVCTL);
1445 /* called with controller lock already held */
1448 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1449 if (!is_cppi_enabled()) {
1451 if (devctl & MGC_M_DEVCTL_HM)
1452 musb_h_ep0_irq(musb);
1454 musb_g_ep0_irq(musb);
1458 /* endpoints 1..15 */
1460 if (devctl & MGC_M_DEVCTL_HM) {
1461 if (is_host_capable())
1462 musb_host_tx(musb, bLocalEnd);
1464 if (is_peripheral_capable())
1465 musb_g_tx(musb, bLocalEnd);
1469 if (devctl & MGC_M_DEVCTL_HM) {
1470 if (is_host_capable())
1471 musb_host_rx(musb, bLocalEnd);
1473 if (is_peripheral_capable())
1474 musb_g_rx(musb, bLocalEnd);
1484 /*-------------------------------------------------------------------------*/
1489 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1491 struct musb *musb = dev_to_musb(dev);
1492 unsigned long flags;
1495 spin_lock_irqsave(&musb->Lock, flags);
1496 switch (musb->board_mode) {
1498 ret = sprintf(buf, "host\n");
1500 case MUSB_PERIPHERAL:
1501 ret = sprintf(buf, "peripheral\n");
1504 ret = sprintf(buf, "otg\n");
1507 spin_unlock_irqrestore(&musb->Lock, flags);
1511 static DEVICE_ATTR(mode, S_IRUGO, musb_mode_show, NULL);
1514 musb_cable_show(struct device *dev, struct device_attribute *attr, char *buf)
1516 struct musb *musb = dev_to_musb(dev);
1517 char *v1= "", *v2 = "?";
1518 unsigned long flags;
1521 spin_lock_irqsave(&musb->Lock, flags);
1522 #if defined(CONFIG_USB_TUSB6010) && !defined(CONFIG_USB_MUSB_OTG)
1523 /* REVISIT: connect-A != connect-B ... */
1524 vbus = musb_platform_get_vbus_status(musb);
1528 v2 = "disconnected";
1530 /* NOTE: board-specific issues, like too-big capacitors keeping
1531 * VBUS high for a long time after power has been removed, can
1532 * cause temporary false indications of a connection.
1534 vbus = musb_readb(musb->pRegs, MGC_O_HDRC_DEVCTL);
1536 /* REVISIT retest on real OTG hardware */
1537 switch (musb->board_mode) {
1541 case MUSB_PERIPHERAL:
1546 v2 = (vbus & MGC_M_DEVCTL_BDEVICE) ? "B" : "A";
1549 } else /* VBUS level below A-Valid */
1550 v2 = "disconnected";
1552 musb_platform_try_idle(musb);
1553 spin_unlock_irqrestore(&musb->Lock, flags);
1555 return sprintf(buf, "%s%s\n", v1, v2);
1557 static DEVICE_ATTR(cable, S_IRUGO, musb_cable_show, NULL);
1561 /* Only used to provide cable state change events */
1562 static void musb_irq_work(struct work_struct *data)
1564 struct musb *musb = container_of(data, struct musb, irq_work);
1566 sysfs_notify(&musb->controller->kobj, NULL, "cable");
1569 /* --------------------------------------------------------------------------
1573 static struct musb *__init
1574 allocate_instance(struct device *dev, void __iomem *mbase)
1577 struct musb_hw_ep *ep;
1579 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1580 struct usb_hcd *hcd;
1582 hcd = usb_create_hcd(&musb_hc_driver, dev, dev->bus_id);
1585 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1587 musb = hcd_to_musb(hcd);
1588 INIT_LIST_HEAD(&musb->control);
1589 INIT_LIST_HEAD(&musb->in_bulk);
1590 INIT_LIST_HEAD(&musb->out_bulk);
1592 hcd->uses_new_polling = 1;
1594 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1596 musb = kzalloc(sizeof *musb, GFP_KERNEL);
1599 dev_set_drvdata(dev, musb);
1603 musb->pRegs = mbase;
1604 musb->ctrl_base = mbase;
1605 musb->nIrq = -ENODEV;
1606 for (epnum = 0, ep = musb->aLocalEnd;
1607 epnum < MUSB_C_NUM_EPS;
1611 ep->bLocalEnd = epnum;
1614 musb->controller = dev;
1618 static void musb_free(struct musb *musb)
1620 /* this has multiple entry modes. it handles fault cleanup after
1621 * probe(), where things may be partially set up, as well as rmmod
1622 * cleanup after everything's been de-activated.
1626 device_remove_file(musb->controller, &dev_attr_mode);
1627 device_remove_file(musb->controller, &dev_attr_cable);
1630 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1631 musb_gadget_cleanup(musb);
1634 if (musb->nIrq >= 0) {
1635 disable_irq_wake(musb->nIrq);
1636 free_irq(musb->nIrq, musb);
1638 if (is_dma_capable() && musb->pDmaController) {
1639 struct dma_controller *c = musb->pDmaController;
1641 (void) c->stop(c->pPrivateData);
1642 dma_controller_destroy(c);
1645 musb_writeb(musb->pRegs, MGC_O_HDRC_DEVCTL, 0);
1646 musb_platform_exit(musb);
1647 musb_writeb(musb->pRegs, MGC_O_HDRC_DEVCTL, 0);
1650 clk_disable(musb->clock);
1651 clk_put(musb->clock);
1654 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1655 usb_put_hcd(musb_to_hcd(musb));
1662 * Perform generic per-controller initialization.
1664 * @pDevice: the controller (already clocked, etc)
1666 * @pRegs: virtual address of controller registers,
1667 * not yet corrected for platform-specific offsets
1670 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1674 struct musb_hdrc_platform_data *plat = dev->platform_data;
1676 /* The driver might handle more features than the board; OK.
1677 * Fail when the board needs a feature that's not enabled.
1680 dev_dbg(dev, "no platform_data?\n");
1683 switch (plat->mode) {
1685 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1690 case MUSB_PERIPHERAL:
1691 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1697 #ifdef CONFIG_USB_MUSB_OTG
1703 dev_err(dev, "incompatible Kconfig role setting\n");
1708 pThis = allocate_instance(dev, ctrl);
1712 spin_lock_init(&pThis->Lock);
1713 pThis->board_mode = plat->mode;
1714 pThis->board_set_power = plat->set_power;
1715 pThis->min_power = plat->min_power;
1717 /* assume vbus is off */
1719 /* platform adjusts pThis->pRegs and pThis->isr if needed,
1720 * and activates clocks
1722 pThis->isr = generic_interrupt;
1723 status = musb_platform_init(pThis);
1732 #ifndef CONFIG_USB_INVENTRA_FIFO
1733 if (use_dma && dev->dma_mask) {
1734 struct dma_controller *c;
1736 c = dma_controller_create(pThis, pThis->pRegs);
1737 pThis->pDmaController = c;
1739 (void) c->start(c->pPrivateData);
1742 /* ideally this would be abstracted in platform setup */
1743 if (!is_dma_capable() || !pThis->pDmaController)
1744 dev->dma_mask = NULL;
1746 /* be sure interrupts are disabled before connecting ISR */
1747 musb_platform_disable(pThis);
1749 /* setup musb parts of the core (especially endpoints) */
1750 status = musb_core_init(plat->multipoint
1751 ? MUSB_CONTROLLER_MHDRC
1752 : MUSB_CONTROLLER_HDRC, pThis);
1756 /* attach to the IRQ */
1757 if (request_irq (nIrq, pThis->isr, 0, dev->bus_id, pThis)) {
1758 dev_err(dev, "request_irq %d failed!\n", nIrq);
1763 // FIXME this handles wakeup irqs wrong
1764 if (enable_irq_wake(nIrq) == 0)
1765 device_init_wakeup(dev, 1);
1767 pr_info("%s: USB %s mode controller at %p using %s, IRQ %d\n",
1770 switch (pThis->board_mode) {
1771 case MUSB_HOST: s = "Host"; break;
1772 case MUSB_PERIPHERAL: s = "Peripheral"; break;
1773 default: s = "OTG"; break;
1776 (is_dma_capable() && pThis->pDmaController)
1780 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1781 /* host side needs more setup, except for no-host modes */
1782 if (pThis->board_mode != MUSB_PERIPHERAL) {
1783 struct usb_hcd *hcd = musb_to_hcd(pThis);
1785 if (pThis->board_mode == MUSB_OTG)
1786 hcd->self.otg_port = 1;
1787 pThis->xceiv.host = &hcd->self;
1788 hcd->power_budget = 2 * (plat->power ? : 250);
1790 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
1792 /* For the host-only role, we can activate right away.
1793 * (We expect the ID pin to be forcibly grounded!!)
1794 * Otherwise, wait till the gadget driver hooks up.
1796 if (!is_otg_enabled(pThis) && is_host_enabled(pThis)) {
1797 MUSB_HST_MODE(pThis);
1798 pThis->xceiv.default_a = 1;
1799 pThis->xceiv.state = OTG_STATE_A_IDLE;
1801 status = usb_add_hcd(musb_to_hcd(pThis), -1, 0);
1803 DBG(1, "%s mode, status %d, devctl %02x %c\n",
1805 musb_readb(pThis->pRegs, MGC_O_HDRC_DEVCTL),
1806 (musb_readb(pThis->pRegs, MGC_O_HDRC_DEVCTL)
1807 & MGC_M_DEVCTL_BDEVICE
1810 } else /* peripheral is enabled */ {
1811 MUSB_DEV_MODE(pThis);
1812 pThis->xceiv.default_a = 0;
1813 pThis->xceiv.state = OTG_STATE_B_IDLE;
1815 status = musb_gadget_setup(pThis);
1817 DBG(1, "%s mode, status %d, dev%02x\n",
1818 is_otg_enabled(pThis) ? "OTG" : "PERIPHERAL",
1820 musb_readb(pThis->pRegs, MGC_O_HDRC_DEVCTL));
1825 musb_debug_create("driver/musb_hdrc", pThis);
1828 device_init_wakeup(dev, 0);
1833 INIT_WORK(&pThis->irq_work, musb_irq_work);
1836 status = device_create_file(dev, &dev_attr_mode);
1837 status = device_create_file(dev, &dev_attr_cable);
1844 musb_platform_exit(pThis);
1848 /*-------------------------------------------------------------------------*/
1850 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
1851 * bridge to a platform device; this driver then suffices.
1854 #ifndef CONFIG_USB_INVENTRA_FIFO
1855 static u64 *orig_dma_mask;
1858 static int __init musb_probe(struct platform_device *pdev)
1860 struct device *dev = &pdev->dev;
1861 int irq = platform_get_irq(pdev, 0);
1862 struct resource *iomem;
1865 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1866 if (!iomem || irq == 0)
1869 base = ioremap(iomem->start, iomem->end - iomem->start + 1);
1871 dev_err(dev, "ioremap failed\n");
1875 #ifndef CONFIG_USB_INVENTRA_FIFO
1876 /* clobbered by use_dma=n */
1877 orig_dma_mask = dev->dma_mask;
1879 return musb_init_controller(dev, irq, base);
1882 static int __devexit musb_remove(struct platform_device *pdev)
1884 struct musb *musb = dev_to_musb(&pdev->dev);
1885 void __iomem *ctrl_base = musb->ctrl_base;
1887 /* this gets called on rmmod.
1888 * - Host mode: host may still be active
1889 * - Peripheral mode: peripheral is deactivated (or never-activated)
1890 * - OTG mode: both roles are deactivated (or never-activated)
1892 musb_shutdown(pdev);
1893 musb_debug_delete("driver/musb_hdrc", musb);
1894 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1895 if (musb->board_mode == MUSB_HOST)
1896 usb_remove_hcd(musb_to_hcd(musb));
1900 device_init_wakeup(&pdev->dev, 0);
1901 #ifndef CONFIG_USB_INVENTRA_FIFO
1902 pdev->dev.dma_mask = orig_dma_mask;
1909 static int musb_suspend(struct platform_device *pdev, pm_message_t message)
1911 unsigned long flags;
1912 struct musb *musb = dev_to_musb(&pdev->dev);
1917 spin_lock_irqsave(&musb->Lock, flags);
1919 if (is_peripheral_active(musb)) {
1920 /* FIXME force disconnect unless we know USB will wake
1921 * the system up quickly enough to respond ...
1923 } else if (is_host_active(musb)) {
1924 /* we know all the children are suspended; sometimes
1925 * they will even be wakeup-enabled.
1929 clk_disable(musb->clock);
1930 spin_unlock_irqrestore(&musb->Lock, flags);
1934 static int musb_resume(struct platform_device *pdev)
1936 unsigned long flags;
1937 struct musb *musb = dev_to_musb(&pdev->dev);
1942 spin_lock_irqsave(&musb->Lock, flags);
1943 clk_enable(musb->clock);
1944 /* for static cmos like DaVinci, register values were preserved
1945 * unless for some reason the whole soc powered down and we're
1946 * not treating that as a whole-system restart (e.g. swsusp)
1948 spin_unlock_irqrestore(&musb->Lock, flags);
1953 #define musb_suspend NULL
1954 #define musb_resume NULL
1957 static struct platform_driver musb_driver = {
1959 .name = (char *)musb_driver_name,
1960 .bus = &platform_bus_type,
1961 .owner = THIS_MODULE,
1963 .remove = __devexit_p(musb_remove),
1964 .shutdown = musb_shutdown,
1965 .suspend = musb_suspend,
1966 .resume = musb_resume,
1969 /*-------------------------------------------------------------------------*/
1971 static int __init musb_init(void)
1973 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1978 pr_info("%s: version " MUSB_VERSION ", "
1979 #ifdef CONFIG_USB_INVENTRA_FIFO
1981 #elif defined(CONFIG_USB_TI_CPPI_DMA)
1983 #elif defined(CONFIG_USB_INVENTRA_DMA)
1985 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
1991 #ifdef CONFIG_USB_MUSB_OTG
1992 "otg (peripheral+host)"
1993 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
1995 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
1999 musb_driver_name, debug);
2000 return platform_driver_probe(&musb_driver, musb_probe);
2003 /* make us init after usbcore and before usb
2004 * gadget and host-side drivers start to register
2006 subsys_initcall(musb_init);
2008 static void __exit musb_cleanup(void)
2010 platform_driver_unregister(&musb_driver);
2012 module_exit(musb_cleanup);