1 /*****************************************************************
2 * Copyright 2005 Mentor Graphics Corporation
3 * Copyright (C) 2005-2006 by Texas Instruments
4 * Copyright (C) 2006 by Nokia Corporation
6 * This file is part of the Inventra Controller Driver for Linux.
8 * The Inventra Controller Driver for Linux is free software; you
9 * can redistribute it and/or modify it under the terms of the GNU
10 * General Public License version 2 as published by the Free Software
13 * The Inventra Controller Driver for Linux is distributed in
14 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
15 * without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 * License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with The Inventra Controller Driver for Linux ; if not,
21 * write to the Free Software Foundation, Inc., 59 Temple Place,
22 * Suite 330, Boston, MA 02111-1307 USA
24 * ANY DOWNLOAD, USE, REPRODUCTION, MODIFICATION OR DISTRIBUTION
25 * OF THIS DRIVER INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE
26 * OF THOSE TERMS.THIS DRIVER IS PROVIDED "AS IS" AND MENTOR GRAPHICS
27 * MAKES NO WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THIS DRIVER.
28 * MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES
29 * OF MERCHANTABILITY; FITNESS FOR A PARTICULAR PURPOSE AND
30 * NON-INFRINGEMENT. MENTOR GRAPHICS DOES NOT PROVIDE SUPPORT
31 * SERVICES OR UPDATES FOR THIS DRIVER, EVEN IF YOU ARE A MENTOR
32 * GRAPHICS SUPPORT CUSTOMER.
33 ******************************************************************/
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - <asm/arch/hdrc_cnf.h> for SOC or family details
86 * - platform_device for addressing, irq, and platform_data
87 * - platform_data is mostly for board-specific informarion
89 * Most of the conditional compilation will (someday) vanish.
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/platform_device.h>
104 #include <asm/arch/hardware.h>
105 #include <asm/arch/memory.h>
106 #include <asm/mach-types.h>
109 #include "musbdefs.h"
112 #ifdef CONFIG_ARCH_DAVINCI
119 unsigned debug = MUSB_DEBUG;
120 module_param(debug, uint, 0);
121 MODULE_PARM_DESC(debug, "initial debug message level");
123 #define MUSB_VERSION_SUFFIX "/dbg"
126 const char *otg_state_string(struct musb *musb)
130 snprintf(buf, sizeof buf, "otg-%d", musb->xceiv.state);
135 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
136 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
138 #define MUSB_VERSION_BASE "2.2a/db-0.5.2"
140 #ifndef MUSB_VERSION_SUFFIX
141 #define MUSB_VERSION_SUFFIX ""
143 #define MUSB_VERSION MUSB_VERSION_BASE MUSB_VERSION_SUFFIX
145 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
147 const char musb_driver_name[] = "musb_hdrc";
149 MODULE_DESCRIPTION(DRIVER_INFO);
150 MODULE_AUTHOR(DRIVER_AUTHOR);
151 MODULE_LICENSE("GPL");
154 /*-------------------------------------------------------------------------*/
156 static inline struct musb *dev_to_musb(struct device *dev)
158 #ifdef CONFIG_USB_MUSB_HDRC_HCD
159 /* usbcore insists dev->driver_data is a "struct hcd *" */
160 return hcd_to_musb(dev_get_drvdata(dev));
162 return dev_get_drvdata(dev);
166 /*-------------------------------------------------------------------------*/
168 #ifndef CONFIG_USB_TUSB6010
170 * Load an endpoint's FIFO
172 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
174 void __iomem *fifo = hw_ep->fifo;
178 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
179 'T', hw_ep->epnum, fifo, len, src);
181 /* we can't assume unaligned reads work */
182 if (likely((0x01 & (unsigned long) src) == 0)) {
185 /* best case is 32bit-aligned source address */
186 if ((0x02 & (unsigned long) src) == 0) {
188 writesl(fifo, src + index, len >> 2);
189 index += len & ~0x03;
192 musb_writew(fifo, 0, *(u16*)&src[index]);
197 writesw(fifo, src + index, len >> 1);
198 index += len & ~0x01;
202 musb_writeb(fifo, 0, src[index]);
205 writesb(fifo, src, len);
210 * Unload an endpoint's FIFO
212 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
214 void __iomem *fifo = hw_ep->fifo;
216 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
217 'R', hw_ep->epnum, fifo, len, dst);
219 /* we can't assume unaligned writes work */
220 if (likely((0x01 & (unsigned long) dst) == 0)) {
223 /* best case is 32bit-aligned destination address */
224 if ((0x02 & (unsigned long) dst) == 0) {
226 readsl(fifo, dst, len >> 2);
230 *(u16*)&dst[index] = musb_readw(fifo, 0);
235 readsw(fifo, dst, len >> 1);
240 dst[index] = musb_readb(fifo, 0);
243 readsb(fifo, dst, len);
247 #endif /* normal PIO */
250 /*-------------------------------------------------------------------------*/
252 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
253 static const u8 musb_test_packet[53] = {
254 /* implicit SYNC then DATA0 to start */
257 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
259 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
261 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
262 /* JJJJJJJKKKKKKK x8 */
263 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
265 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
266 /* JKKKKKKK x10, JK */
267 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
269 /* implicit CRC16 then EOP to end */
272 void musb_load_testpacket(struct musb *musb)
274 void __iomem *regs = musb->endpoints[0].regs;
276 MGC_SelectEnd(musb->mregs, 0);
277 musb_write_fifo(musb->control_ep,
278 sizeof(musb_test_packet), musb_test_packet);
279 musb_writew(regs, MGC_O_HDRC_CSR0, MGC_M_CSR0_TXPKTRDY);
282 /*-------------------------------------------------------------------------*/
284 #ifdef CONFIG_USB_MUSB_OTG
287 * See also USB_OTG_1-3.pdf 6.6.5 Timers
288 * REVISIT: Are the other timers done in the hardware?
290 #define TB_ASE0_BRST 100 /* Min 3.125 ms */
293 * Handles OTG hnp timeouts, such as b_ase0_brst
295 void musb_otg_timer_func(unsigned long data)
297 struct musb *musb = (struct musb *)data;
300 spin_lock_irqsave(&musb->Lock, flags);
301 if (musb->xceiv.state == OTG_STATE_B_WAIT_ACON) {
302 DBG(1, "HNP: B_WAIT_ACON timeout, going back to B_PERIPHERAL\n");
303 musb_g_disconnect(musb);
304 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
307 spin_unlock_irqrestore(&musb->Lock, flags);
310 static DEFINE_TIMER(musb_otg_timer, musb_otg_timer_func, 0, 0);
313 * Stops the B-device HNP state. Caller must take care of locking.
315 void musb_hnp_stop(struct musb *musb)
317 struct usb_hcd *hcd = musb_to_hcd(musb);
318 void __iomem *mbase = musb->mregs;
321 switch (musb->xceiv.state) {
322 case OTG_STATE_A_PERIPHERAL:
323 case OTG_STATE_A_WAIT_VFALL:
324 DBG(1, "HNP: Switching back to A-host\n");
325 musb_g_disconnect(musb);
326 musb_root_disconnect(musb);
327 musb->xceiv.state = OTG_STATE_A_IDLE;
330 case OTG_STATE_B_HOST:
331 DBG(1, "HNP: Disabling HR\n");
332 hcd->self.is_b_host = 0;
333 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
334 reg = musb_readb(mbase, MGC_O_HDRC_POWER);
335 reg |= MGC_M_POWER_SUSPENDM;
336 musb_writeb(mbase, MGC_O_HDRC_POWER, reg);
337 /* REVISIT: Start SESSION_REQUEST here? */
340 DBG(1, "HNP: Stopping in unknown state %s\n",
341 otg_state_string(musb));
348 * Interrupt Service Routine to record USB "global" interrupts.
349 * Since these do not happen often and signify things of
350 * paramount importance, it seems OK to check them individually;
351 * the order of the tests is specified in the manual
353 * @param musb instance pointer
354 * @param bIntrUSB register contents
359 #define STAGE0_MASK (MGC_M_INTR_RESUME | MGC_M_INTR_SESSREQ \
360 | MGC_M_INTR_VBUSERROR | MGC_M_INTR_CONNECT \
363 static irqreturn_t musb_stage0_irq(struct musb * musb, u8 bIntrUSB,
366 irqreturn_t handled = IRQ_NONE;
367 #ifdef CONFIG_USB_MUSB_HDRC_HCD
368 void __iomem *mbase = musb->mregs;
371 DBG(3, "<== Power=%02x, DevCtl=%02x, bIntrUSB=0x%x\n", power, devctl,
374 /* in host mode, the peripheral may issue remote wakeup.
375 * in peripheral mode, the host may resume the link.
376 * spurious RESUME irqs happen too, paired with SUSPEND.
378 if (bIntrUSB & MGC_M_INTR_RESUME) {
379 handled = IRQ_HANDLED;
380 DBG(3, "RESUME (%s)\n", otg_state_string(musb));
382 if (devctl & MGC_M_DEVCTL_HM) {
383 #ifdef CONFIG_USB_MUSB_HDRC_HCD
384 switch (musb->xceiv.state) {
385 case OTG_STATE_A_SUSPEND:
386 /* remote wakeup? later, GetPortStatus
387 * will stop RESUME signaling
390 if (power & MGC_M_POWER_SUSPENDM) {
392 musb->int_usb &= ~MGC_M_INTR_SUSPEND;
393 DBG(2, "Spurious SUSPENDM\n");
397 power &= ~MGC_M_POWER_SUSPENDM;
398 musb_writeb(mbase, MGC_O_HDRC_POWER,
399 power | MGC_M_POWER_RESUME);
401 musb->port1_status |=
402 (USB_PORT_STAT_C_SUSPEND << 16)
403 | MUSB_PORT_STAT_RESUME;
404 musb->rh_timer = jiffies
405 + msecs_to_jiffies(20);
407 musb->xceiv.state = OTG_STATE_A_HOST;
409 usb_hcd_resume_root_hub(musb_to_hcd(musb));
411 case OTG_STATE_B_WAIT_ACON:
412 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
417 WARN("bogus %s RESUME (%s)\n",
419 otg_state_string(musb));
423 switch (musb->xceiv.state) {
424 #ifdef CONFIG_USB_MUSB_HDRC_HCD
425 case OTG_STATE_A_SUSPEND:
426 /* possibly DISCONNECT is upcoming */
427 musb->xceiv.state = OTG_STATE_A_HOST;
428 usb_hcd_resume_root_hub(musb_to_hcd(musb));
431 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
432 case OTG_STATE_B_WAIT_ACON:
433 case OTG_STATE_B_PERIPHERAL:
434 /* disconnect while suspended? we may
435 * not get a disconnect irq...
437 if ((devctl & MGC_M_DEVCTL_VBUS)
438 != (3 << MGC_S_DEVCTL_VBUS)) {
439 musb->int_usb |= MGC_M_INTR_DISCONNECT;
440 musb->int_usb &= ~MGC_M_INTR_SUSPEND;
445 case OTG_STATE_B_IDLE:
446 musb->int_usb &= ~MGC_M_INTR_SUSPEND;
450 WARN("bogus %s RESUME (%s)\n",
452 otg_state_string(musb));
457 #ifdef CONFIG_USB_MUSB_HDRC_HCD
458 /* see manual for the order of the tests */
459 if (bIntrUSB & MGC_M_INTR_SESSREQ) {
460 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb));
462 /* IRQ arrives from ID pin sense or (later, if VBUS power
463 * is removed) SRP. responses are time critical:
464 * - turn on VBUS (with silicon-specific mechanism)
465 * - go through A_WAIT_VRISE
466 * - ... to A_WAIT_BCON.
467 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
469 musb_writeb(mbase, MGC_O_HDRC_DEVCTL, MGC_M_DEVCTL_SESSION);
470 musb->bEnd0Stage = MGC_END0_START;
471 musb->xceiv.state = OTG_STATE_A_IDLE;
473 musb_set_vbus(musb, 1);
475 handled = IRQ_HANDLED;
478 if (bIntrUSB & MGC_M_INTR_VBUSERROR) {
481 /* During connection as an A-Device, we may see a short
482 * current spikes causing voltage drop, because of cable
483 * and peripheral capacitance combined with vbus draw.
484 * (So: less common with truly self-powered devices, where
485 * vbus doesn't act like a power supply.)
487 * Such spikes are short; usually less than ~500 usec, max
488 * of ~2 msec. That is, they're not sustained overcurrent
489 * errors, though they're reported using VBUSERROR irqs.
491 * Workarounds: (a) hardware: use self powered devices.
492 * (b) software: ignore non-repeated VBUS errors.
494 * REVISIT: do delays from lots of DEBUG_KERNEL checks
495 * make trouble here, keeping VBUS < 4.4V ?
497 switch (musb->xceiv.state) {
498 case OTG_STATE_A_HOST:
499 /* recovery is dicey once we've gotten past the
500 * initial stages of enumeration, but if VBUS
501 * stayed ok at the other end of the link, and
502 * another reset is due (at least for high speed,
503 * to redo the chirp etc), it might work OK...
505 case OTG_STATE_A_WAIT_BCON:
506 case OTG_STATE_A_WAIT_VRISE:
507 if (musb->vbuserr_retry) {
508 musb->vbuserr_retry--;
510 devctl |= MGC_M_DEVCTL_SESSION;
511 musb_writeb(mbase, MGC_O_HDRC_DEVCTL, devctl);
513 musb->port1_status |=
514 (1 << USB_PORT_FEAT_OVER_CURRENT)
515 | (1 << USB_PORT_FEAT_C_OVER_CURRENT);
522 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
523 otg_state_string(musb),
526 switch (devctl & MGC_M_DEVCTL_VBUS) {
527 case 0 << MGC_S_DEVCTL_VBUS:
528 s = "<SessEnd"; break;
529 case 1 << MGC_S_DEVCTL_VBUS:
530 s = "<AValid"; break;
531 case 2 << MGC_S_DEVCTL_VBUS:
532 s = "<VBusValid"; break;
533 //case 3 << MGC_S_DEVCTL_VBUS:
537 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
540 /* go through A_WAIT_VFALL then start a new session */
542 musb_set_vbus(musb, 0);
543 handled = IRQ_HANDLED;
546 if (bIntrUSB & MGC_M_INTR_CONNECT) {
547 struct usb_hcd *hcd = musb_to_hcd(musb);
549 handled = IRQ_HANDLED;
551 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
553 musb->bEnd0Stage = MGC_END0_START;
555 #ifdef CONFIG_USB_MUSB_OTG
556 /* flush endpoints when transitioning from Device Mode */
557 if (is_peripheral_active(musb)) {
558 // REVISIT HNP; just force disconnect
560 musb->bDelayPortPowerOff = FALSE;
561 musb_writew(mbase, MGC_O_HDRC_INTRTXE, musb->wEndMask);
562 musb_writew(mbase, MGC_O_HDRC_INTRRXE, musb->wEndMask & 0xfffe);
563 musb_writeb(mbase, MGC_O_HDRC_INTRUSBE, 0xf7);
565 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
566 |USB_PORT_STAT_HIGH_SPEED
567 |USB_PORT_STAT_ENABLE
569 musb->port1_status |= USB_PORT_STAT_CONNECTION
570 |(USB_PORT_STAT_C_CONNECTION << 16);
572 /* high vs full speed is just a guess until after reset */
573 if (devctl & MGC_M_DEVCTL_LSDEV)
574 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
577 usb_hcd_poll_rh_status(hcd);
579 usb_hcd_resume_root_hub(hcd);
583 /* indicate new connection to OTG machine */
584 switch (musb->xceiv.state) {
585 case OTG_STATE_B_WAIT_ACON:
586 DBG(1, "HNP: Waiting to switch to b_host state\n");
587 musb->xceiv.state = OTG_STATE_B_HOST;
588 hcd->self.is_b_host = 1;
591 if ((devctl & MGC_M_DEVCTL_VBUS)
592 == (3 << MGC_S_DEVCTL_VBUS)) {
593 musb->xceiv.state = OTG_STATE_A_HOST;
594 hcd->self.is_b_host = 0;
598 DBG(1, "CONNECT (%s) devctl %02x\n",
599 otg_state_string(musb), devctl);
601 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
603 /* mentor saves a bit: bus reset and babble share the same irq.
604 * only host sees babble; only peripheral sees bus reset.
606 if (bIntrUSB & MGC_M_INTR_RESET) {
607 if (devctl & MGC_M_DEVCTL_HM) {
609 * Looks like non-HS BABBLE can be ignored, but
610 * HS BABBLE is an error condition. For HS the solution
611 * is to avoid babble in the first place and fix whatever
612 * causes BABBLE. When HS BABBLE happens we can only stop
615 if (devctl & (MGC_M_DEVCTL_FSDEV | MGC_M_DEVCTL_LSDEV))
616 DBG(1, "BABBLE devctl: %02x\n", devctl);
618 ERR("Stopping host session because of babble\n");
619 musb_writeb(mbase, MGC_O_HDRC_DEVCTL, 0);
622 DBG(1, "BUS RESET\n");
625 schedule_work(&musb->irq_work);
628 handled = IRQ_HANDLED;
635 * Interrupt Service Routine to record USB "global" interrupts.
636 * Since these do not happen often and signify things of
637 * paramount importance, it seems OK to check them individually;
638 * the order of the tests is specified in the manual
640 * @param musb instance pointer
641 * @param bIntrUSB register contents
645 static irqreturn_t musb_stage2_irq(struct musb * musb, u8 bIntrUSB,
648 irqreturn_t handled = IRQ_NONE;
651 /* REVISIT ... this would be for multiplexing periodic endpoints, or
652 * supporting transfer phasing to prevent exceeding ISO bandwidth
653 * limits of a given frame or microframe.
655 * It's not needed for peripheral side, which dedicates endpoints;
656 * though it _might_ use SOF irqs for other purposes.
658 * And it's not currently needed for host side, which also dedicates
659 * endpoints, relies on TX/RX interval registers, and isn't claimed
660 * to support ISO transfers yet.
662 if (bIntrUSB & MGC_M_INTR_SOF) {
663 void __iomem *mbase = musb->mregs;
664 struct musb_hw_ep *ep;
668 DBG(6, "START_OF_FRAME\n");
669 handled = IRQ_HANDLED;
671 /* start any periodic Tx transfers waiting for current frame */
672 wFrame = musb_readw(mbase, MGC_O_HDRC_FRAME);
673 ep = musb->endpoints;
674 for (bEnd = 1; (bEnd < musb->nr_endpoints)
675 && (musb->wEndMask >= (1 << bEnd));
677 // FIXME handle framecounter wraps (12 bits)
678 // eliminate duplicated StartUrb logic
679 if (ep->dwWaitFrame >= wFrame) {
681 printk("SOF --> periodic TX%s on %d\n",
682 ep->tx_channel ? " DMA" : "",
685 musb_h_tx_start(musb, bEnd);
687 cppi_hostdma_start(musb, bEnd);
689 } /* end of for loop */
693 if ((bIntrUSB & MGC_M_INTR_DISCONNECT) && !musb->bIgnoreDisconnect) {
694 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
695 otg_state_string(musb),
696 MUSB_MODE(musb), devctl);
697 handled = IRQ_HANDLED;
699 switch (musb->xceiv.state) {
700 #ifdef CONFIG_USB_MUSB_HDRC_HCD
701 case OTG_STATE_A_HOST:
702 case OTG_STATE_A_SUSPEND:
703 musb_root_disconnect(musb);
704 if (musb->a_wait_bcon != 0)
705 musb_platform_try_idle(musb, jiffies
706 + msecs_to_jiffies(musb->a_wait_bcon));
709 #ifdef CONFIG_USB_MUSB_OTG
710 case OTG_STATE_B_HOST:
714 case OTG_STATE_A_PERIPHERAL:
715 musb_root_disconnect(musb);
717 case OTG_STATE_B_WAIT_ACON:
719 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
720 case OTG_STATE_B_PERIPHERAL:
721 musb_g_disconnect(musb);
725 WARN("unhandled DISCONNECT transition (%s)\n",
726 otg_state_string(musb));
730 schedule_work(&musb->irq_work);
733 if (bIntrUSB & MGC_M_INTR_SUSPEND) {
734 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
735 otg_state_string(musb), devctl, power);
736 handled = IRQ_HANDLED;
738 switch (musb->xceiv.state) {
739 case OTG_STATE_A_PERIPHERAL:
742 case OTG_STATE_B_PERIPHERAL:
743 musb_g_suspend(musb);
744 musb->is_active = is_otg_enabled(musb)
745 && musb->xceiv.gadget->b_hnp_enable;
746 if (musb->is_active) {
747 musb->xceiv.state = OTG_STATE_B_WAIT_ACON;
748 #ifdef CONFIG_USB_MUSB_OTG
749 DBG(1, "HNP: Setting timer for b_ase0_brst\n");
750 musb_otg_timer.data = (unsigned long)musb;
751 mod_timer(&musb_otg_timer, jiffies
752 + msecs_to_jiffies(TB_ASE0_BRST));
756 case OTG_STATE_A_WAIT_BCON:
757 if (musb->a_wait_bcon != 0)
758 musb_platform_try_idle(musb, jiffies
759 + msecs_to_jiffies(musb->a_wait_bcon));
761 case OTG_STATE_A_HOST:
762 musb->xceiv.state = OTG_STATE_A_SUSPEND;
763 musb->is_active = is_otg_enabled(musb)
764 && musb->xceiv.host->b_hnp_enable;
766 case OTG_STATE_B_HOST:
767 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
768 DBG(1, "REVISIT: SUSPEND as B_HOST\n");
771 /* "should not happen" */
781 /*-------------------------------------------------------------------------*/
784 * Program the HDRC to start (enable interrupts, dma, etc.).
786 void musb_start(struct musb *musb)
788 void __iomem *regs = musb->mregs;
789 u8 devctl = musb_readb(regs, MGC_O_HDRC_DEVCTL);
791 DBG(2, "<== devctl %02x\n", devctl);
793 /* Set INT enable registers, enable interrupts */
794 musb_writew(regs, MGC_O_HDRC_INTRTXE, musb->wEndMask);
795 musb_writew(regs, MGC_O_HDRC_INTRRXE, musb->wEndMask & 0xfffe);
796 musb_writeb(regs, MGC_O_HDRC_INTRUSBE, 0xf7);
798 musb_writeb(regs, MGC_O_HDRC_TESTMODE, 0);
800 /* put into basic highspeed mode and start session */
801 musb_writeb(regs, MGC_O_HDRC_POWER, MGC_M_POWER_ISOUPDATE
802 | MGC_M_POWER_SOFTCONN
804 /* ENSUSPEND wedges tusb */
805 // | MGC_M_POWER_ENSUSPEND
809 devctl = musb_readb(regs, MGC_O_HDRC_DEVCTL);
810 devctl &= ~MGC_M_DEVCTL_SESSION;
812 if (is_otg_enabled(musb)) {
813 /* session started after:
814 * (a) ID-grounded irq, host mode;
815 * (b) vbus present/connect IRQ, peripheral mode;
816 * (c) peripheral initiates, using SRP
818 if ((devctl & MGC_M_DEVCTL_VBUS) == MGC_M_DEVCTL_VBUS)
821 devctl |= MGC_M_DEVCTL_SESSION;
823 } else if (is_host_enabled(musb)) {
824 /* assume ID pin is hard-wired to ground */
825 devctl |= MGC_M_DEVCTL_SESSION;
827 } else /* peripheral is enabled */ {
828 if ((devctl & MGC_M_DEVCTL_VBUS) == MGC_M_DEVCTL_VBUS)
831 musb_platform_enable(musb);
832 musb_writeb(regs, MGC_O_HDRC_DEVCTL, devctl);
836 static void musb_generic_disable(struct musb *musb)
838 void __iomem *mbase = musb->mregs;
841 /* disable interrupts */
842 musb_writeb(mbase, MGC_O_HDRC_INTRUSBE, 0);
843 musb_writew(mbase, MGC_O_HDRC_INTRTXE, 0);
844 musb_writew(mbase, MGC_O_HDRC_INTRRXE, 0);
847 musb_writeb(mbase, MGC_O_HDRC_DEVCTL, 0);
849 /* flush pending interrupts */
850 temp = musb_readb(mbase, MGC_O_HDRC_INTRUSB);
851 temp = musb_readw(mbase, MGC_O_HDRC_INTRTX);
852 temp = musb_readw(mbase, MGC_O_HDRC_INTRRX);
857 * Make the HDRC stop (disable interrupts, etc.);
858 * reversible by musb_start
859 * called on gadget driver unregister
860 * with controller locked, irqs blocked
861 * acts as a NOP unless some role activated the hardware
863 void musb_stop(struct musb *musb)
865 /* stop IRQs, timers, ... */
866 musb_platform_disable(musb);
867 musb_generic_disable(musb);
868 DBG(3, "HDRC disabled\n");
871 * - mark host and/or peripheral drivers unusable/inactive
872 * - disable DMA (and enable it in HdrcStart)
873 * - make sure we can musb_start() after musb_stop(); with
874 * OTG mode, gadget driver module rmmod/modprobe cycles that
877 musb_platform_try_idle(musb, 0);
880 static void musb_shutdown(struct platform_device *pdev)
882 struct musb *musb = dev_to_musb(&pdev->dev);
885 spin_lock_irqsave(&musb->Lock, flags);
886 musb_platform_disable(musb);
887 musb_generic_disable(musb);
889 clk_put(musb->clock);
892 spin_unlock_irqrestore(&musb->Lock, flags);
894 /* FIXME power down */
898 /*-------------------------------------------------------------------------*/
901 * The silicon either has hard-wired endpoint configurations, or else
902 * "dynamic fifo" sizing. The driver has support for both, though at this
903 * writing only the dynamic sizing is very well tested. We use normal
904 * idioms to so both modes are compile-tested, but dead code elimination
905 * leaves only the relevant one in the object file.
907 * We don't currently use dynamic fifo setup capability to do anything
908 * more than selecting one of a bunch of predefined configurations.
910 #ifdef MUSB_C_DYNFIFO_DEF
911 #define can_dynfifo() 1
913 #define can_dynfifo() 0
916 #ifdef CONFIG_USB_TUSB6010
917 static ushort __initdata fifo_mode = 4;
919 static ushort __initdata fifo_mode = 2;
922 /* "modprobe ... fifo_mode=1" etc */
923 module_param(fifo_mode, ushort, 0);
924 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
927 #define DYN_FIFO_SIZE (1<<(MUSB_C_RAM_BITS+2))
929 enum fifo_style { FIFO_RXTX, FIFO_TX, FIFO_RX } __attribute__ ((packed));
930 enum buf_mode { BUF_SINGLE, BUF_DOUBLE } __attribute__ ((packed));
934 enum fifo_style style;
940 * tables defining fifo_mode values. define more if you like.
941 * for host side, make sure both halves of ep1 are set up.
944 /* mode 0 - fits in 2KB */
945 static struct fifo_cfg __initdata mode_0_cfg[] = {
946 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
947 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
948 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
949 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
950 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
953 /* mode 1 - fits in 4KB */
954 static struct fifo_cfg __initdata mode_1_cfg[] = {
955 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
956 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
957 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
958 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
959 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
962 /* mode 2 - fits in 4KB */
963 static struct fifo_cfg __initdata mode_2_cfg[] = {
964 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
965 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
966 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
967 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
968 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
969 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
972 /* mode 3 - fits in 4KB */
973 static struct fifo_cfg __initdata mode_3_cfg[] = {
974 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
975 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
976 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
977 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
978 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
979 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
982 /* mode 4 - fits in 16KB */
983 static struct fifo_cfg __initdata mode_4_cfg[] = {
984 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
985 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
986 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
987 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
988 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
989 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
990 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
991 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
992 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
993 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
994 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
995 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
996 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
997 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
998 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
999 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1000 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1001 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1002 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 512, },
1003 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 512, },
1004 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 512, },
1005 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 512, },
1006 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 512, },
1007 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 512, },
1008 { .hw_ep_num = 13, .style = FIFO_TX, .maxpacket = 512, },
1009 { .hw_ep_num = 13, .style = FIFO_RX, .maxpacket = 512, },
1010 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1011 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1016 * configure a fifo; for non-shared endpoints, this may be called
1017 * once for a tx fifo and once for an rx fifo.
1019 * returns negative errno or offset for next fifo.
1022 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1023 const struct fifo_cfg *cfg, u16 offset)
1025 void __iomem *mbase = musb->mregs;
1027 u16 maxpacket = cfg->maxpacket;
1028 u16 c_off = offset >> 3;
1031 /* expect hw_ep has already been zero-initialized */
1033 size = ffs(max(maxpacket, (u16) 8)) - 1;
1034 maxpacket = 1 << size;
1037 if (cfg->mode == BUF_DOUBLE) {
1038 if ((offset + (maxpacket << 1)) > DYN_FIFO_SIZE)
1040 c_size |= MGC_M_FIFOSZ_DPB;
1042 if ((offset + maxpacket) > DYN_FIFO_SIZE)
1046 /* configure the FIFO */
1047 musb_writeb(mbase, MGC_O_HDRC_INDEX, hw_ep->epnum);
1049 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1050 /* EP0 reserved endpoint for control, bidirectional;
1051 * EP1 reserved for bulk, two unidirection halves.
1053 if (hw_ep->epnum == 1)
1054 musb->bulk_ep = hw_ep;
1055 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1057 switch (cfg->style) {
1059 musb_writeb(mbase, MGC_O_HDRC_TXFIFOSZ, c_size);
1060 musb_writew(mbase, MGC_O_HDRC_TXFIFOADD, c_off);
1061 hw_ep->tx_double_buffered = !!(c_size & MGC_M_FIFOSZ_DPB);
1062 hw_ep->wMaxPacketSizeTx = maxpacket;
1065 musb_writeb(mbase, MGC_O_HDRC_RXFIFOSZ, c_size);
1066 musb_writew(mbase, MGC_O_HDRC_RXFIFOADD, c_off);
1067 hw_ep->rx_double_buffered = !!(c_size & MGC_M_FIFOSZ_DPB);
1068 hw_ep->wMaxPacketSizeRx = maxpacket;
1071 musb_writeb(mbase, MGC_O_HDRC_TXFIFOSZ, c_size);
1072 musb_writew(mbase, MGC_O_HDRC_TXFIFOADD, c_off);
1073 hw_ep->rx_double_buffered = !!(c_size & MGC_M_FIFOSZ_DPB);
1074 hw_ep->wMaxPacketSizeRx = maxpacket;
1076 musb_writeb(mbase, MGC_O_HDRC_RXFIFOSZ, c_size);
1077 musb_writew(mbase, MGC_O_HDRC_RXFIFOADD, c_off);
1078 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1079 hw_ep->wMaxPacketSizeTx = maxpacket;
1081 hw_ep->bIsSharedFifo = TRUE;
1085 /* NOTE rx and tx endpoint irqs aren't managed separately,
1086 * which happens to be ok
1088 musb->wEndMask |= (1 << hw_ep->epnum);
1090 return offset + (maxpacket << ((c_size & MGC_M_FIFOSZ_DPB) ? 1 : 0));
1093 static struct fifo_cfg __initdata ep0_cfg = {
1094 .style = FIFO_RXTX, .maxpacket = 64,
1097 static int __init ep_config_from_table(struct musb *musb)
1099 const struct fifo_cfg *cfg;
1102 struct musb_hw_ep *hw_ep = musb->endpoints;
1104 switch (fifo_mode) {
1110 n = ARRAY_SIZE(mode_0_cfg);
1114 n = ARRAY_SIZE(mode_1_cfg);
1118 n = ARRAY_SIZE(mode_2_cfg);
1122 n = ARRAY_SIZE(mode_3_cfg);
1126 n = ARRAY_SIZE(mode_4_cfg);
1130 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1131 musb_driver_name, fifo_mode);
1134 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1135 // assert(offset > 0)
1137 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1138 * be better than static MUSB_C_NUM_EPS and DYN_FIFO_SIZE...
1141 for (i = 0; i < n; i++) {
1142 u8 epn = cfg->hw_ep_num;
1144 if (epn >= MUSB_C_NUM_EPS) {
1145 pr_debug( "%s: invalid ep %d\n",
1146 musb_driver_name, epn);
1149 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1151 pr_debug( "%s: mem overrun, ep %d\n",
1152 musb_driver_name, epn);
1156 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1159 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1161 n + 1, MUSB_C_NUM_EPS * 2 - 1,
1162 offset, DYN_FIFO_SIZE);
1164 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1165 if (!musb->bulk_ep) {
1166 pr_debug( "%s: missing bulk\n", musb_driver_name);
1176 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1177 * @param musb the controller
1179 static int __init ep_config_from_hw(struct musb *musb)
1182 struct musb_hw_ep *hw_ep;
1183 void *mbase = musb->mregs;
1185 DBG(2, "<== static silicon ep config\n");
1187 /* FIXME pick up ep0 maxpacket size */
1189 for (bEnd = 1; bEnd < MUSB_C_NUM_EPS; bEnd++) {
1190 MGC_SelectEnd(mbase, bEnd);
1191 hw_ep = musb->endpoints + bEnd;
1193 /* read from core using indexed model */
1194 reg = musb_readb(hw_ep->regs, 0x10 + MGC_O_HDRC_FIFOSIZE);
1196 /* 0's returned when no more endpoints */
1199 musb->nr_endpoints++;
1200 musb->wEndMask |= (1 << bEnd);
1202 hw_ep->wMaxPacketSizeTx = 1 << (reg & 0x0f);
1204 /* shared TX/RX FIFO? */
1205 if ((reg & 0xf0) == 0xf0) {
1206 hw_ep->wMaxPacketSizeRx = hw_ep->wMaxPacketSizeTx;
1207 hw_ep->bIsSharedFifo = TRUE;
1210 hw_ep->wMaxPacketSizeRx = 1 << ((reg & 0xf0) >> 4);
1211 hw_ep->bIsSharedFifo = FALSE;
1214 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1216 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1217 /* pick an RX/TX endpoint for bulk */
1218 if (hw_ep->wMaxPacketSizeTx < 512
1219 || hw_ep->wMaxPacketSizeRx < 512)
1222 /* REVISIT: this algorithm is lazy, we should at least
1223 * try to pick a double buffered endpoint.
1227 musb->bulk_ep = hw_ep;
1231 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1232 if (!musb->bulk_ep) {
1233 pr_debug( "%s: missing bulk\n", musb_driver_name);
1241 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1243 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1244 * configure endpoints, or take their config from silicon
1246 static int __init musb_core_init(u16 wType, struct musb *musb)
1253 u16 wRelease, wRelMajor, wRelMinor;
1254 char aInfo[78], aRevision[32], aDate[12];
1255 void __iomem *mbase = musb->mregs;
1259 /* log core options (read using indexed model) */
1260 MGC_SelectEnd(mbase, 0);
1261 reg = musb_readb(mbase, 0x10 + MGC_O_HDRC_CONFIGDATA);
1263 strcpy(aInfo, (reg & MGC_M_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1264 if (reg & MGC_M_CONFIGDATA_DYNFIFO) {
1265 strcat(aInfo, ", dyn FIFOs");
1267 if (reg & MGC_M_CONFIGDATA_MPRXE) {
1268 strcat(aInfo, ", bulk combine");
1270 musb->bBulkCombine = TRUE;
1272 strcat(aInfo, " (X)"); /* no driver support */
1275 if (reg & MGC_M_CONFIGDATA_MPTXE) {
1276 strcat(aInfo, ", bulk split");
1278 musb->bBulkSplit = TRUE;
1280 strcat(aInfo, " (X)"); /* no driver support */
1283 if (reg & MGC_M_CONFIGDATA_HBRXE) {
1284 strcat(aInfo, ", HB-ISO Rx");
1285 strcat(aInfo, " (X)"); /* no driver support */
1287 if (reg & MGC_M_CONFIGDATA_HBTXE) {
1288 strcat(aInfo, ", HB-ISO Tx");
1289 strcat(aInfo, " (X)"); /* no driver support */
1291 if (reg & MGC_M_CONFIGDATA_SOFTCONE) {
1292 strcat(aInfo, ", SoftConn");
1295 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1296 musb_driver_name, reg, aInfo);
1299 dwData = musb_readl(mbase, 0x404);
1300 sprintf(aDate, "%04d-%02x-%02x", (dwData & 0xffff),
1301 (dwData >> 16) & 0xff, (dwData >> 24) & 0xff);
1302 /* FIXME ID2 and ID3 are unused */
1303 dwData = musb_readl(mbase, 0x408);
1304 printk("ID2=%lx\n", (long unsigned)dwData);
1305 dwData = musb_readl(mbase, 0x40c);
1306 printk("ID3=%lx\n", (long unsigned)dwData);
1307 reg = musb_readb(mbase, 0x400);
1308 wType = ('M' == reg) ? MUSB_CONTROLLER_MHDRC : MUSB_CONTROLLER_HDRC;
1312 if (MUSB_CONTROLLER_MHDRC == wType) {
1313 musb->bIsMultipoint = 1;
1316 musb->bIsMultipoint = 0;
1318 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1319 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1321 "%s: kernel must blacklist external hubs\n",
1327 /* log release info */
1328 wRelease = musb_readw(mbase, MGC_O_HDRC_HWVERS);
1329 wRelMajor = (wRelease >> 10) & 0x1f;
1330 wRelMinor = wRelease & 0x3ff;
1331 snprintf(aRevision, 32, "%d.%d%s", wRelMajor,
1332 wRelMinor, (wRelease & 0x8000) ? "RC" : "");
1333 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1334 musb_driver_name, type, aRevision, aDate);
1337 musb->endpoints[0].wMaxPacketSizeTx = MGC_END0_FIFOSIZE;
1338 musb->endpoints[0].wMaxPacketSizeRx = MGC_END0_FIFOSIZE;
1340 /* discover endpoint configuration */
1341 musb->nr_endpoints = 1;
1344 if (reg & MGC_M_CONFIGDATA_DYNFIFO) {
1346 status = ep_config_from_table(musb);
1348 ERR("reconfigure software for Dynamic FIFOs\n");
1353 status = ep_config_from_hw(musb);
1355 ERR("reconfigure software for static FIFOs\n");
1363 /* finish init, and print endpoint config */
1364 for (i = 0; i < musb->nr_endpoints; i++) {
1365 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1367 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1368 #ifdef CONFIG_USB_TUSB6010
1369 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1370 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1371 hw_ep->fifo_sync_va =
1372 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1375 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1377 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1380 hw_ep->regs = MGC_END_OFFSET(i, 0) + mbase;
1381 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1382 hw_ep->target_regs = MGC_BUSCTL_OFFSET(i, 0) + mbase;
1383 hw_ep->rx_reinit = 1;
1384 hw_ep->tx_reinit = 1;
1387 if (hw_ep->wMaxPacketSizeTx) {
1389 "%s: hw_ep %d%s, %smax %d\n",
1390 musb_driver_name, i,
1391 hw_ep->bIsSharedFifo ? "shared" : "tx",
1392 hw_ep->tx_double_buffered
1393 ? "doublebuffer, " : "",
1394 hw_ep->wMaxPacketSizeTx);
1396 if (hw_ep->wMaxPacketSizeRx && !hw_ep->bIsSharedFifo) {
1398 "%s: hw_ep %d%s, %smax %d\n",
1399 musb_driver_name, i,
1401 hw_ep->rx_double_buffered
1402 ? "doublebuffer, " : "",
1403 hw_ep->wMaxPacketSizeRx);
1405 if (!(hw_ep->wMaxPacketSizeTx || hw_ep->wMaxPacketSizeRx))
1406 DBG(1, "hw_ep %d not configured\n", i);
1412 /*-------------------------------------------------------------------------*/
1414 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
1416 static irqreturn_t generic_interrupt(int irq, void *__hci)
1418 unsigned long flags;
1419 irqreturn_t retval = IRQ_NONE;
1420 struct musb *musb = __hci;
1422 spin_lock_irqsave(&musb->Lock, flags);
1424 musb->int_usb = musb_readb(musb->mregs, MGC_O_HDRC_INTRUSB);
1425 musb->int_tx = musb_readw(musb->mregs, MGC_O_HDRC_INTRTX);
1426 musb->int_rx = musb_readw(musb->mregs, MGC_O_HDRC_INTRRX);
1428 if (musb->int_usb || musb->int_tx || musb->int_rx)
1429 retval = musb_interrupt(musb);
1431 spin_unlock_irqrestore(&musb->Lock, flags);
1433 /* REVISIT we sometimes get spurious IRQs on g_ep0
1436 if (retval != IRQ_HANDLED)
1437 DBG(5, "spurious?\n");
1443 #define generic_interrupt NULL
1447 * handle all the irqs defined by the HDRC core. for now we expect: other
1448 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1449 * will be assigned, and the irq will already have been acked.
1451 * called in irq context with spinlock held, irqs blocked
1453 irqreturn_t musb_interrupt(struct musb *musb)
1455 irqreturn_t retval = IRQ_NONE;
1460 devctl = musb_readb(musb->mregs, MGC_O_HDRC_DEVCTL);
1461 power = musb_readb(musb->mregs, MGC_O_HDRC_POWER);
1463 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
1464 (devctl & MGC_M_DEVCTL_HM) ? "host" : "peripheral",
1465 musb->int_usb, musb->int_tx, musb->int_rx);
1467 /* the core can interrupt us for multiple reasons; docs have
1468 * a generic interrupt flowchart to follow
1470 if (musb->int_usb & STAGE0_MASK)
1471 retval |= musb_stage0_irq(musb, musb->int_usb,
1474 /* "stage 1" is handling endpoint irqs */
1476 /* handle endpoint 0 first */
1477 if (musb->int_tx & 1) {
1478 if (devctl & MGC_M_DEVCTL_HM)
1479 retval |= musb_h_ep0_irq(musb);
1481 retval |= musb_g_ep0_irq(musb);
1484 /* RX on endpoints 1-15 */
1485 reg = musb->int_rx >> 1;
1489 // MGC_SelectEnd(musb->mregs, ep_num);
1490 /* REVISIT just retval = ep->rx_irq(...) */
1491 retval = IRQ_HANDLED;
1492 if (devctl & MGC_M_DEVCTL_HM) {
1493 if (is_host_capable())
1494 musb_host_rx(musb, ep_num);
1496 if (is_peripheral_capable())
1497 musb_g_rx(musb, ep_num);
1505 /* TX on endpoints 1-15 */
1506 reg = musb->int_tx >> 1;
1510 // MGC_SelectEnd(musb->mregs, ep_num);
1511 /* REVISIT just retval |= ep->tx_irq(...) */
1512 retval = IRQ_HANDLED;
1513 if (devctl & MGC_M_DEVCTL_HM) {
1514 if (is_host_capable())
1515 musb_host_tx(musb, ep_num);
1517 if (is_peripheral_capable())
1518 musb_g_tx(musb, ep_num);
1525 /* finish handling "global" interrupts after handling fifos */
1527 retval |= musb_stage2_irq(musb,
1528 musb->int_usb, devctl, power);
1534 #ifndef CONFIG_USB_INVENTRA_FIFO
1535 static int __initdata use_dma = 1;
1537 /* "modprobe ... use_dma=0" etc */
1538 module_param(use_dma, bool, 0);
1539 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1541 void musb_dma_completion(struct musb *musb, u8 epnum, u8 bTransmit)
1543 u8 devctl = musb_readb(musb->mregs, MGC_O_HDRC_DEVCTL);
1545 /* called with controller lock already held */
1548 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1549 if (!is_cppi_enabled()) {
1551 if (devctl & MGC_M_DEVCTL_HM)
1552 musb_h_ep0_irq(musb);
1554 musb_g_ep0_irq(musb);
1558 /* endpoints 1..15 */
1560 if (devctl & MGC_M_DEVCTL_HM) {
1561 if (is_host_capable())
1562 musb_host_tx(musb, epnum);
1564 if (is_peripheral_capable())
1565 musb_g_tx(musb, epnum);
1569 if (devctl & MGC_M_DEVCTL_HM) {
1570 if (is_host_capable())
1571 musb_host_rx(musb, epnum);
1573 if (is_peripheral_capable())
1574 musb_g_rx(musb, epnum);
1584 /*-------------------------------------------------------------------------*/
1589 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1591 struct musb *musb = dev_to_musb(dev);
1592 unsigned long flags;
1595 spin_lock_irqsave(&musb->Lock, flags);
1596 ret = sprintf(buf, "%s\n", otg_state_string(musb));
1597 spin_unlock_irqrestore(&musb->Lock, flags);
1603 musb_mode_store(struct device *dev, struct device_attribute *attr,
1604 const char *buf, size_t n)
1606 struct musb *musb = dev_to_musb(dev);
1607 unsigned long flags;
1609 spin_lock_irqsave(&musb->Lock, flags);
1610 if (!strncmp(buf, "host", 4))
1611 musb_platform_set_mode(musb, MUSB_HOST);
1612 if (!strncmp(buf, "peripheral", 10))
1613 musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1614 if (!strncmp(buf, "otg", 3))
1615 musb_platform_set_mode(musb, MUSB_OTG);
1616 spin_unlock_irqrestore(&musb->Lock, flags);
1620 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1623 musb_cable_show(struct device *dev, struct device_attribute *attr, char *buf)
1625 struct musb *musb = dev_to_musb(dev);
1626 char *v1= "", *v2 = "?";
1627 unsigned long flags;
1630 spin_lock_irqsave(&musb->Lock, flags);
1631 #if defined(CONFIG_USB_TUSB6010) && !defined(CONFIG_USB_MUSB_OTG)
1632 /* REVISIT: connect-A != connect-B ... */
1633 vbus = musb_platform_get_vbus_status(musb);
1637 v2 = "disconnected";
1639 /* NOTE: board-specific issues, like too-big capacitors keeping
1640 * VBUS high for a long time after power has been removed, can
1641 * cause temporary false indications of a connection.
1643 vbus = musb_readb(musb->mregs, MGC_O_HDRC_DEVCTL);
1645 /* REVISIT retest on real OTG hardware */
1646 switch (musb->board_mode) {
1650 case MUSB_PERIPHERAL:
1655 v2 = (vbus & MGC_M_DEVCTL_BDEVICE) ? "B" : "A";
1658 } else /* VBUS level below A-Valid */
1659 v2 = "disconnected";
1661 musb_platform_try_idle(musb, 0);
1662 spin_unlock_irqrestore(&musb->Lock, flags);
1664 return sprintf(buf, "%s%s\n", v1, v2);
1666 static DEVICE_ATTR(cable, S_IRUGO, musb_cable_show, NULL);
1669 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1670 const char *buf, size_t n)
1672 struct musb *musb = dev_to_musb(dev);
1673 unsigned long flags;
1676 spin_lock_irqsave(&musb->Lock, flags);
1677 if (sscanf(buf, "%lu", &val) < 1) {
1678 printk(KERN_ERR "Invalid VBUS timeout ms value\n");
1681 musb->a_wait_bcon = val;
1682 if (musb->xceiv.state == OTG_STATE_A_WAIT_BCON)
1683 musb->is_active = 0;
1684 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1685 spin_unlock_irqrestore(&musb->Lock, flags);
1691 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1693 struct musb *musb = dev_to_musb(dev);
1694 unsigned long flags;
1697 spin_lock_irqsave(&musb->Lock, flags);
1698 val = musb->a_wait_bcon;
1699 spin_unlock_irqrestore(&musb->Lock, flags);
1701 return sprintf(buf, "%lu\n", val);
1703 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1706 musb_srp_store(struct device *dev, struct device_attribute *attr,
1707 const char *buf, size_t n)
1709 struct musb *musb=dev_to_musb(dev);
1710 unsigned long flags;
1713 if (sscanf(buf, "%hu", &srp) != 1
1715 printk (KERN_ERR "SRP: Value must be 1\n");
1719 spin_lock_irqsave(&musb->Lock, flags);
1721 musb_g_wakeup(musb);
1722 spin_unlock_irqrestore(&musb->Lock, flags);
1726 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1729 /* Only used to provide cable state change events */
1730 static void musb_irq_work(struct work_struct *data)
1732 struct musb *musb = container_of(data, struct musb, irq_work);
1734 sysfs_notify(&musb->controller->kobj, NULL, "cable");
1737 /* --------------------------------------------------------------------------
1741 static struct musb *__init
1742 allocate_instance(struct device *dev, void __iomem *mbase)
1745 struct musb_hw_ep *ep;
1747 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1748 struct usb_hcd *hcd;
1750 hcd = usb_create_hcd(&musb_hc_driver, dev, dev->bus_id);
1753 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1755 musb = hcd_to_musb(hcd);
1756 INIT_LIST_HEAD(&musb->control);
1757 INIT_LIST_HEAD(&musb->in_bulk);
1758 INIT_LIST_HEAD(&musb->out_bulk);
1760 hcd->uses_new_polling = 1;
1762 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1764 musb = kzalloc(sizeof *musb, GFP_KERNEL);
1767 dev_set_drvdata(dev, musb);
1771 musb->mregs = mbase;
1772 musb->ctrl_base = mbase;
1773 musb->nIrq = -ENODEV;
1774 for (epnum = 0, ep = musb->endpoints;
1775 epnum < MUSB_C_NUM_EPS;
1782 musb->controller = dev;
1786 static void musb_free(struct musb *musb)
1788 /* this has multiple entry modes. it handles fault cleanup after
1789 * probe(), where things may be partially set up, as well as rmmod
1790 * cleanup after everything's been de-activated.
1794 device_remove_file(musb->controller, &dev_attr_mode);
1795 device_remove_file(musb->controller, &dev_attr_cable);
1796 device_remove_file(musb->controller, &dev_attr_vbus);
1797 #ifdef CONFIG_USB_MUSB_OTG
1798 device_remove_file(musb->controller, &dev_attr_srp);
1802 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1803 musb_gadget_cleanup(musb);
1806 if (musb->nIrq >= 0) {
1807 disable_irq_wake(musb->nIrq);
1808 free_irq(musb->nIrq, musb);
1810 if (is_dma_capable() && musb->pDmaController) {
1811 struct dma_controller *c = musb->pDmaController;
1813 (void) c->stop(c->pPrivateData);
1814 dma_controller_destroy(c);
1817 musb_writeb(musb->mregs, MGC_O_HDRC_DEVCTL, 0);
1818 musb_platform_exit(musb);
1819 musb_writeb(musb->mregs, MGC_O_HDRC_DEVCTL, 0);
1822 clk_disable(musb->clock);
1823 clk_put(musb->clock);
1826 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1827 usb_put_hcd(musb_to_hcd(musb));
1834 * Perform generic per-controller initialization.
1836 * @pDevice: the controller (already clocked, etc)
1838 * @mregs: virtual address of controller registers,
1839 * not yet corrected for platform-specific offsets
1842 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1846 struct musb_hdrc_platform_data *plat = dev->platform_data;
1848 /* The driver might handle more features than the board; OK.
1849 * Fail when the board needs a feature that's not enabled.
1852 dev_dbg(dev, "no platform_data?\n");
1855 switch (plat->mode) {
1857 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1862 case MUSB_PERIPHERAL:
1863 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1869 #ifdef CONFIG_USB_MUSB_OTG
1875 dev_err(dev, "incompatible Kconfig role setting\n");
1880 musb = allocate_instance(dev, ctrl);
1884 spin_lock_init(&musb->Lock);
1885 musb->board_mode = plat->mode;
1886 musb->board_set_power = plat->set_power;
1887 musb->set_clock = plat->set_clock;
1888 musb->min_power = plat->min_power;
1890 /* Clock usage is chip-specific ... functional clock (DaVinci,
1891 * OMAP2430), or PHY ref (some TUSB6010 boards). All this core
1892 * code does is make sure a clock handle is available; platform
1893 * code manages it during start/stop and suspend/resume.
1896 musb->clock = clk_get(dev, plat->clock);
1897 if (IS_ERR(musb->clock)) {
1898 status = PTR_ERR(musb->clock);
1904 /* assume vbus is off */
1906 /* platform adjusts musb->mregs and musb->isr if needed,
1907 * and activates clocks
1909 musb->isr = generic_interrupt;
1910 status = musb_platform_init(musb);
1919 #ifndef CONFIG_USB_INVENTRA_FIFO
1920 if (use_dma && dev->dma_mask) {
1921 struct dma_controller *c;
1923 c = dma_controller_create(musb, musb->mregs);
1924 musb->pDmaController = c;
1926 (void) c->start(c->pPrivateData);
1929 /* ideally this would be abstracted in platform setup */
1930 if (!is_dma_capable() || !musb->pDmaController)
1931 dev->dma_mask = NULL;
1933 /* be sure interrupts are disabled before connecting ISR */
1934 musb_platform_disable(musb);
1935 musb_generic_disable(musb);
1937 /* setup musb parts of the core (especially endpoints) */
1938 status = musb_core_init(plat->multipoint
1939 ? MUSB_CONTROLLER_MHDRC
1940 : MUSB_CONTROLLER_HDRC, musb);
1944 /* attach to the IRQ */
1945 if (request_irq (nIrq, musb->isr, 0, dev->bus_id, musb)) {
1946 dev_err(dev, "request_irq %d failed!\n", nIrq);
1951 // FIXME this handles wakeup irqs wrong
1952 if (enable_irq_wake(nIrq) == 0)
1953 device_init_wakeup(dev, 1);
1955 pr_info("%s: USB %s mode controller at %p using %s, IRQ %d\n",
1958 switch (musb->board_mode) {
1959 case MUSB_HOST: s = "Host"; break;
1960 case MUSB_PERIPHERAL: s = "Peripheral"; break;
1961 default: s = "OTG"; break;
1964 (is_dma_capable() && musb->pDmaController)
1968 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1969 /* host side needs more setup, except for no-host modes */
1970 if (musb->board_mode != MUSB_PERIPHERAL) {
1971 struct usb_hcd *hcd = musb_to_hcd(musb);
1973 if (musb->board_mode == MUSB_OTG)
1974 hcd->self.otg_port = 1;
1975 musb->xceiv.host = &hcd->self;
1976 hcd->power_budget = 2 * (plat->power ? : 250);
1978 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
1980 /* For the host-only role, we can activate right away.
1981 * (We expect the ID pin to be forcibly grounded!!)
1982 * Otherwise, wait till the gadget driver hooks up.
1984 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
1985 MUSB_HST_MODE(musb);
1986 musb->xceiv.default_a = 1;
1987 musb->xceiv.state = OTG_STATE_A_IDLE;
1989 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
1991 DBG(1, "%s mode, status %d, devctl %02x %c\n",
1993 musb_readb(musb->mregs, MGC_O_HDRC_DEVCTL),
1994 (musb_readb(musb->mregs, MGC_O_HDRC_DEVCTL)
1995 & MGC_M_DEVCTL_BDEVICE
1998 } else /* peripheral is enabled */ {
1999 MUSB_DEV_MODE(musb);
2000 musb->xceiv.default_a = 0;
2001 musb->xceiv.state = OTG_STATE_B_IDLE;
2003 status = musb_gadget_setup(musb);
2005 DBG(1, "%s mode, status %d, dev%02x\n",
2006 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2008 musb_readb(musb->mregs, MGC_O_HDRC_DEVCTL));
2013 musb_debug_create("driver/musb_hdrc", musb);
2017 clk_put(musb->clock);
2018 device_init_wakeup(dev, 0);
2023 INIT_WORK(&musb->irq_work, musb_irq_work);
2026 status = device_create_file(dev, &dev_attr_mode);
2027 status = device_create_file(dev, &dev_attr_cable);
2028 status = device_create_file(dev, &dev_attr_vbus);
2029 #ifdef CONFIG_USB_MUSB_OTG
2030 status = device_create_file(dev, &dev_attr_srp);
2031 #endif /* CONFIG_USB_MUSB_OTG */
2038 musb_platform_exit(musb);
2042 /*-------------------------------------------------------------------------*/
2044 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2045 * bridge to a platform device; this driver then suffices.
2048 #ifndef CONFIG_USB_INVENTRA_FIFO
2049 static u64 *orig_dma_mask;
2052 static int __init musb_probe(struct platform_device *pdev)
2054 struct device *dev = &pdev->dev;
2055 int irq = platform_get_irq(pdev, 0);
2056 struct resource *iomem;
2059 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2060 if (!iomem || irq == 0)
2063 base = ioremap(iomem->start, iomem->end - iomem->start + 1);
2065 dev_err(dev, "ioremap failed\n");
2069 #ifndef CONFIG_USB_INVENTRA_FIFO
2070 /* clobbered by use_dma=n */
2071 orig_dma_mask = dev->dma_mask;
2073 return musb_init_controller(dev, irq, base);
2076 static int __devexit musb_remove(struct platform_device *pdev)
2078 struct musb *musb = dev_to_musb(&pdev->dev);
2079 void __iomem *ctrl_base = musb->ctrl_base;
2081 /* this gets called on rmmod.
2082 * - Host mode: host may still be active
2083 * - Peripheral mode: peripheral is deactivated (or never-activated)
2084 * - OTG mode: both roles are deactivated (or never-activated)
2086 musb_shutdown(pdev);
2087 musb_debug_delete("driver/musb_hdrc", musb);
2088 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2089 if (musb->board_mode == MUSB_HOST)
2090 usb_remove_hcd(musb_to_hcd(musb));
2094 device_init_wakeup(&pdev->dev, 0);
2095 #ifndef CONFIG_USB_INVENTRA_FIFO
2096 pdev->dev.dma_mask = orig_dma_mask;
2103 static int musb_suspend(struct platform_device *pdev, pm_message_t message)
2105 unsigned long flags;
2106 struct musb *musb = dev_to_musb(&pdev->dev);
2111 spin_lock_irqsave(&musb->Lock, flags);
2113 if (is_peripheral_active(musb)) {
2114 /* FIXME force disconnect unless we know USB will wake
2115 * the system up quickly enough to respond ...
2117 } else if (is_host_active(musb)) {
2118 /* we know all the children are suspended; sometimes
2119 * they will even be wakeup-enabled.
2123 if (musb->set_clock)
2124 musb->set_clock(musb->clock, 0);
2126 clk_disable(musb->clock);
2127 spin_unlock_irqrestore(&musb->Lock, flags);
2131 static int musb_resume(struct platform_device *pdev)
2133 unsigned long flags;
2134 struct musb *musb = dev_to_musb(&pdev->dev);
2139 spin_lock_irqsave(&musb->Lock, flags);
2141 if (musb->set_clock)
2142 musb->set_clock(musb->clock, 1);
2144 clk_enable(musb->clock);
2146 /* for static cmos like DaVinci, register values were preserved
2147 * unless for some reason the whole soc powered down and we're
2148 * not treating that as a whole-system restart (e.g. swsusp)
2150 spin_unlock_irqrestore(&musb->Lock, flags);
2155 #define musb_suspend NULL
2156 #define musb_resume NULL
2159 static struct platform_driver musb_driver = {
2161 .name = (char *)musb_driver_name,
2162 .bus = &platform_bus_type,
2163 .owner = THIS_MODULE,
2165 .remove = __devexit_p(musb_remove),
2166 .shutdown = musb_shutdown,
2167 .suspend = musb_suspend,
2168 .resume = musb_resume,
2171 /*-------------------------------------------------------------------------*/
2173 static int __init musb_init(void)
2175 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2180 pr_info("%s: version " MUSB_VERSION ", "
2181 #ifdef CONFIG_USB_INVENTRA_FIFO
2183 #elif defined(CONFIG_USB_TI_CPPI_DMA)
2185 #elif defined(CONFIG_USB_INVENTRA_DMA)
2187 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
2193 #ifdef CONFIG_USB_MUSB_OTG
2194 "otg (peripheral+host)"
2195 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
2197 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2201 musb_driver_name, debug);
2202 return platform_driver_probe(&musb_driver, musb_probe);
2205 /* make us init after usbcore and before usb
2206 * gadget and host-side drivers start to register
2208 subsys_initcall(musb_init);
2210 static void __exit musb_cleanup(void)
2212 platform_driver_unregister(&musb_driver);
2214 module_exit(musb_cleanup);