1 /*****************************************************************
2 * Copyright 2005 Mentor Graphics Corporation
3 * Copyright (C) 2005-2006 by Texas Instruments
4 * Copyright (C) 2006 by Nokia Corporation
6 * This file is part of the Inventra Controller Driver for Linux.
8 * The Inventra Controller Driver for Linux is free software; you
9 * can redistribute it and/or modify it under the terms of the GNU
10 * General Public License version 2 as published by the Free Software
13 * The Inventra Controller Driver for Linux is distributed in
14 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
15 * without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 * License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with The Inventra Controller Driver for Linux ; if not,
21 * write to the Free Software Foundation, Inc., 59 Temple Place,
22 * Suite 330, Boston, MA 02111-1307 USA
24 * ANY DOWNLOAD, USE, REPRODUCTION, MODIFICATION OR DISTRIBUTION
25 * OF THIS DRIVER INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE
26 * OF THOSE TERMS.THIS DRIVER IS PROVIDED "AS IS" AND MENTOR GRAPHICS
27 * MAKES NO WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THIS DRIVER.
28 * MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES
29 * OF MERCHANTABILITY; FITNESS FOR A PARTICULAR PURPOSE AND
30 * NON-INFRINGEMENT. MENTOR GRAPHICS DOES NOT PROVIDE SUPPORT
31 * SERVICES OR UPDATES FOR THIS DRIVER, EVEN IF YOU ARE A MENTOR
32 * GRAPHICS SUPPORT CUSTOMER.
33 ******************************************************************/
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - <asm/arch/hdrc_cnf.h> for SOC or family details
86 * - platform_device for addressing, irq, and platform_data
87 * - platform_data is mostly for board-specific informarion
89 * Most of the conditional compilation will (someday) vanish.
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/platform_device.h>
100 #include <linux/clk.h>
105 #include <asm/arch/hardware.h>
106 #include <asm/arch/memory.h>
107 #include <asm/mach-types.h>
110 #include "musbdefs.h"
113 #ifdef CONFIG_ARCH_DAVINCI
120 unsigned debug = MUSB_DEBUG;
121 module_param(debug, uint, 0);
122 MODULE_PARM_DESC(debug, "initial debug message level");
124 #define MUSB_VERSION_SUFFIX "/dbg"
127 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
128 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
130 #define MUSB_VERSION_BASE "2.2a/db-0.5.2"
132 #ifndef MUSB_VERSION_SUFFIX
133 #define MUSB_VERSION_SUFFIX ""
135 #define MUSB_VERSION MUSB_VERSION_BASE MUSB_VERSION_SUFFIX
137 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
139 const char musb_driver_name[] = "musb_hdrc";
141 MODULE_DESCRIPTION(DRIVER_INFO);
142 MODULE_AUTHOR(DRIVER_AUTHOR);
143 MODULE_LICENSE("GPL");
146 /*-------------------------------------------------------------------------*/
148 #ifdef CONFIG_USB_MUSB_OTG
150 /* For debugging/prototyping: allow disabling host side support on boards
151 * with Mini-AB (or Mini-A) connectors, making peripheral side support look
152 * like pure peripherals (not reporting OTG capabilities, and able to
153 * draw a full 100mA unit load).
157 module_param(musb_otg, bool, 0);
158 MODULE_PARM_DESC(musb_otg, "enable/disable OTG capabilities");
161 static inline struct musb *dev_to_musb(struct device *dev)
163 #ifdef CONFIG_USB_MUSB_HDRC_HCD
164 /* usbcore insists dev->driver_data is a "struct hcd *" */
165 return hcd_to_musb(dev_get_drvdata(dev));
167 return dev_get_drvdata(dev);
171 /*-------------------------------------------------------------------------*/
173 #ifndef CONFIG_USB_TUSB6010
175 * Load an endpoint's FIFO
177 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 wCount, const u8 *pSource)
179 void __iomem *fifo = hw_ep->fifo;
181 prefetch((u8 *)pSource);
183 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
184 'T', hw_ep->bLocalEnd, fifo, wCount, pSource);
186 /* we can't assume unaligned reads work */
187 if (likely((0x01 & (unsigned long) pSource) == 0)) {
190 /* best case is 32bit-aligned source address */
191 if ((0x02 & (unsigned long) pSource) == 0) {
193 writesl(fifo, pSource + index, wCount >> 2);
194 index += wCount & ~0x03;
197 musb_writew(fifo, 0, *(u16*)&pSource[index]);
202 writesw(fifo, pSource + index, wCount >> 1);
203 index += wCount & ~0x01;
207 musb_writeb(fifo, 0, pSource[index]);
210 writesb(fifo, pSource, wCount);
215 * Unload an endpoint's FIFO
217 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 wCount, u8 *pDest)
219 void __iomem *fifo = hw_ep->fifo;
221 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
222 'R', hw_ep->bLocalEnd, fifo, wCount, pDest);
224 /* we can't assume unaligned writes work */
225 if (likely((0x01 & (unsigned long) pDest) == 0)) {
228 /* best case is 32bit-aligned destination address */
229 if ((0x02 & (unsigned long) pDest) == 0) {
231 readsl(fifo, pDest, wCount >> 2);
232 index = wCount & ~0x03;
235 *(u16*)&pDest[index] = musb_readw(fifo, 0);
240 readsw(fifo, pDest, wCount >> 1);
241 index = wCount & ~0x01;
245 pDest[index] = musb_readb(fifo, 0);
248 readsb(fifo, pDest, wCount);
252 #endif /* normal PIO */
255 /*-------------------------------------------------------------------------*/
257 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
258 static const u8 musb_test_packet[53] = {
259 /* implicit SYNC then DATA0 to start */
262 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
264 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
266 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
267 /* JJJJJJJKKKKKKK x8 */
268 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
270 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
271 /* JKKKKKKK x10, JK */
272 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
274 /* implicit CRC16 then EOP to end */
277 void musb_load_testpacket(struct musb *musb)
279 void __iomem *regs = musb->aLocalEnd[0].regs;
281 MGC_SelectEnd(musb->pRegs, 0);
282 musb_write_fifo(musb->control_ep,
283 sizeof(musb_test_packet), musb_test_packet);
284 musb_writew(regs, MGC_O_HDRC_CSR0, MGC_M_CSR0_TXPKTRDY);
287 /*-------------------------------------------------------------------------*/
290 * Interrupt Service Routine to record USB "global" interrupts.
291 * Since these do not happen often and signify things of
292 * paramount importance, it seems OK to check them individually;
293 * the order of the tests is specified in the manual
295 * @param pThis instance pointer
296 * @param bIntrUSB register contents
301 #define STAGE0_MASK (MGC_M_INTR_RESUME | MGC_M_INTR_SESSREQ \
302 | MGC_M_INTR_VBUSERROR | MGC_M_INTR_CONNECT \
305 static irqreturn_t musb_stage0_irq(struct musb * pThis, u8 bIntrUSB,
308 irqreturn_t handled = IRQ_NONE;
309 #ifdef CONFIG_USB_MUSB_HDRC_HCD
310 void __iomem *pBase = pThis->pRegs;
313 DBG(3, "<== Power=%02x, DevCtl=%02x, bIntrUSB=0x%x\n", power, devctl,
316 /* in host mode, the peripheral may issue remote wakeup.
317 * in peripheral mode, the host may resume the link.
318 * spurious RESUME irqs happen too, paired with SUSPEND.
320 if (bIntrUSB & MGC_M_INTR_RESUME) {
321 handled = IRQ_HANDLED;
322 DBG(3, "RESUME (%s)\n", otg_state_string(pThis));
324 if (devctl & MGC_M_DEVCTL_HM) {
325 #ifdef CONFIG_USB_MUSB_HDRC_HCD
326 switch (pThis->xceiv.state) {
327 case OTG_STATE_A_SUSPEND:
328 /* remote wakeup? later, GetPortStatus
329 * will stop RESUME signaling
331 if (power & MGC_M_POWER_RESUME) {
332 power &= ~MGC_M_POWER_SUSPENDM;
333 musb_writeb(pBase, MGC_O_HDRC_POWER,
334 power | MGC_M_POWER_RESUME);
336 pThis->port1_status |=
337 MUSB_PORT_STAT_RESUME
338 | USB_PORT_STAT_C_SUSPEND;
339 pThis->rh_timer = jiffies
340 + msecs_to_jiffies(20);
342 pThis->xceiv.state = OTG_STATE_A_HOST;
343 pThis->is_active = 1;
344 usb_hcd_resume_root_hub(
347 } else if (power & MGC_M_POWER_SUSPENDM) {
349 pThis->int_usb &= ~MGC_M_INTR_SUSPEND;
352 case OTG_STATE_B_WAIT_ACON:
353 pThis->xceiv.state = OTG_STATE_B_PERIPHERAL;
354 pThis->is_active = 1;
355 MUSB_DEV_MODE(pThis);
358 WARN("bogus %s RESUME (%s)\n",
360 otg_state_string(pThis));
364 switch (pThis->xceiv.state) {
365 #ifdef CONFIG_USB_MUSB_HDRC_HCD
366 case OTG_STATE_A_SUSPEND:
367 /* possibly DISCONNECT is upcoming */
368 pThis->xceiv.state = OTG_STATE_A_HOST;
369 usb_hcd_resume_root_hub(musb_to_hcd(pThis));
372 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
373 case OTG_STATE_B_WAIT_ACON:
374 case OTG_STATE_B_PERIPHERAL:
375 musb_g_resume(pThis);
377 case OTG_STATE_B_IDLE:
378 pThis->int_usb &= ~MGC_M_INTR_SUSPEND;
382 WARN("bogus %s RESUME (%s)\n",
384 otg_state_string(pThis));
389 #ifdef CONFIG_USB_MUSB_HDRC_HCD
390 /* see manual for the order of the tests */
391 if (bIntrUSB & MGC_M_INTR_SESSREQ) {
392 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(pThis));
394 /* IRQ arrives from ID pin sense or (later, if VBUS power
395 * is removed) SRP. responses are time critical:
396 * - turn on VBUS (with silicon-specific mechanism)
397 * - go through A_WAIT_VRISE
398 * - ... to A_WAIT_BCON.
399 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
401 musb_writeb(pBase, MGC_O_HDRC_DEVCTL, MGC_M_DEVCTL_SESSION);
402 pThis->bEnd0Stage = MGC_END0_START;
403 pThis->xceiv.state = OTG_STATE_A_IDLE;
404 MUSB_HST_MODE(pThis);
405 musb_set_vbus(pThis, 1);
407 handled = IRQ_HANDLED;
410 if (bIntrUSB & MGC_M_INTR_VBUSERROR) {
413 /* During connection as an A-Device, we may see a short
414 * current spikes causing voltage drop, because of cable
415 * and peripheral capacitance combined with vbus draw.
416 * (So: less common with truly self-powered devices, where
417 * vbus doesn't act like a power supply.)
419 * Such spikes are short; usually less than ~500 usec, max
420 * of ~2 msec. That is, they're not sustained overcurrent
421 * errors, though they're reported using VBUSERROR irqs.
423 * Workarounds: (a) hardware: use self powered devices.
424 * (b) software: ignore non-repeated VBUS errors.
426 * REVISIT: do delays from lots of DEBUG_KERNEL checks
427 * make trouble here, keeping VBUS < 4.4V ?
429 switch (pThis->xceiv.state) {
430 case OTG_STATE_A_HOST:
431 /* recovery is dicey once we've gotten past the
432 * initial stages of enumeration, but if VBUS
433 * stayed ok at the other end of the link, and
434 * another reset is due (at least for high speed,
435 * to redo the chirp etc), it might work OK...
437 case OTG_STATE_A_WAIT_BCON:
438 case OTG_STATE_A_WAIT_VRISE:
439 if (pThis->vbuserr_retry) {
440 pThis->vbuserr_retry--;
442 devctl |= MGC_M_DEVCTL_SESSION;
443 musb_writeb(pBase, MGC_O_HDRC_DEVCTL, devctl);
445 pThis->port1_status |=
446 (1 << USB_PORT_FEAT_OVER_CURRENT)
447 | (1 << USB_PORT_FEAT_C_OVER_CURRENT);
454 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
455 otg_state_string(pThis),
458 switch (devctl & MGC_M_DEVCTL_VBUS) {
459 case 0 << MGC_S_DEVCTL_VBUS:
460 s = "<SessEnd"; break;
461 case 1 << MGC_S_DEVCTL_VBUS:
462 s = "<AValid"; break;
463 case 2 << MGC_S_DEVCTL_VBUS:
464 s = "<VBusValid"; break;
465 //case 3 << MGC_S_DEVCTL_VBUS:
469 VBUSERR_RETRY_COUNT - pThis->vbuserr_retry,
470 pThis->port1_status);
472 /* go through A_WAIT_VFALL then start a new session */
474 musb_set_vbus(pThis, 0);
475 handled = IRQ_HANDLED;
478 if (bIntrUSB & MGC_M_INTR_CONNECT) {
479 handled = IRQ_HANDLED;
480 pThis->is_active = 1;
481 set_bit(HCD_FLAG_SAW_IRQ, &musb_to_hcd(pThis)->flags);
483 pThis->bEnd0Stage = MGC_END0_START;
485 #ifdef CONFIG_USB_MUSB_OTG
486 /* flush endpoints when transitioning from Device Mode */
487 if (is_peripheral_active(pThis)) {
488 // REVISIT HNP; just force disconnect
490 pThis->bDelayPortPowerOff = FALSE;
492 pThis->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
493 |USB_PORT_STAT_HIGH_SPEED
494 |USB_PORT_STAT_ENABLE
496 pThis->port1_status |= USB_PORT_STAT_CONNECTION
497 |(USB_PORT_STAT_C_CONNECTION << 16);
499 /* high vs full speed is just a guess until after reset */
500 if (devctl & MGC_M_DEVCTL_LSDEV)
501 pThis->port1_status |= USB_PORT_STAT_LOW_SPEED;
503 usb_hcd_poll_rh_status(musb_to_hcd(pThis));
505 MUSB_HST_MODE(pThis);
507 /* indicate new connection to OTG machine */
508 switch (pThis->xceiv.state) {
509 case OTG_STATE_B_WAIT_ACON:
510 pThis->xceiv.state = OTG_STATE_B_HOST;
513 if ((devctl & MGC_M_DEVCTL_VBUS)
514 == (3 << MGC_S_DEVCTL_VBUS))
515 pThis->xceiv.state = OTG_STATE_A_HOST;
518 DBG(1, "CONNECT (%s) devctl %02x\n",
519 otg_state_string(pThis), devctl);
521 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
523 /* mentor saves a bit: bus reset and babble share the same irq.
524 * only host sees babble; only peripheral sees bus reset.
526 if (bIntrUSB & MGC_M_INTR_RESET) {
527 if (devctl & MGC_M_DEVCTL_HM) {
530 /* REVISIT it's unclear how to handle this. Mentor's
531 * code stopped the whole USB host, which is clearly
532 * very wrong. Docs say (15.1) that babble ends the
533 * current sesssion, so shutdown _with restart_ would
534 * be appropriate ... except that seems to be wrong,
535 * at least some lowspeed enumerations trigger the
536 * babbles without aborting the session!
538 * (A "babble" IRQ seems quite pointless...)
542 DBG(1, "BUS RESET\n");
545 schedule_work(&pThis->irq_work);
548 handled = IRQ_HANDLED;
555 * Interrupt Service Routine to record USB "global" interrupts.
556 * Since these do not happen often and signify things of
557 * paramount importance, it seems OK to check them individually;
558 * the order of the tests is specified in the manual
560 * @param pThis instance pointer
561 * @param bIntrUSB register contents
565 static irqreturn_t musb_stage2_irq(struct musb * pThis, u8 bIntrUSB,
568 irqreturn_t handled = IRQ_NONE;
571 /* REVISIT ... this would be for multiplexing periodic endpoints, or
572 * supporting transfer phasing to prevent exceeding ISO bandwidth
573 * limits of a given frame or microframe.
575 * It's not needed for peripheral side, which dedicates endpoints;
576 * though it _might_ use SOF irqs for other purposes.
578 * And it's not currently needed for host side, which also dedicates
579 * endpoints, relies on TX/RX interval registers, and isn't claimed
580 * to support ISO transfers yet.
582 if (bIntrUSB & MGC_M_INTR_SOF) {
583 void __iomem *pBase = pThis->pRegs;
584 struct musb_hw_ep *ep;
588 DBG(6, "START_OF_FRAME\n");
589 handled = IRQ_HANDLED;
591 /* start any periodic Tx transfers waiting for current frame */
592 wFrame = musb_readw(pBase, MGC_O_HDRC_FRAME);
593 ep = pThis->aLocalEnd;
594 for (bEnd = 1; (bEnd < pThis->bEndCount)
595 && (pThis->wEndMask >= (1 << bEnd));
597 // FIXME handle framecounter wraps (12 bits)
598 // eliminate duplicated StartUrb logic
599 if (ep->dwWaitFrame >= wFrame) {
601 printk("SOF --> periodic TX%s on %d\n",
602 ep->tx_channel ? " DMA" : "",
605 musb_h_tx_start(pThis, bEnd);
607 cppi_hostdma_start(pThis, bEnd);
609 } /* end of for loop */
613 if ((bIntrUSB & MGC_M_INTR_DISCONNECT) && !pThis->bIgnoreDisconnect) {
614 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
615 otg_state_string(pThis),
616 MUSB_MODE(pThis), devctl);
617 handled = IRQ_HANDLED;
619 switch (pThis->xceiv.state) {
620 #ifdef CONFIG_USB_MUSB_HDRC_HCD
621 case OTG_STATE_A_HOST:
622 case OTG_STATE_A_SUSPEND:
623 musb_root_disconnect(pThis);
626 #ifdef CONFIG_USB_MUSB_OTG
627 case OTG_STATE_A_PERIPHERAL:
628 case OTG_STATE_B_HOST:
629 musb_root_disconnect(pThis);
631 case OTG_STATE_B_WAIT_ACON:
633 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
634 case OTG_STATE_B_PERIPHERAL:
635 musb_g_disconnect(pThis);
639 WARN("unhandled DISCONNECT transition (%s)\n",
640 otg_state_string(pThis));
644 schedule_work(&pThis->irq_work);
647 if (bIntrUSB & MGC_M_INTR_SUSPEND) {
648 DBG(1, "SUSPEND (%s) devctl %02x\n",
649 otg_state_string(pThis), devctl);
650 handled = IRQ_HANDLED;
652 switch (pThis->xceiv.state) {
653 case OTG_STATE_B_PERIPHERAL:
654 musb_g_suspend(pThis);
655 pThis->is_active = is_otg_enabled(pThis)
656 && pThis->xceiv.gadget->b_hnp_enable;
657 if (pThis->is_active) {
658 pThis->xceiv.state = OTG_STATE_B_WAIT_ACON;
659 /* REVISIT timeout for b_ase0_brst, etc */
662 case OTG_STATE_A_HOST:
663 pThis->xceiv.state = OTG_STATE_A_SUSPEND;
664 pThis->is_active = is_otg_enabled(pThis)
665 && pThis->xceiv.host->b_hnp_enable;
668 /* "should not happen" */
669 pThis->is_active = 0;
678 /*-------------------------------------------------------------------------*/
681 * Program the HDRC to start (enable interrupts, dma, etc.).
683 void musb_start(struct musb *musb)
685 void __iomem *regs = musb->pRegs;
686 u8 devctl = musb_readb(regs, MGC_O_HDRC_DEVCTL);
688 DBG(2, "<== devctl %02x\n", devctl);
690 /* Set INT enable registers, enable interrupts */
691 musb_writew(regs, MGC_O_HDRC_INTRTXE, musb->wEndMask);
692 musb_writew(regs, MGC_O_HDRC_INTRRXE, musb->wEndMask & 0xfffe);
693 musb_writeb(regs, MGC_O_HDRC_INTRUSBE, 0xf7);
695 musb_writeb(regs, MGC_O_HDRC_TESTMODE, 0);
697 /* put into basic highspeed mode and start session */
698 musb_writeb(regs, MGC_O_HDRC_POWER, MGC_M_POWER_ISOUPDATE
699 | MGC_M_POWER_SOFTCONN
701 /* ENSUSPEND wedges tusb */
702 // | MGC_M_POWER_ENSUSPEND
706 devctl = musb_readb(regs, MGC_O_HDRC_DEVCTL);
707 devctl &= ~MGC_M_DEVCTL_SESSION;
709 if (is_otg_enabled(musb)) {
710 /* session started after:
711 * (a) ID-grounded irq, host mode;
712 * (b) vbus present/connect IRQ, peripheral mode;
713 * (c) peripheral initiates, using SRP
715 if ((devctl & MGC_M_DEVCTL_VBUS) == MGC_M_DEVCTL_VBUS)
718 devctl |= MGC_M_DEVCTL_SESSION;
720 } else if (is_host_enabled(musb)) {
721 /* assume ID pin is hard-wired to ground */
722 devctl |= MGC_M_DEVCTL_SESSION;
724 } else /* peripheral is enabled */ {
725 if ((devctl & MGC_M_DEVCTL_VBUS) == MGC_M_DEVCTL_VBUS)
728 musb_platform_enable(musb);
729 musb_writeb(regs, MGC_O_HDRC_DEVCTL, devctl);
733 static void musb_generic_disable(struct musb *pThis)
735 void __iomem *pBase = pThis->pRegs;
738 /* disable interrupts */
739 musb_writeb(pBase, MGC_O_HDRC_INTRUSBE, 0);
740 musb_writew(pBase, MGC_O_HDRC_INTRTX, 0);
741 musb_writew(pBase, MGC_O_HDRC_INTRRX, 0);
744 musb_writeb(pBase, MGC_O_HDRC_DEVCTL, 0);
746 /* flush pending interrupts */
747 temp = musb_readb(pBase, MGC_O_HDRC_INTRUSB);
748 temp = musb_readw(pBase, MGC_O_HDRC_INTRTX);
749 temp = musb_readw(pBase, MGC_O_HDRC_INTRRX);
754 * Make the HDRC stop (disable interrupts, etc.);
755 * reversible by musb_start
756 * called on gadget driver unregister
757 * with controller locked, irqs blocked
758 * acts as a NOP unless some role activated the hardware
760 void musb_stop(struct musb *musb)
762 /* stop IRQs, timers, ... */
763 musb_platform_disable(musb);
764 musb_generic_disable(musb);
765 DBG(3, "HDRC disabled\n");
768 * - mark host and/or peripheral drivers unusable/inactive
769 * - disable DMA (and enable it in HdrcStart)
770 * - make sure we can musb_start() after musb_stop(); with
771 * OTG mode, gadget driver module rmmod/modprobe cycles that
774 musb_platform_try_idle(musb);
777 static void musb_shutdown(struct platform_device *pdev)
779 struct musb *musb = dev_to_musb(&pdev->dev);
782 spin_lock_irqsave(&musb->Lock, flags);
783 musb_platform_disable(musb);
784 musb_generic_disable(musb);
785 spin_unlock_irqrestore(&musb->Lock, flags);
787 /* FIXME power down */
791 /*-------------------------------------------------------------------------*/
794 * The silicon either has hard-wired endpoint configurations, or else
795 * "dynamic fifo" sizing. The driver has support for both, though at this
796 * writing only the dynamic sizing is very well tested. We use normal
797 * idioms to so both modes are compile-tested, but dead code elimination
798 * leaves only the relevant one in the object file.
800 * We don't currently use dynamic fifo setup capability to do anything
801 * more than selecting one of a bunch of predefined configurations.
803 #ifdef MUSB_C_DYNFIFO_DEF
804 #define can_dynfifo() 1
806 #define can_dynfifo() 0
809 #ifdef CONFIG_USB_TUSB6010
810 static ushort __devinitdata fifo_mode = 4;
812 static ushort __devinitdata fifo_mode = 2;
815 /* "modprobe ... fifo_mode=1" etc */
816 module_param(fifo_mode, ushort, 0);
817 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
820 #define DYN_FIFO_SIZE (1<<(MUSB_C_RAM_BITS+2))
822 enum fifo_style { FIFO_RXTX, FIFO_TX, FIFO_RX } __attribute__ ((packed));
823 enum buf_mode { BUF_SINGLE, BUF_DOUBLE } __attribute__ ((packed));
827 enum fifo_style style;
833 * tables defining fifo_mode values. define more if you like.
834 * for host side, make sure both halves of ep1 are set up.
837 /* mode 0 - fits in 2KB */
838 static const struct fifo_cfg __devinitdata mode_0_cfg[] = {
839 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
840 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
841 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
842 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
843 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
846 /* mode 1 - fits in 4KB */
847 static const struct fifo_cfg __devinitdata mode_1_cfg[] = {
848 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
849 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
850 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
851 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
852 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
855 /* mode 2 - fits in 4KB */
856 static const struct fifo_cfg __devinitdata mode_2_cfg[] = {
857 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
858 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
859 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
860 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
861 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
862 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
865 /* mode 3 - fits in 4KB */
866 static const struct fifo_cfg __devinitdata mode_3_cfg[] = {
867 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
868 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
869 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
870 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
871 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
872 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
875 /* mode 4 - fits in 16KB */
876 static const struct fifo_cfg __devinitdata mode_4_cfg[] = {
877 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
878 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
879 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
880 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
881 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
882 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
883 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
884 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
885 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
886 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
887 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
888 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
889 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
890 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
891 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
892 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
893 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
894 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
895 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 512, },
896 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 512, },
897 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 512, },
898 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 512, },
899 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 512, },
900 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 512, },
901 { .hw_ep_num = 13, .style = FIFO_TX, .maxpacket = 512, },
902 { .hw_ep_num = 13, .style = FIFO_RX, .maxpacket = 512, },
903 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
904 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
909 * configure a fifo; for non-shared endpoints, this may be called
910 * once for a tx fifo and once for an rx fifo.
912 * returns negative errno or offset for next fifo.
915 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
916 const struct fifo_cfg *cfg, u16 offset)
918 void __iomem *mbase = musb->pRegs;
920 u16 maxpacket = cfg->maxpacket;
921 u16 c_off = offset >> 3;
924 /* expect hw_ep has already been zero-initialized */
926 size = ffs(max(maxpacket, (u16) 8)) - 1;
927 maxpacket = 1 << size;
930 if (cfg->mode == BUF_DOUBLE) {
931 if ((offset + (maxpacket << 1)) > DYN_FIFO_SIZE)
933 c_size |= MGC_M_FIFOSZ_DPB;
935 if ((offset + maxpacket) > DYN_FIFO_SIZE)
939 /* configure the FIFO */
940 musb_writeb(mbase, MGC_O_HDRC_INDEX, hw_ep->bLocalEnd);
942 #ifdef CONFIG_USB_MUSB_HDRC_HCD
943 /* EP0 reserved endpoint for control, bidirectional;
944 * EP1 reserved for bulk, two unidirection halves.
946 if (hw_ep->bLocalEnd == 1)
947 musb->bulk_ep = hw_ep;
948 /* REVISIT error check: be sure ep0 can both rx and tx ... */
950 switch (cfg->style) {
952 musb_writeb(mbase, MGC_O_HDRC_TXFIFOSZ, c_size);
953 musb_writew(mbase, MGC_O_HDRC_TXFIFOADD, c_off);
954 hw_ep->tx_double_buffered = !!(c_size & MGC_M_FIFOSZ_DPB);
955 hw_ep->wMaxPacketSizeTx = maxpacket;
958 musb_writeb(mbase, MGC_O_HDRC_RXFIFOSZ, c_size);
959 musb_writew(mbase, MGC_O_HDRC_RXFIFOADD, c_off);
960 hw_ep->rx_double_buffered = !!(c_size & MGC_M_FIFOSZ_DPB);
961 hw_ep->wMaxPacketSizeRx = maxpacket;
964 musb_writeb(mbase, MGC_O_HDRC_TXFIFOSZ, c_size);
965 musb_writew(mbase, MGC_O_HDRC_TXFIFOADD, c_off);
966 hw_ep->rx_double_buffered = !!(c_size & MGC_M_FIFOSZ_DPB);
967 hw_ep->wMaxPacketSizeRx = maxpacket;
969 musb_writeb(mbase, MGC_O_HDRC_RXFIFOSZ, c_size);
970 musb_writew(mbase, MGC_O_HDRC_RXFIFOADD, c_off);
971 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
972 hw_ep->wMaxPacketSizeTx = maxpacket;
974 hw_ep->bIsSharedFifo = TRUE;
978 /* NOTE rx and tx endpoint irqs aren't managed separately,
979 * which happens to be ok
981 musb->wEndMask |= (1 << hw_ep->bLocalEnd);
983 return offset + (maxpacket << ((c_size & MGC_M_FIFOSZ_DPB) ? 1 : 0));
986 static const struct fifo_cfg __devinitdata ep0_cfg = {
987 .style = FIFO_RXTX, .maxpacket = 64,
990 static int __devinit ep_config_from_table(struct musb *musb)
992 const struct fifo_cfg *cfg;
995 struct musb_hw_ep *hw_ep = musb->aLocalEnd;
1003 n = ARRAY_SIZE(mode_0_cfg);
1007 n = ARRAY_SIZE(mode_1_cfg);
1011 n = ARRAY_SIZE(mode_2_cfg);
1015 n = ARRAY_SIZE(mode_3_cfg);
1019 n = ARRAY_SIZE(mode_4_cfg);
1023 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1024 musb_driver_name, fifo_mode);
1027 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1028 // assert(offset > 0)
1030 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1031 * be better than static MUSB_C_NUM_EPS and DYN_FIFO_SIZE...
1034 for (i = 0; i < n; i++) {
1035 u8 epn = cfg->hw_ep_num;
1037 if (epn >= MUSB_C_NUM_EPS) {
1038 pr_debug( "%s: invalid ep %d\n",
1039 musb_driver_name, epn);
1042 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1044 pr_debug( "%s: mem overrun, ep %d\n",
1045 musb_driver_name, epn);
1049 musb->bEndCount = max(epn, musb->bEndCount);
1052 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1054 n + 1, MUSB_C_NUM_EPS * 2 - 1,
1055 offset, DYN_FIFO_SIZE);
1057 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1058 if (!musb->bulk_ep) {
1059 pr_debug( "%s: missing bulk\n", musb_driver_name);
1069 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1070 * @param pThis the controller
1072 static int __devinit ep_config_from_hw(struct musb *musb)
1075 struct musb_hw_ep *pEnd;
1076 void *pBase = musb->pRegs;
1078 DBG(2, "<== static silicon ep config\n");
1080 /* FIXME pick up ep0 maxpacket size */
1082 for (bEnd = 1; bEnd < MUSB_C_NUM_EPS; bEnd++) {
1083 MGC_SelectEnd(pBase, bEnd);
1084 pEnd = musb->aLocalEnd + bEnd;
1086 /* read from core using indexed model */
1087 reg = musb_readb(pEnd->regs, 0x10 + MGC_O_HDRC_FIFOSIZE);
1089 /* 0's returned when no more endpoints */
1093 musb->wEndMask |= (1 << bEnd);
1095 pEnd->wMaxPacketSizeTx = 1 << (reg & 0x0f);
1097 /* shared TX/RX FIFO? */
1098 if ((reg & 0xf0) == 0xf0) {
1099 pEnd->wMaxPacketSizeRx = pEnd->wMaxPacketSizeTx;
1100 pEnd->bIsSharedFifo = TRUE;
1103 pEnd->wMaxPacketSizeRx = 1 << ((reg & 0xf0) >> 4);
1104 pEnd->bIsSharedFifo = FALSE;
1107 /* FIXME set up pEnd->{rx,tx}_double_buffered */
1109 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1110 /* pick an RX/TX endpoint for bulk */
1111 if (pEnd->wMaxPacketSizeTx < 512
1112 || pEnd->wMaxPacketSizeRx < 512)
1115 /* REVISIT: this algorithm is lazy, we should at least
1116 * try to pick a double buffered endpoint.
1120 musb->bulk_ep = pEnd;
1124 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1125 if (!musb->bulk_ep) {
1126 pr_debug( "%s: missing bulk\n", musb_driver_name);
1134 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1136 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1137 * configure endpoints, or take their config from silicon
1139 static int __devinit musb_core_init(u16 wType, struct musb *pThis)
1146 u16 wRelease, wRelMajor, wRelMinor;
1147 char aInfo[78], aRevision[32], aDate[12];
1148 void __iomem *pBase = pThis->pRegs;
1152 /* log core options (read using indexed model) */
1153 MGC_SelectEnd(pBase, 0);
1154 reg = musb_readb(pBase, 0x10 + MGC_O_HDRC_CONFIGDATA);
1156 strcpy(aInfo, (reg & MGC_M_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1157 if (reg & MGC_M_CONFIGDATA_DYNFIFO) {
1158 strcat(aInfo, ", dyn FIFOs");
1160 if (reg & MGC_M_CONFIGDATA_MPRXE) {
1161 strcat(aInfo, ", bulk combine");
1163 pThis->bBulkCombine = TRUE;
1165 strcat(aInfo, " (X)"); /* no driver support */
1168 if (reg & MGC_M_CONFIGDATA_MPTXE) {
1169 strcat(aInfo, ", bulk split");
1171 pThis->bBulkSplit = TRUE;
1173 strcat(aInfo, " (X)"); /* no driver support */
1176 if (reg & MGC_M_CONFIGDATA_HBRXE) {
1177 strcat(aInfo, ", HB-ISO Rx");
1178 strcat(aInfo, " (X)"); /* no driver support */
1180 if (reg & MGC_M_CONFIGDATA_HBTXE) {
1181 strcat(aInfo, ", HB-ISO Tx");
1182 strcat(aInfo, " (X)"); /* no driver support */
1184 if (reg & MGC_M_CONFIGDATA_SOFTCONE) {
1185 strcat(aInfo, ", SoftConn");
1188 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1189 musb_driver_name, reg, aInfo);
1192 dwData = musb_readl(pBase, 0x404);
1193 sprintf(aDate, "%04d-%02x-%02x", (dwData & 0xffff),
1194 (dwData >> 16) & 0xff, (dwData >> 24) & 0xff);
1195 /* FIXME ID2 and ID3 are unused */
1196 dwData = musb_readl(pBase, 0x408);
1197 printk("ID2=%lx\n", (long unsigned)dwData);
1198 dwData = musb_readl(pBase, 0x40c);
1199 printk("ID3=%lx\n", (long unsigned)dwData);
1200 reg = musb_readb(pBase, 0x400);
1201 wType = ('M' == reg) ? MUSB_CONTROLLER_MHDRC : MUSB_CONTROLLER_HDRC;
1205 if (MUSB_CONTROLLER_MHDRC == wType) {
1206 pThis->bIsMultipoint = 1;
1209 pThis->bIsMultipoint = 0;
1211 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1212 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1214 "%s: kernel must blacklist external hubs\n",
1220 /* log release info */
1221 wRelease = musb_readw(pBase, MGC_O_HDRC_HWVERS);
1222 wRelMajor = (wRelease >> 10) & 0x1f;
1223 wRelMinor = wRelease & 0x3ff;
1224 snprintf(aRevision, 32, "%d.%d%s", wRelMajor,
1225 wRelMinor, (wRelease & 0x8000) ? "RC" : "");
1226 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1227 musb_driver_name, type, aRevision, aDate);
1230 pThis->aLocalEnd[0].wMaxPacketSizeTx = MGC_END0_FIFOSIZE;
1231 pThis->aLocalEnd[0].wMaxPacketSizeRx = MGC_END0_FIFOSIZE;
1233 /* discover endpoint configuration */
1234 pThis->bEndCount = 1;
1235 pThis->wEndMask = 1;
1237 if (reg & MGC_M_CONFIGDATA_DYNFIFO) {
1239 status = ep_config_from_table(pThis);
1241 ERR("reconfigure software for Dynamic FIFOs\n");
1246 status = ep_config_from_hw(pThis);
1248 ERR("reconfigure software for static FIFOs\n");
1256 /* finish init, and print endpoint config */
1257 for (i = 0; i < pThis->bEndCount; i++) {
1258 struct musb_hw_ep *hw_ep = pThis->aLocalEnd + i;
1260 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + pBase;
1261 #ifdef CONFIG_USB_TUSB6010
1262 hw_ep->fifo_async = pThis->async + 0x400 + MUSB_FIFO_OFFSET(i);
1263 hw_ep->fifo_sync = pThis->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1265 hw_ep->conf = pBase - 0x400 + TUSB_EP0_CONF;
1267 hw_ep->conf = pBase + 0x400 + (((i - 1) & 0xf) << 2);
1270 hw_ep->regs = MGC_END_OFFSET(i, 0) + pBase;
1271 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1272 hw_ep->target_regs = MGC_BUSCTL_OFFSET(i, 0) + pBase;
1273 hw_ep->rx_reinit = 1;
1274 hw_ep->tx_reinit = 1;
1277 if (hw_ep->wMaxPacketSizeTx) {
1279 "%s: hw_ep %d%s, %smax %d\n",
1280 musb_driver_name, i,
1281 hw_ep->bIsSharedFifo ? "shared" : "tx",
1282 hw_ep->tx_double_buffered
1283 ? "doublebuffer, " : "",
1284 hw_ep->wMaxPacketSizeTx);
1286 if (hw_ep->wMaxPacketSizeRx && !hw_ep->bIsSharedFifo) {
1288 "%s: hw_ep %d%s, %smax %d\n",
1289 musb_driver_name, i,
1291 hw_ep->rx_double_buffered
1292 ? "doublebuffer, " : "",
1293 hw_ep->wMaxPacketSizeRx);
1295 if (!(hw_ep->wMaxPacketSizeTx || hw_ep->wMaxPacketSizeRx))
1296 DBG(1, "hw_ep %d not configured\n", i);
1302 /*-------------------------------------------------------------------------*/
1304 #ifdef CONFIG_ARCH_OMAP243X
1306 static irqreturn_t generic_interrupt(int irq, void *__hci)
1308 unsigned long flags;
1309 irqreturn_t retval = IRQ_NONE;
1310 struct musb *musb = __hci;
1312 spin_lock_irqsave(&musb->Lock, flags);
1314 musb->int_usb = musb_readb(musb->pRegs, MGC_O_HDRC_INTRUSB);
1315 musb->int_tx = musb_readw(musb->pRegs, MGC_O_HDRC_INTRTX);
1316 musb->int_rx = musb_readw(musb->pRegs, MGC_O_HDRC_INTRRX);
1318 if (musb->int_usb || musb->int_tx || musb->int_rx)
1319 retval = musb_interrupt(musb);
1321 spin_unlock_irqrestore(&musb->Lock, flags);
1323 /* REVISIT we sometimes get spurious IRQs on g_ep0
1326 if (retval != IRQ_HANDLED)
1327 DBG(5, "spurious?\n");
1333 #define generic_interrupt NULL
1337 * handle all the irqs defined by the HDRC core. for now we expect: other
1338 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1339 * will be assigned, and the irq will already have been acked.
1341 * called in irq context with spinlock held, irqs blocked
1343 irqreturn_t musb_interrupt(struct musb *musb)
1345 irqreturn_t retval = IRQ_NONE;
1350 devctl = musb_readb(musb->pRegs, MGC_O_HDRC_DEVCTL);
1351 power = musb_readb(musb->pRegs, MGC_O_HDRC_POWER);
1353 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
1354 (devctl & MGC_M_DEVCTL_HM) ? "host" : "peripheral",
1355 musb->int_usb, musb->int_tx, musb->int_rx);
1357 /* the core can interrupt us for multiple reasons; docs have
1358 * a generic interrupt flowchart to follow
1360 if (musb->int_usb & STAGE0_MASK)
1361 retval |= musb_stage0_irq(musb, musb->int_usb,
1364 /* "stage 1" is handling endpoint irqs */
1366 /* handle endpoint 0 first */
1367 if (musb->int_tx & 1) {
1368 if (devctl & MGC_M_DEVCTL_HM)
1369 retval |= musb_h_ep0_irq(musb);
1371 retval |= musb_g_ep0_irq(musb);
1374 /* RX on endpoints 1-15 */
1375 reg = musb->int_rx >> 1;
1379 // MGC_SelectEnd(musb->pRegs, ep_num);
1380 /* REVISIT just retval = ep->rx_irq(...) */
1381 retval = IRQ_HANDLED;
1382 if (devctl & MGC_M_DEVCTL_HM) {
1383 if (is_host_capable())
1384 musb_host_rx(musb, ep_num);
1386 if (is_peripheral_capable())
1387 musb_g_rx(musb, ep_num);
1395 /* TX on endpoints 1-15 */
1396 reg = musb->int_tx >> 1;
1400 // MGC_SelectEnd(musb->pRegs, ep_num);
1401 /* REVISIT just retval |= ep->tx_irq(...) */
1402 retval = IRQ_HANDLED;
1403 if (devctl & MGC_M_DEVCTL_HM) {
1404 if (is_host_capable())
1405 musb_host_tx(musb, ep_num);
1407 if (is_peripheral_capable())
1408 musb_g_tx(musb, ep_num);
1415 /* finish handling "global" interrupts after handling fifos */
1417 retval |= musb_stage2_irq(musb,
1418 musb->int_usb, devctl, power);
1424 #ifndef CONFIG_USB_INVENTRA_FIFO
1425 static int __devinitdata use_dma = is_dma_capable();
1427 /* "modprobe ... use_dma=0" etc */
1428 module_param(use_dma, bool, 0);
1429 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1431 void musb_dma_completion(struct musb *musb, u8 bLocalEnd, u8 bTransmit)
1433 u8 devctl = musb_readb(musb->pRegs, MGC_O_HDRC_DEVCTL);
1435 /* called with controller lock already held */
1438 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1439 if (!is_cppi_enabled()) {
1441 if (devctl & MGC_M_DEVCTL_HM)
1442 musb_h_ep0_irq(musb);
1444 musb_g_ep0_irq(musb);
1448 /* endpoints 1..15 */
1450 if (devctl & MGC_M_DEVCTL_HM) {
1451 if (is_host_capable())
1452 musb_host_tx(musb, bLocalEnd);
1454 if (is_peripheral_capable())
1455 musb_g_tx(musb, bLocalEnd);
1459 if (devctl & MGC_M_DEVCTL_HM) {
1460 if (is_host_capable())
1461 musb_host_rx(musb, bLocalEnd);
1463 if (is_peripheral_capable())
1464 musb_g_rx(musb, bLocalEnd);
1471 #define use_dma is_dma_capable()
1474 /*-------------------------------------------------------------------------*/
1479 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1481 struct musb *musb = dev_to_musb(dev);
1482 unsigned long flags;
1485 spin_lock_irqsave(&musb->Lock, flags);
1486 switch (musb->board_mode) {
1488 ret = sprintf(buf, "host\n");
1490 case MUSB_PERIPHERAL:
1491 ret = sprintf(buf, "peripheral\n");
1494 ret = sprintf(buf, "otg\n");
1497 spin_unlock_irqrestore(&musb->Lock, flags);
1501 static DEVICE_ATTR(mode, S_IRUGO, musb_mode_show, NULL);
1504 musb_cable_show(struct device *dev, struct device_attribute *attr, char *buf)
1506 struct musb *musb = dev_to_musb(dev);
1507 char *v1= "", *v2 = "?";
1508 unsigned long flags;
1511 spin_lock_irqsave(&musb->Lock, flags);
1512 #if defined(CONFIG_USB_TUSB6010) && !defined(CONFIG_USB_MUSB_OTG)
1513 /* REVISIT: connect-A != connect-B ... */
1514 vbus = musb_platform_get_vbus_status(musb);
1518 v2 = "disconnected";
1520 /* NOTE: board-specific issues, like too-big capacitors keeping
1521 * VBUS high for a long time after power has been removed, can
1522 * cause temporary false indications of a connection.
1524 vbus = musb_readb(musb->pRegs, MGC_O_HDRC_DEVCTL);
1526 /* REVISIT retest on real OTG hardware */
1527 switch (musb->board_mode) {
1531 case MUSB_PERIPHERAL:
1536 v2 = (vbus & MGC_M_DEVCTL_BDEVICE) ? "B" : "A";
1539 } else /* VBUS level below A-Valid */
1540 v2 = "disconnected";
1542 musb_platform_try_idle(musb);
1543 spin_unlock_irqrestore(&musb->Lock, flags);
1545 return sprintf(buf, "%s%s\n", v1, v2);
1547 static DEVICE_ATTR(cable, S_IRUGO, musb_cable_show, NULL);
1551 /* Only used to provide cable state change events */
1552 static void musb_irq_work(void *data)
1554 struct musb *musb = (struct musb *)data;
1556 sysfs_notify(&musb->controller->kobj, NULL, "cable");
1559 /* --------------------------------------------------------------------------
1563 static struct musb *__devinit
1564 allocate_instance(struct device *dev, void __iomem *mbase)
1567 struct musb_hw_ep *ep;
1569 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1570 struct usb_hcd *hcd;
1572 hcd = usb_create_hcd(&musb_hc_driver, dev, dev->bus_id);
1575 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1577 musb = hcd_to_musb(hcd);
1578 INIT_LIST_HEAD(&musb->control);
1579 INIT_LIST_HEAD(&musb->in_bulk);
1580 INIT_LIST_HEAD(&musb->out_bulk);
1582 hcd->uses_new_polling = 1;
1584 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1586 musb = kzalloc(sizeof *musb, GFP_KERNEL);
1589 dev_set_drvdata(dev, musb);
1593 musb->pRegs = mbase;
1594 musb->ctrl_base = mbase;
1595 musb->nIrq = -ENODEV;
1596 for (epnum = 0, ep = musb->aLocalEnd;
1597 epnum < MUSB_C_NUM_EPS;
1601 ep->bLocalEnd = epnum;
1604 musb->controller = dev;
1608 static void musb_free(struct musb *musb)
1610 /* this has multiple entry modes. it handles fault cleanup after
1611 * probe(), where things may be partially set up, as well as rmmod
1612 * cleanup after everything's been de-activated.
1616 device_remove_file(musb->controller, &dev_attr_mode);
1617 device_remove_file(musb->controller, &dev_attr_cable);
1620 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1621 musb_gadget_cleanup(musb);
1624 if (musb->nIrq >= 0) {
1625 disable_irq_wake(musb->nIrq);
1626 free_irq(musb->nIrq, musb);
1628 if (is_dma_capable() && musb->pDmaController) {
1629 struct dma_controller *c = musb->pDmaController;
1631 (void) c->stop(c->pPrivateData);
1632 dma_controller_factory.destroy(c);
1635 musb_writeb(musb->pRegs, MGC_O_HDRC_DEVCTL, 0);
1636 musb_platform_exit(musb);
1637 musb_writeb(musb->pRegs, MGC_O_HDRC_DEVCTL, 0);
1640 clk_disable(musb->clock);
1641 clk_put(musb->clock);
1644 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1645 usb_put_hcd(musb_to_hcd(musb));
1652 * Perform generic per-controller initialization.
1654 * @pDevice: the controller (already clocked, etc)
1656 * @pRegs: virtual address of controller registers,
1657 * not yet corrected for platform-specific offsets
1659 static int __devinit
1660 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1664 struct musb_hdrc_platform_data *plat = dev->platform_data;
1666 /* The driver might handle more features than the board; OK.
1667 * Fail when the board needs a feature that's not enabled.
1670 dev_dbg(dev, "no platform_data?\n");
1673 switch (plat->mode) {
1675 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1680 case MUSB_PERIPHERAL:
1681 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1687 #ifdef CONFIG_USB_MUSB_OTG
1693 dev_err(dev, "incompatible Kconfig role setting\n");
1698 pThis = allocate_instance(dev, ctrl);
1702 spin_lock_init(&pThis->Lock);
1703 pThis->board_mode = plat->mode;
1704 pThis->board_set_power = plat->set_power;
1705 pThis->min_power = plat->min_power;
1707 /* assume vbus is off */
1709 /* platform adjusts pThis->pRegs and pThis->isr if needed,
1710 * and activates clocks
1712 pThis->isr = generic_interrupt;
1713 status = musb_platform_init(pThis);
1722 #ifndef CONFIG_USB_INVENTRA_FIFO
1723 if (use_dma && dev->dma_mask) {
1724 struct dma_controller *c;
1726 c = dma_controller_factory.create(pThis, pThis->pRegs);
1727 pThis->pDmaController = c;
1729 (void) c->start(c->pPrivateData);
1732 /* ideally this would be abstracted in platform setup */
1733 if (!is_dma_capable() || !pThis->pDmaController)
1734 dev->dma_mask = NULL;
1736 /* be sure interrupts are disabled before connecting ISR */
1737 musb_platform_disable(pThis);
1739 /* setup musb parts of the core (especially endpoints) */
1740 status = musb_core_init(plat->multipoint
1741 ? MUSB_CONTROLLER_MHDRC
1742 : MUSB_CONTROLLER_HDRC, pThis);
1746 /* attach to the IRQ */
1747 if (request_irq (nIrq, pThis->isr, 0, dev->bus_id, pThis)) {
1748 dev_err(dev, "request_irq %d failed!\n", nIrq);
1753 if (enable_irq_wake(nIrq) == 0)
1754 device_init_wakeup(dev, 1);
1756 pr_info("%s: USB %s mode controller at %p using %s, IRQ %d\n",
1759 switch (pThis->board_mode) {
1760 case MUSB_HOST: s = "Host"; break;
1761 case MUSB_PERIPHERAL: s = "Peripheral"; break;
1762 default: s = "OTG"; break;
1765 (is_dma_capable() && pThis->pDmaController)
1769 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1770 /* host side needs more setup, except for no-host modes */
1771 if (pThis->board_mode != MUSB_PERIPHERAL) {
1772 struct usb_hcd *hcd = musb_to_hcd(pThis);
1774 if (pThis->board_mode == MUSB_OTG)
1775 hcd->self.otg_port = 1;
1776 pThis->xceiv.host = &hcd->self;
1777 hcd->power_budget = 2 * (plat->power ? : 250);
1779 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
1781 #ifdef CONFIG_USB_MUSB_OTG
1782 if (!is_otg_enabled(pThis))
1786 /* For the host-only role, we can activate right away.
1787 * (We expect the ID pin to be forcibly grounded!!)
1788 * Otherwise, wait till the gadget driver hooks up.
1790 if (!is_otg_enabled(pThis) && is_host_enabled(pThis)) {
1791 MUSB_HST_MODE(pThis);
1792 pThis->xceiv.default_a = 1;
1793 pThis->xceiv.state = OTG_STATE_A_IDLE;
1795 status = usb_add_hcd(musb_to_hcd(pThis), -1, 0);
1797 DBG(1, "%s mode, status %d, devctl %02x %c\n",
1799 musb_readb(pThis->pRegs, MGC_O_HDRC_DEVCTL),
1800 (musb_readb(pThis->pRegs, MGC_O_HDRC_DEVCTL)
1801 & MGC_M_DEVCTL_BDEVICE
1804 } else /* peripheral is enabled */ {
1805 MUSB_DEV_MODE(pThis);
1806 pThis->xceiv.default_a = 0;
1807 pThis->xceiv.state = OTG_STATE_B_IDLE;
1809 status = musb_gadget_setup(pThis);
1811 DBG(1, "%s mode, status %d, dev%02x\n",
1812 is_otg_enabled(pThis) ? "OTG" : "PERIPHERAL",
1814 musb_readb(pThis->pRegs, MGC_O_HDRC_DEVCTL));
1819 musb_debug_create("driver/musb_hdrc", pThis);
1822 device_init_wakeup(dev, 0);
1827 INIT_WORK(&pThis->irq_work, musb_irq_work, pThis);
1830 status = device_create_file(dev, &dev_attr_mode);
1831 status = device_create_file(dev, &dev_attr_cable);
1838 musb_platform_exit(pThis);
1842 /*-------------------------------------------------------------------------*/
1844 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
1845 * bridge to a platform device; this driver then suffices.
1848 #ifndef CONFIG_USB_INVENTRA_FIFO
1849 static u64 *orig_dma_mask;
1852 static int __devinit musb_probe(struct platform_device *pdev)
1854 struct device *dev = &pdev->dev;
1855 int irq = platform_get_irq(pdev, 0);
1856 struct resource *iomem;
1859 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1860 if (!iomem || irq == 0)
1863 base = ioremap(iomem->start, iomem->end - iomem->start + 1);
1865 dev_err(dev, "ioremap failed\n");
1869 #ifndef CONFIG_USB_INVENTRA_FIFO
1870 /* clobbered by use_dma=n */
1871 orig_dma_mask = dev->dma_mask;
1873 return musb_init_controller(dev, irq, base);
1876 static int __devexit musb_remove(struct platform_device *pdev)
1878 struct musb *musb = dev_to_musb(&pdev->dev);
1879 void __iomem *ctrl_base = musb->ctrl_base;
1881 /* this gets called on rmmod.
1882 * - Host mode: host may still be active
1883 * - Peripheral mode: peripheral is deactivated (or never-activated)
1884 * - OTG mode: both roles are deactivated (or never-activated)
1886 musb_shutdown(pdev);
1887 musb_debug_delete("driver/musb_hdrc", musb);
1888 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1889 if (musb->board_mode == MUSB_HOST)
1890 usb_remove_hcd(musb_to_hcd(musb));
1894 device_init_wakeup(&pdev->dev, 0);
1895 #ifndef CONFIG_USB_INVENTRA_FIFO
1896 pdev->dev.dma_mask = orig_dma_mask;
1903 static int musb_suspend(struct platform_device *pdev, pm_message_t message)
1905 unsigned long flags;
1906 struct musb *musb = dev_to_musb(&pdev->dev);
1911 spin_lock_irqsave(&musb->Lock, flags);
1913 if (is_peripheral_active(musb)) {
1914 /* FIXME force disconnect unless we know USB will wake
1915 * the system up quickly enough to respond ...
1917 } else if (is_host_active(musb)) {
1918 /* we know all the children are suspended; sometimes
1919 * they will even be wakeup-enabled.
1923 clk_disable(musb->clock);
1924 spin_unlock_irqrestore(&musb->Lock, flags);
1928 static int musb_resume(struct platform_device *pdev)
1930 unsigned long flags;
1931 struct musb *musb = dev_to_musb(&pdev->dev);
1936 spin_lock_irqsave(&musb->Lock, flags);
1937 clk_enable(musb->clock);
1938 /* for static cmos like DaVinci, register values were preserved
1939 * unless for some reason the whole soc powered down and we're
1940 * not treating that as a whole-system restart (e.g. swsusp)
1942 spin_unlock_irqrestore(&musb->Lock, flags);
1947 #define musb_suspend NULL
1948 #define musb_resume NULL
1951 static struct platform_driver musb_driver = {
1953 .name = (char *)musb_driver_name,
1954 .bus = &platform_bus_type,
1955 .owner = THIS_MODULE,
1957 .probe = musb_probe,
1958 .remove = __devexit_p(musb_remove),
1959 .shutdown = musb_shutdown,
1960 .suspend = musb_suspend,
1961 .resume = musb_resume,
1964 /*-------------------------------------------------------------------------*/
1966 static int __init musb_init(void)
1968 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1973 pr_info("%s: version " MUSB_VERSION ", "
1974 #ifdef CONFIG_USB_INVENTRA_FIFO
1976 #elif defined(CONFIG_USB_TI_CPPI_DMA)
1978 #elif defined(CONFIG_USB_INVENTRA_DMA)
1980 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
1986 #ifdef CONFIG_USB_MUSB_OTG
1987 "otg (peripheral+host)"
1988 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
1990 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
1994 musb_driver_name, debug);
1995 return platform_driver_register(&musb_driver);
1998 /* make us init after usbcore and before usb
1999 * gadget and host-side drivers start to register
2001 subsys_initcall(musb_init);
2003 static void __exit musb_cleanup(void)
2005 platform_driver_unregister(&musb_driver);
2007 module_exit(musb_cleanup);