1 /*****************************************************************
2 * Copyright 2005 Mentor Graphics Corporation
3 * Copyright (C) 2005-2006 by Texas Instruments
4 * Copyright (C) 2006 by Nokia Corporation
6 * This file is part of the Inventra Controller Driver for Linux.
8 * The Inventra Controller Driver for Linux is free software; you
9 * can redistribute it and/or modify it under the terms of the GNU
10 * General Public License version 2 as published by the Free Software
13 * The Inventra Controller Driver for Linux is distributed in
14 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
15 * without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 * License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with The Inventra Controller Driver for Linux ; if not,
21 * write to the Free Software Foundation, Inc., 59 Temple Place,
22 * Suite 330, Boston, MA 02111-1307 USA
24 * ANY DOWNLOAD, USE, REPRODUCTION, MODIFICATION OR DISTRIBUTION
25 * OF THIS DRIVER INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE
26 * OF THOSE TERMS.THIS DRIVER IS PROVIDED "AS IS" AND MENTOR GRAPHICS
27 * MAKES NO WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THIS DRIVER.
28 * MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES
29 * OF MERCHANTABILITY; FITNESS FOR A PARTICULAR PURPOSE AND
30 * NON-INFRINGEMENT. MENTOR GRAPHICS DOES NOT PROVIDE SUPPORT
31 * SERVICES OR UPDATES FOR THIS DRIVER, EVEN IF YOU ARE A MENTOR
32 * GRAPHICS SUPPORT CUSTOMER.
33 ******************************************************************/
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
81 * - Provides its own OTG bits. These are untested, and many of them
82 * seem to be superfluous code bloat given what usbcore does. (They
83 * have now been partially removed.)
87 * This gets many kinds of configuration information:
88 * - Kconfig for everything user-configurable
89 * - <asm/arch/hdrc_cnf.h> for SOC or family details
90 * - platform_device for addressing, irq, and platform_data
91 * - platform_data is mostly for board-specific informarion
93 * Most of the conditional compilation will (someday) vanish.
96 #include <linux/config.h>
97 #include <linux/module.h>
98 #include <linux/pci.h>
99 #include <linux/kernel.h>
100 #include <linux/sched.h>
101 #include <linux/slab.h>
102 #include <linux/init.h>
103 #include <linux/list.h>
104 #include <linux/kobject.h>
105 #include <linux/platform_device.h>
106 #include <linux/clk.h>
111 #include <asm/arch/hardware.h>
112 #include <asm/arch/memory.h>
113 #include <asm/mach-types.h>
116 #include "musbdefs.h"
117 // #ifdef CONFIG_USB_MUSB_HDRC_HCD
118 #define VBUSERR_RETRY_COUNT 2 /* is this too few? */
122 #ifdef CONFIG_ARCH_DAVINCI
129 unsigned debug = MUSB_DEBUG;
130 module_param(debug, uint, 0);
131 MODULE_PARM_DESC(debug, "initial debug message level");
133 #define MUSB_VERSION_SUFFIX "/dbg"
136 #define DRIVER_AUTHOR "Mentor Graphics Corp. and Texas Instruments"
137 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
139 #define MUSB_VERSION_BASE "2.2a/db-0.5.1"
141 #ifndef MUSB_VERSION_SUFFIX
142 #define MUSB_VERSION_SUFFIX ""
144 #define MUSB_VERSION MUSB_VERSION_BASE MUSB_VERSION_SUFFIX
146 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
148 const char musb_driver_name[] = "musb_hdrc";
150 MODULE_DESCRIPTION(DRIVER_INFO);
151 MODULE_AUTHOR(DRIVER_AUTHOR);
152 MODULE_LICENSE("GPL");
154 /* time (millseconds) to wait before a restart */
155 #define MUSB_RESTART_TIME 5000
157 /* how many babbles to allow before giving up */
158 #define MUSB_MAX_BABBLE_COUNT 10
161 /*-------------------------------------------------------------------------*/
163 #ifdef CONFIG_USB_MUSB_OTG
165 /* For debugging/prototyping: allow disabling host side support on boards
166 * with Mini-AB (or Mini-A) connectors, making peripheral side support look
167 * like pure peripherals (not reporting OTG capabilities, and able to
168 * draw a full 100mA unit load).
172 module_param(musb_otg, bool, 0600);
173 MODULE_PARM_DESC(musb_otg, "enable/disable OTG capabilities");
176 static inline struct musb *dev_to_musb(struct device *dev)
178 #ifdef CONFIG_USB_MUSB_HDRC_HCD
179 /* usbcore insists dev->driver_data is a "struct hcd *" */
180 return hcd_to_musb(dev_get_drvdata(dev));
182 return dev_get_drvdata(dev);
186 static void otg_input_changed(struct musb * pThis, u8 devctl, u8 reset,
187 u8 connection, u8 suspend)
189 #ifdef CONFIG_USB_MUSB_OTG
190 struct otg_machine *otgm = &pThis->OtgMachine;
191 MGC_OtgMachineInputs Inputs;
193 /* reading suspend state from Power register does NOT work */
194 memset(&Inputs, 0, sizeof(Inputs));
196 Inputs.bSession = (devctl & MGC_M_DEVCTL_SESSION) ? TRUE : FALSE;
197 Inputs.bSuspend = suspend;
198 Inputs.bConnection = connection;
199 Inputs.bReset = reset;
200 Inputs.bConnectorId = (devctl & MGC_M_DEVCTL_BDEVICE) ? TRUE : FALSE;
202 MGC_OtgMachineInputsChanged(otgm, &Inputs);
206 static void otg_input_changed_X(struct musb * pThis, u8 bVbusError, u8 bConnect)
208 #ifdef CONFIG_USB_MUSB_OTG
209 MGC_OtgMachineInputs Inputs;
210 void __iomem *pBase = pThis->pRegs;
211 u8 devctl = musb_readb(pBase, MGC_O_HDRC_DEVCTL);
212 u8 power = musb_readb(pBase, MGC_O_HDRC_POWER);
214 DBG(2, "<== power %02x, devctl %02x%s%s\n", power, devctl,
215 bConnect ? ", bcon" : "",
216 bVbusError ? ", vbus_error" : "");
219 memset(&Inputs, 0, sizeof(Inputs));
220 Inputs.bSession = (devctl & MGC_M_DEVCTL_SESSION) ? TRUE : FALSE;
221 Inputs.bConnectorId = (devctl & MGC_M_DEVCTL_BDEVICE) ? TRUE : FALSE;
222 Inputs.bReset = (power & MGC_M_POWER_RESET) ? TRUE : FALSE;
223 Inputs.bConnection = bConnect;
224 Inputs.bVbusError = bVbusError;
225 Inputs.bSuspend = (power & MGC_M_POWER_SUSPENDM) ? TRUE : FALSE;
226 MGC_OtgMachineInputsChanged(&(pThis->OtgMachine), &Inputs);
227 #endif /* CONFIG_USB_MUSB_OTG */
231 /*-------------------------------------------------------------------------*/
233 #ifndef CONFIG_USB_TUSB6010
235 * Load an endpoint's FIFO
237 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 wCount, const u8 *pSource)
239 void __iomem *fifo = hw_ep->fifo;
241 prefetch((u8 *)pSource);
243 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
244 'T', hw_ep->bLocalEnd, fifo, wCount, pSource);
246 /* we can't assume unaligned reads work */
247 if (likely((0x01 & (unsigned long) pSource) == 0)) {
250 /* best case is 32bit-aligned source address */
251 if ((0x02 & (unsigned long) pSource) == 0) {
253 writesl(fifo, pSource + index, wCount >> 2);
254 index += wCount & ~0x03;
257 musb_writew(fifo, 0, *(u16*)&pSource[index]);
262 writesw(fifo, pSource + index, wCount >> 1);
263 index += wCount & ~0x01;
267 musb_writeb(fifo, 0, pSource[index]);
270 writesb(fifo, pSource, wCount);
275 * Unload an endpoint's FIFO
277 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 wCount, u8 *pDest)
279 void __iomem *fifo = hw_ep->fifo;
281 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
282 'R', hw_ep->bLocalEnd, fifo, wCount, pDest);
284 /* we can't assume unaligned writes work */
285 if (likely((0x01 & (unsigned long) pDest) == 0)) {
288 /* best case is 32bit-aligned destination address */
289 if ((0x02 & (unsigned long) pDest) == 0) {
291 readsl(fifo, pDest, wCount >> 2);
292 index = wCount & ~0x03;
295 *(u16*)&pDest[index] = musb_readw(fifo, 0);
300 readsw(fifo, pDest, wCount >> 1);
301 index = wCount & ~0x01;
305 pDest[index] = musb_readb(fifo, 0);
308 readsb(fifo, pDest, wCount);
312 #endif /* normal PIO */
315 /*-------------------------------------------------------------------------*/
317 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
318 static const u8 musb_test_packet[53] = {
319 /* implicit SYNC then DATA0 to start */
322 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
324 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
326 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
327 /* JJJJJJJKKKKKKK x8 */
328 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
330 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
331 /* JKKKKKKK x10, JK */
332 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
334 /* implicit CRC16 then EOP to end */
337 void musb_load_testpacket(struct musb *musb)
339 MGC_SelectEnd(musb->pRegs, 0);
340 musb_write_fifo(musb->control_ep,
341 sizeof(musb_test_packet), musb_test_packet);
342 musb_writew(musb->pRegs, MGC_O_HDRC_CSR0, MGC_M_CSR0_TXPKTRDY);
345 /*-------------------------------------------------------------------------*/
348 * Interrupt Service Routine to record USB "global" interrupts.
349 * Since these do not happen often and signify things of
350 * paramount importance, it seems OK to check them individually;
351 * the order of the tests is specified in the manual
353 * @param pThis instance pointer
354 * @param bIntrUSB register contents
359 #define STAGE0_MASK (MGC_M_INTR_RESUME | MGC_M_INTR_SESSREQ \
360 | MGC_M_INTR_VBUSERROR | MGC_M_INTR_CONNECT \
363 static irqreturn_t musb_stage0_irq(struct musb * pThis, u8 bIntrUSB,
366 irqreturn_t handled = IRQ_NONE;
367 #ifdef CONFIG_USB_MUSB_HDRC_HCD
368 void __iomem *pBase = pThis->pRegs;
371 DBG(3, "<== Power=%02x, DevCtl=%02x, bIntrUSB=0x%x\n", power, devctl,
374 /* in host mode when a device resume me (from power save)
375 * in device mode when the host resume me; it shold not change
378 if (bIntrUSB & MGC_M_INTR_RESUME) {
379 handled = IRQ_HANDLED;
381 pThis->is_active = 1;
383 if (devctl & MGC_M_DEVCTL_HM) {
384 #ifdef CONFIG_USB_MUSB_HDRC_HCD
385 /* REVISIT: this is where SRP kicks in, yes?
386 * host responsibility should be to CLEAR the
387 * resume signaling after 50 msec ...
389 MUSB_HST_MODE(pThis); /* unnecessary */
390 power &= ~MGC_M_POWER_SUSPENDM;
391 musb_writeb(pBase, MGC_O_HDRC_POWER,
392 power | MGC_M_POWER_RESUME);
394 /* should now be A_SUSPEND */
395 pThis->xceiv.state = OTG_STATE_A_HOST;
398 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
399 MUSB_DEV_MODE(pThis); /* unnecessary */
401 musb_g_resume(pThis);
405 #ifdef CONFIG_USB_MUSB_HDRC_HCD
406 /* see manual for the order of the tests */
407 if (bIntrUSB & MGC_M_INTR_SESSREQ) {
408 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(pThis));
410 /* IRQ arrives from ID pin sense or (later, if VBUS power
411 * is removed) SRP. responses are time critical:
412 * - turn on VBUS (with silicon-specific mechanism)
413 * - go through A_WAIT_VRISE
414 * - ... to A_WAIT_BCON.
415 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
417 musb_writeb(pBase, MGC_O_HDRC_DEVCTL, MGC_M_DEVCTL_SESSION);
418 pThis->bEnd0Stage = MGC_END0_START;
419 pThis->xceiv.state = OTG_STATE_A_IDLE;
420 MUSB_HST_MODE(pThis);
421 musb_set_vbus(pThis, 1);
423 handled = IRQ_HANDLED;
425 #ifdef CONFIG_USB_MUSB_OTG
427 MGC_OtgMachineInputs Inputs;
428 memset(&Inputs, 0, sizeof(Inputs));
429 Inputs.bSession = TRUE;
430 Inputs.bConnectorId = FALSE;
431 Inputs.bReset = FALSE;
432 Inputs.bConnection = FALSE;
433 Inputs.bSuspend = FALSE;
434 MGC_OtgMachineInputsChanged(&(pThis->OtgMachine), &Inputs);
439 if (bIntrUSB & MGC_M_INTR_VBUSERROR) {
441 // MGC_OtgMachineInputsChanged(otgm, &Inputs);
442 // otg_input_changed_X(pThis, TRUE, TRUE);
443 // ... may need to abort otg timer ...
445 DBG(1, "VBUS_ERROR (%02x, %s), retry #%d\n", devctl,
447 switch (devctl & MGC_M_DEVCTL_VBUS) {
448 case 0 << MGC_S_DEVCTL_VBUS:
449 s = "<SessEnd"; break;
450 case 1 << MGC_S_DEVCTL_VBUS:
451 s = "<AValid"; break;
452 case 2 << MGC_S_DEVCTL_VBUS:
453 s = "<VBusValid"; break;
454 //case 3 << MGC_S_DEVCTL_VBUS:
458 pThis->vbuserr_retry);
460 /* go through A_WAIT_VFALL then start a new session */
461 musb_set_vbus(pThis, 0);
462 handled = IRQ_HANDLED;
464 pThis->vbuserr_retry = VBUSERR_RETRY_COUNT;
466 if (bIntrUSB & MGC_M_INTR_CONNECT) {
467 handled = IRQ_HANDLED;
468 pThis->is_active = 1;
469 set_bit(HCD_FLAG_SAW_IRQ, &musb_to_hcd(pThis)->flags);
471 pThis->bEnd0Stage = MGC_END0_START;
473 #ifdef CONFIG_USB_MUSB_OTG
474 /* flush endpoints when transitioning from Device Mode */
475 if (is_peripheral_active(pThis)) {
476 // REVISIT HNP; just force disconnect
478 pThis->bDelayPortPowerOff = FALSE;
480 pThis->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
481 |USB_PORT_STAT_HIGH_SPEED
482 |USB_PORT_STAT_ENABLE
484 pThis->port1_status |= USB_PORT_STAT_CONNECTION
485 |(USB_PORT_STAT_C_CONNECTION << 16);
487 /* high vs full speed is just a guess until after reset */
488 if (devctl & MGC_M_DEVCTL_LSDEV)
489 pThis->port1_status |= USB_PORT_STAT_LOW_SPEED;
491 usb_hcd_poll_rh_status(musb_to_hcd(pThis));
493 MUSB_HST_MODE(pThis);
495 /* indicate new connection to OTG machine */
496 switch (pThis->xceiv.state) {
497 case OTG_STATE_B_WAIT_ACON:
498 pThis->xceiv.state = OTG_STATE_B_HOST;
501 pThis->xceiv.state = OTG_STATE_A_HOST;
504 DBG(1, "CONNECT (%s)\n", otg_state_string(pThis));
505 otg_input_changed(pThis, devctl, FALSE, TRUE, FALSE);
507 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
509 /* saved one bit: bus reset and babble share the same bit;
510 * If I am host is a babble! i must be the only one allowed
511 * to reset the bus; when in otg mode it means that I have
512 * to switch to device
514 if (bIntrUSB & MGC_M_INTR_RESET) {
515 if (devctl & MGC_M_DEVCTL_HM) {
518 /* REVISIT it's unclear how to handle this. Mentor's
519 * code stopped the whole USB host, which is clearly
520 * very wrong. Docs say (15.1) that babble ends the
521 * current sesssion, so shutdown _with restart_ would
522 * be appropriate ... except that seems to be wrong,
523 * at least some lowspeed enumerations trigger the
524 * babbles without aborting the session!
526 * (A "babble" IRQ seems quite pointless...)
530 DBG(1, "BUS RESET\n");
534 /* reading state from Power register doesn't work */
535 otg_input_changed(pThis, devctl, TRUE, FALSE,
536 (power & MGC_M_POWER_SUSPENDM)
539 schedule_work(&pThis->irq_work);
542 handled = IRQ_HANDLED;
549 * Interrupt Service Routine to record USB "global" interrupts.
550 * Since these do not happen often and signify things of
551 * paramount importance, it seems OK to check them individually;
552 * the order of the tests is specified in the manual
554 * @param pThis instance pointer
555 * @param bIntrUSB register contents
559 static irqreturn_t musb_stage2_irq(struct musb * pThis, u8 bIntrUSB,
562 irqreturn_t handled = IRQ_NONE;
565 /* REVISIT ... this would be for multiplexing periodic endpoints, or
566 * supporting transfer phasing to prevent exceeding ISO bandwidth
567 * limits of a given frame or microframe.
569 * It's not needed for peripheral side, which dedicates endpoints;
570 * though it _might_ use SOF irqs for other purposes.
572 * And it's not currently needed for host side, which also dedicates
573 * endpoints, relies on TX/RX interval registers, and isn't claimed
574 * to support ISO transfers yet.
576 if (bIntrUSB & MGC_M_INTR_SOF) {
577 void __iomem *pBase = pThis->pRegs;
578 struct musb_hw_ep *ep;
582 DBG(6, "START_OF_FRAME\n");
583 handled = IRQ_HANDLED;
585 /* start any periodic Tx transfers waiting for current frame */
586 wFrame = musb_readw(pBase, MGC_O_HDRC_FRAME);
587 ep = pThis->aLocalEnd;
588 for (bEnd = 1; (bEnd < pThis->bEndCount)
589 && (pThis->wEndMask >= (1 << bEnd));
591 // FIXME handle framecounter wraps (12 bits)
592 // eliminate duplicated StartUrb logic
593 if (ep->dwWaitFrame >= wFrame) {
595 printk("SOF --> periodic TX%s on %d\n",
596 ep->tx_channel ? " DMA" : "",
599 musb_h_tx_start(pThis, bEnd);
601 cppi_hostdma_start(pThis, bEnd);
603 } /* end of for loop */
607 if ((bIntrUSB & MGC_M_INTR_DISCONNECT) && !pThis->bIgnoreDisconnect) {
608 DBG(1, "DISCONNECT as %s, devctl %02x\n",
609 MUSB_MODE(pThis), devctl);
610 handled = IRQ_HANDLED;
611 pThis->is_active = 0;
613 /* need to check it against pThis, because devctl is going
614 * to report ID low as soon as the device gets disconnected
616 if (is_host_active(pThis))
617 musb_root_disconnect(pThis);
619 musb_g_disconnect(pThis);
621 /* REVISIT all OTG state machine transitions */
622 otg_input_changed_X(pThis, FALSE, FALSE);
624 schedule_work(&pThis->irq_work);
627 if (bIntrUSB & MGC_M_INTR_SUSPEND) {
628 DBG(1, "SUSPEND, devctl %02x\n", devctl);
629 handled = IRQ_HANDLED;
631 /* peripheral suspend, may trigger HNP */
632 if (!(devctl & MGC_M_DEVCTL_HM)) {
633 musb_g_suspend(pThis);
634 pThis->is_active = is_otg_enabled(pThis)
635 && pThis->xceiv.gadget->b_hnp_enable;
636 otg_input_changed(pThis, devctl, FALSE, FALSE, TRUE);
638 pThis->is_active = 0;
644 /*-------------------------------------------------------------------------*/
647 * Program the HDRC to start (enable interrupts, dma, etc.).
649 void musb_start(struct musb *musb)
651 void __iomem *regs = musb->pRegs;
652 u8 devctl = musb_readb(regs, MGC_O_HDRC_DEVCTL);
654 DBG(2, "<== devctl %02x\n", devctl);
656 /* Set INT enable registers, enable interrupts */
657 musb_writew(regs, MGC_O_HDRC_INTRTXE, musb->wEndMask);
658 musb_writew(regs, MGC_O_HDRC_INTRRXE, musb->wEndMask & 0xfffe);
659 musb_writeb(regs, MGC_O_HDRC_INTRUSBE, 0xf7);
661 musb_writeb(regs, MGC_O_HDRC_TESTMODE, 0);
663 musb_platform_enable(musb);
665 /* put into basic highspeed mode and start session */
666 musb_writeb(regs, MGC_O_HDRC_POWER, MGC_M_POWER_ISOUPDATE
667 | MGC_M_POWER_SOFTCONN
669 // | MGC_M_POWER_ENSUSPEND
673 devctl = musb_readb(regs, MGC_O_HDRC_DEVCTL);
674 devctl &= ~MGC_M_DEVCTL_SESSION;
676 if (is_otg_enabled(pThis)) {
677 /* session started after:
678 * (a) ID-grounded irq, host mode;
679 * (b) vbus present/connect IRQ, peripheral mode;
680 * (c) peripheral initiates, using SRP
682 if ((devctl & MGC_M_DEVCTL_VBUS) == MGC_M_DEVCTL_VBUS)
685 devctl |= MGC_M_DEVCTL_SESSION;
687 } else if (is_host_enabled(pThis)) {
688 /* assume ID pin is hard-wired to ground */
689 devctl |= MGC_M_DEVCTL_SESSION;
691 } else /* peripheral is enabled */ {
692 if ((devctl & MGC_M_DEVCTL_VBUS) == MGC_M_DEVCTL_VBUS)
695 musb_writeb(regs, MGC_O_HDRC_DEVCTL, devctl);
699 static void musb_generic_disable(struct musb *pThis)
701 void __iomem *pBase = pThis->pRegs;
704 /* disable interrupts */
705 musb_writeb(pBase, MGC_O_HDRC_INTRUSBE, 0);
706 musb_writew(pBase, MGC_O_HDRC_INTRTX, 0);
707 musb_writew(pBase, MGC_O_HDRC_INTRRX, 0);
710 musb_writeb(pBase, MGC_O_HDRC_DEVCTL, 0);
712 /* flush pending interrupts */
713 temp = musb_readb(pBase, MGC_O_HDRC_INTRUSB);
714 temp = musb_readw(pBase, MGC_O_HDRC_INTRTX);
715 temp = musb_readw(pBase, MGC_O_HDRC_INTRRX);
720 * Make the HDRC stop (disable interrupts, etc.);
721 * reversible by musb_start
722 * called on gadget driver unregister
723 * with controller locked, irqs blocked
724 * acts as a NOP unless some role activated the hardware
726 void musb_stop(struct musb * pThis)
728 /* stop IRQs, timers, ... */
729 musb_platform_disable(pThis);
730 musb_generic_disable(pThis);
731 DBG(3, "HDRC disabled\n");
733 #ifdef CONFIG_USB_MUSB_OTG
734 if (is_otg_enabled(pThis))
735 MGC_OtgMachineDestroy(&pThis->OtgMachine);
739 * - mark host and/or peripheral drivers unusable/inactive
740 * - disable DMA (and enable it in HdrcStart)
741 * - make sure we can musb_start() after musb_stop(); with
742 * OTG mode, gadget driver module rmmod/modprobe cycles that
746 #ifdef CONFIG_USB_MUSB_HDRC_HCD
747 if (is_host_enabled(pThis)) {
748 /* REVISIT aren't there some paths where this is wrong? */
749 dev_warn(pThis->controller, "%s, root hub still active\n",
755 static void musb_shutdown(struct platform_device *pdev)
757 struct musb *musb = dev_to_musb(&pdev->dev);
760 spin_lock_irqsave(&musb->Lock, flags);
761 musb_platform_disable(musb);
762 musb_generic_disable(musb);
763 spin_unlock_irqrestore(&musb->Lock, flags);
765 /* FIXME power down */
769 /*-------------------------------------------------------------------------*/
772 * The silicon either has hard-wired endpoint configurations, or else
773 * "dynamic fifo" sizing. The driver has support for both, though at this
774 * writing only the dynamic sizing is very well tested. We use normal
775 * idioms to so both modes are compile-tested, but dead code elimination
776 * leaves only the relevant one in the object file.
778 * We don't currently use dynamic fifo setup capability to do anything
779 * more than selecting one of a bunch of predefined configurations.
781 #ifdef MUSB_C_DYNFIFO_DEF
782 #define can_dynfifo() 1
784 #define can_dynfifo() 0
787 #ifdef CONFIG_USB_TUSB6010
788 static ushort __devinitdata fifo_mode = 4;
790 static ushort __devinitdata fifo_mode = 2;
793 /* "modprobe ... fifo_mode=1" etc */
794 module_param(fifo_mode, ushort, 0);
795 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
798 #define DYN_FIFO_SIZE (1<<(MUSB_C_RAM_BITS+2))
800 enum fifo_style { FIFO_RXTX, FIFO_TX, FIFO_RX } __attribute__ ((packed));
801 enum buf_mode { BUF_SINGLE, BUF_DOUBLE } __attribute__ ((packed));
805 enum fifo_style style;
811 * tables defining fifo_mode values. define more if you like.
812 * for host side, make sure both halves of ep1 are set up.
815 /* mode 0 - fits in 2KB */
816 static const struct fifo_cfg __devinitdata mode_0_cfg[] = {
817 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
818 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
819 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
820 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
821 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
824 /* mode 1 - fits in 4KB */
825 static const struct fifo_cfg __devinitdata mode_1_cfg[] = {
826 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
827 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
828 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
829 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
830 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
833 /* mode 2 - fits in 4KB */
834 static const struct fifo_cfg __devinitdata mode_2_cfg[] = {
835 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
836 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
837 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
838 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
839 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
840 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
843 /* mode 3 - fits in 4KB */
844 static const struct fifo_cfg __devinitdata mode_3_cfg[] = {
845 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
846 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
847 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
848 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
849 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
850 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
853 /* mode 4 - fits in 16KB */
854 static const struct fifo_cfg __devinitdata mode_4_cfg[] = {
855 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
856 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
857 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
858 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
859 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
860 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
861 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
862 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
863 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
864 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
865 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
866 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
867 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
868 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
869 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
870 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
871 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
872 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
873 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 512, },
874 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 512, },
875 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 512, },
876 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 512, },
877 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 512, },
878 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 512, },
879 { .hw_ep_num = 13, .style = FIFO_TX, .maxpacket = 512, },
880 { .hw_ep_num = 13, .style = FIFO_RX, .maxpacket = 512, },
881 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
882 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
887 * configure a fifo; for non-shared endpoints, this may be called
888 * once for a tx fifo and once for an rx fifo.
890 * returns negative errno or offset for next fifo.
893 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
894 const struct fifo_cfg *cfg, u16 offset)
896 void __iomem *mbase = musb->pRegs;
898 u16 maxpacket = cfg->maxpacket;
899 u16 c_off = offset >> 3;
902 /* expect hw_ep has already been zero-initialized */
904 size = ffs(max(maxpacket, (u16) 8)) - 1;
905 maxpacket = 1 << size;
908 if (cfg->mode == BUF_DOUBLE) {
909 if ((offset + (maxpacket << 1)) > DYN_FIFO_SIZE)
911 c_size |= MGC_M_FIFOSZ_DPB;
913 if ((offset + maxpacket) > DYN_FIFO_SIZE)
917 /* configure the FIFO */
918 musb_writeb(mbase, MGC_O_HDRC_INDEX, hw_ep->bLocalEnd);
920 #ifdef CONFIG_USB_MUSB_HDRC_HCD
921 /* EP0 reserved endpoint for control, bidirectional;
922 * EP1 reserved for bulk, two unidirection halves.
924 if (hw_ep->bLocalEnd == 1)
925 musb->bulk_ep = hw_ep;
926 /* REVISIT error check: be sure ep0 can both rx and tx ... */
928 switch (cfg->style) {
930 musb_writeb(mbase, MGC_O_HDRC_TXFIFOSZ, c_size);
931 musb_writew(mbase, MGC_O_HDRC_TXFIFOADD, c_off);
932 hw_ep->tx_double_buffered = !!(c_size & MGC_M_FIFOSZ_DPB);
933 hw_ep->wMaxPacketSizeTx = maxpacket;
936 musb_writeb(mbase, MGC_O_HDRC_RXFIFOSZ, c_size);
937 musb_writew(mbase, MGC_O_HDRC_RXFIFOADD, c_off);
938 hw_ep->rx_double_buffered = !!(c_size & MGC_M_FIFOSZ_DPB);
939 hw_ep->wMaxPacketSizeRx = maxpacket;
942 musb_writeb(mbase, MGC_O_HDRC_TXFIFOSZ, c_size);
943 musb_writew(mbase, MGC_O_HDRC_TXFIFOADD, c_off);
944 hw_ep->rx_double_buffered = !!(c_size & MGC_M_FIFOSZ_DPB);
945 hw_ep->wMaxPacketSizeRx = maxpacket;
947 musb_writeb(mbase, MGC_O_HDRC_RXFIFOSZ, c_size);
948 musb_writew(mbase, MGC_O_HDRC_RXFIFOADD, c_off);
949 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
950 hw_ep->wMaxPacketSizeTx = maxpacket;
952 hw_ep->bIsSharedFifo = TRUE;
956 /* NOTE rx and tx endpoint irqs aren't managed separately,
957 * which happens to be ok
959 musb->wEndMask |= (1 << hw_ep->bLocalEnd);
961 return offset + (maxpacket << ((c_size & MGC_M_FIFOSZ_DPB) ? 1 : 0));
964 static const struct fifo_cfg __devinitdata ep0_cfg = {
965 .style = FIFO_RXTX, .maxpacket = 64,
968 static int __devinit ep_config_from_table(struct musb *musb)
970 const struct fifo_cfg *cfg;
973 struct musb_hw_ep *hw_ep = musb->aLocalEnd;
981 n = ARRAY_SIZE(mode_0_cfg);
985 n = ARRAY_SIZE(mode_1_cfg);
989 n = ARRAY_SIZE(mode_2_cfg);
993 n = ARRAY_SIZE(mode_3_cfg);
997 n = ARRAY_SIZE(mode_4_cfg);
1001 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1002 musb_driver_name, fifo_mode);
1005 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1006 // assert(offset > 0)
1008 for (i = 0; i < n; i++) {
1009 u8 epn = cfg->hw_ep_num;
1011 if (epn >= MUSB_C_NUM_EPS) {
1012 pr_debug( "%s: invalid ep %d\n",
1013 musb_driver_name, epn);
1016 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1018 pr_debug( "%s: mem overrun, ep %d\n",
1019 musb_driver_name, epn);
1023 musb->bEndCount = max(epn, musb->bEndCount);
1026 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1028 n + 1, MUSB_C_NUM_EPS * 2 - 1,
1029 offset, DYN_FIFO_SIZE);
1031 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1032 if (!musb->bulk_ep) {
1033 pr_debug( "%s: missing bulk\n", musb_driver_name);
1043 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1044 * @param pThis the controller
1046 static int __devinit ep_config_from_hw(struct musb *musb)
1049 struct musb_hw_ep *pEnd;
1050 void *pBase = musb->pRegs;
1052 DBG(2, "<== static silicon ep config\n");
1054 /* FIXME pick up ep0 maxpacket size */
1056 for (bEnd = 1; bEnd < MUSB_C_NUM_EPS; bEnd++) {
1057 MGC_SelectEnd(pBase, bEnd);
1058 pEnd = musb->aLocalEnd + bEnd;
1060 /* read from core using indexed model */
1061 reg = musb_readb(pEnd->regs, 0x10 + MGC_O_HDRC_FIFOSIZE);
1063 /* 0's returned when no more endpoints */
1067 musb->wEndMask |= (1 << bEnd);
1069 pEnd->wMaxPacketSizeTx = 1 << (reg & 0x0f);
1071 /* shared TX/RX FIFO? */
1072 if ((reg & 0xf0) == 0xf0) {
1073 pEnd->wMaxPacketSizeRx = pEnd->wMaxPacketSizeTx;
1074 pEnd->bIsSharedFifo = TRUE;
1077 pEnd->wMaxPacketSizeRx = 1 << ((reg & 0xf0) >> 4);
1078 pEnd->bIsSharedFifo = FALSE;
1081 /* FIXME set up pEnd->{rx,tx}_double_buffered */
1083 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1084 /* pick an RX/TX endpoint for bulk */
1085 if (pEnd->wMaxPacketSizeTx < 512
1086 || pEnd->wMaxPacketSizeRx < 512)
1089 /* REVISIT: this algorithm is lazy, we should at least
1090 * try to pick a double buffered endpoint.
1094 musb->bulk_ep = pEnd;
1098 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1099 if (!musb->bulk_ep) {
1100 pr_debug( "%s: missing bulk\n", musb_driver_name);
1108 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1110 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1111 * configure endpoints, or take their config from silicon
1113 static int __devinit musb_core_init(u16 wType, struct musb *pThis)
1120 u16 wRelease, wRelMajor, wRelMinor;
1121 char aInfo[78], aRevision[32], aDate[12];
1122 void __iomem *pBase = pThis->pRegs;
1126 /* log core options (read using indexed model) */
1127 MGC_SelectEnd(pBase, 0);
1128 reg = musb_readb(pBase, 0x10 + MGC_O_HDRC_CONFIGDATA);
1130 strcpy(aInfo, (reg & MGC_M_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1131 if (reg & MGC_M_CONFIGDATA_DYNFIFO) {
1132 strcat(aInfo, ", dyn FIFOs");
1134 if (reg & MGC_M_CONFIGDATA_MPRXE) {
1135 strcat(aInfo, ", bulk combine");
1137 pThis->bBulkCombine = TRUE;
1139 strcat(aInfo, " (X)"); /* no driver support */
1142 if (reg & MGC_M_CONFIGDATA_MPTXE) {
1143 strcat(aInfo, ", bulk split");
1145 pThis->bBulkSplit = TRUE;
1147 strcat(aInfo, " (X)"); /* no driver support */
1150 if (reg & MGC_M_CONFIGDATA_HBRXE) {
1151 strcat(aInfo, ", HB-ISO Rx");
1152 strcat(aInfo, " (X)"); /* no driver support */
1154 if (reg & MGC_M_CONFIGDATA_HBTXE) {
1155 strcat(aInfo, ", HB-ISO Tx");
1156 strcat(aInfo, " (X)"); /* no driver support */
1158 if (reg & MGC_M_CONFIGDATA_SOFTCONE) {
1159 strcat(aInfo, ", SoftConn");
1162 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1163 musb_driver_name, reg, aInfo);
1166 dwData = musb_readl(pBase, 0x404);
1167 sprintf(aDate, "%04d-%02x-%02x", (dwData & 0xffff),
1168 (dwData >> 16) & 0xff, (dwData >> 24) & 0xff);
1169 /* FIXME ID2 and ID3 are unused */
1170 dwData = musb_readl(pBase, 0x408);
1171 printk("ID2=%lx\n", (long unsigned)dwData);
1172 dwData = musb_readl(pBase, 0x40c);
1173 printk("ID3=%lx\n", (long unsigned)dwData);
1174 reg = musb_readb(pBase, 0x400);
1175 wType = ('M' == reg) ? MUSB_CONTROLLER_MHDRC : MUSB_CONTROLLER_HDRC;
1179 if (MUSB_CONTROLLER_MHDRC == wType) {
1180 pThis->bIsMultipoint = 1;
1183 pThis->bIsMultipoint = 0;
1185 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1186 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1188 "%s: kernel must blacklist external hubs\n",
1194 /* log release info */
1195 wRelease = musb_readw(pBase, MGC_O_HDRC_HWVERS);
1196 wRelMajor = (wRelease >> 10) & 0x1f;
1197 wRelMinor = wRelease & 0x3ff;
1198 snprintf(aRevision, 32, "%d.%d%s", wRelMajor,
1199 wRelMinor, (wRelease & 0x8000) ? "RC" : "");
1200 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1201 musb_driver_name, type, aRevision, aDate);
1204 pThis->aLocalEnd[0].wMaxPacketSizeTx = MGC_END0_FIFOSIZE;
1205 pThis->aLocalEnd[0].wMaxPacketSizeRx = MGC_END0_FIFOSIZE;
1207 /* discover endpoint configuration */
1208 pThis->bEndCount = 1;
1209 pThis->wEndMask = 1;
1211 if (reg & MGC_M_CONFIGDATA_DYNFIFO) {
1213 status = ep_config_from_table(pThis);
1215 ERR("reconfigure software for Dynamic FIFOs\n");
1220 status = ep_config_from_hw(pThis);
1222 ERR("reconfigure software for static FIFOs\n");
1230 /* finish init, and print endpoint config */
1231 for (i = 0; i < pThis->bEndCount; i++) {
1232 struct musb_hw_ep *hw_ep = pThis->aLocalEnd + i;
1234 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + pBase;
1235 #ifdef CONFIG_USB_TUSB6010
1236 hw_ep->fifo_async = pThis->async + 0x400 + MUSB_FIFO_OFFSET(i);
1237 hw_ep->fifo_sync = pThis->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1239 hw_ep->conf = pBase - 0x400 + TUSB_EP0_CONF;
1241 hw_ep->conf = pBase + 0x400 + (((i - 1) & 0xf) << 2);
1244 hw_ep->regs = MGC_END_OFFSET(i, 0) + pBase;
1245 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1246 hw_ep->target_regs = MGC_BUSCTL_OFFSET(i, 0) + pBase;
1247 hw_ep->rx_reinit = 1;
1248 hw_ep->tx_reinit = 1;
1251 if (hw_ep->wMaxPacketSizeTx) {
1253 "%s: hw_ep %d%s, %smax %d\n",
1254 musb_driver_name, i,
1255 hw_ep->bIsSharedFifo ? "shared" : "tx",
1256 hw_ep->tx_double_buffered
1257 ? "doublebuffer, " : "",
1258 hw_ep->wMaxPacketSizeTx);
1260 if (hw_ep->wMaxPacketSizeRx && !hw_ep->bIsSharedFifo) {
1262 "%s: hw_ep %d%s, %smax %d\n",
1263 musb_driver_name, i,
1265 hw_ep->rx_double_buffered
1266 ? "doublebuffer, " : "",
1267 hw_ep->wMaxPacketSizeRx);
1269 if (!(hw_ep->wMaxPacketSizeTx || hw_ep->wMaxPacketSizeRx))
1270 DBG(1, "hw_ep %d not configured\n", i);
1276 /*-------------------------------------------------------------------------*/
1278 #ifdef CONFIG_ARCH_OMAP243X
1280 static irqreturn_t generic_interrupt(int irq, void *__hci, struct pt_regs *r)
1282 unsigned long flags;
1283 irqreturn_t retval = IRQ_NONE;
1284 struct musb *musb = __hci;
1286 spin_lock_irqsave(&musb->Lock, flags);
1288 musb->int_usb = musb_readb(musb->pRegs, MGC_O_HDRC_INTRUSB);
1289 musb->int_tx = musb_readw(musb->pRegs, MGC_O_HDRC_INTRTX);
1290 musb->int_rx = musb_readw(musb->pRegs, MGC_O_HDRC_INTRRX);
1293 if (musb->int_usb || musb->int_tx || musb->int_rx)
1294 retval = musb_interrupt(musb);
1296 spin_unlock_irqrestore(&musb->Lock, flags);
1298 /* REVISIT we sometimes get spurious IRQs on g_ep0
1301 if (retval != IRQ_HANDLED)
1302 DBG(5, "spurious?\n");
1308 #define generic_interrupt NULL
1312 * handle all the irqs defined by the HDRC core. for now we expect: other
1313 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1314 * will be assigned, and the irq will already have been acked.
1316 * called in irq context with spinlock held, irqs blocked
1318 irqreturn_t musb_interrupt(struct musb *musb)
1320 irqreturn_t retval = IRQ_NONE;
1325 devctl = musb_readb(musb->pRegs, MGC_O_HDRC_DEVCTL);
1326 power = musb_readb(musb->pRegs, MGC_O_HDRC_POWER);
1328 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
1329 (devctl & MGC_M_DEVCTL_HM) ? "host" : "peripheral",
1330 musb->int_usb, musb->int_tx, musb->int_rx);
1332 /* the core can interrupt us for multiple reasons; docs have
1333 * a generic interrupt flowchart to follow
1335 if (musb->int_usb & STAGE0_MASK)
1336 retval |= musb_stage0_irq(musb, musb->int_usb,
1339 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1341 /* "stage 1" is handling endpoint irqs */
1343 /* handle endpoint 0 first */
1344 if (musb->int_tx & 1) {
1345 if (devctl & MGC_M_DEVCTL_HM)
1346 retval |= musb_h_ep0_irq(musb);
1348 retval |= musb_g_ep0_irq(musb);
1351 /* RX on endpoints 1-15 */
1352 reg = musb->int_rx >> 1;
1356 // MGC_SelectEnd(musb->pRegs, ep_num);
1357 /* REVISIT just retval = ep->rx_irq(...) */
1358 retval = IRQ_HANDLED;
1359 if (devctl & MGC_M_DEVCTL_HM) {
1360 if (is_host_capable())
1361 musb_host_rx(musb, ep_num);
1363 if (is_peripheral_capable())
1364 musb_g_rx(musb, ep_num);
1372 /* TX on endpoints 1-15 */
1373 reg = musb->int_tx >> 1;
1377 // MGC_SelectEnd(musb->pRegs, ep_num);
1378 /* REVISIT just retval |= ep->tx_irq(...) */
1379 retval = IRQ_HANDLED;
1380 if (devctl & MGC_M_DEVCTL_HM) {
1381 if (is_host_capable())
1382 musb_host_tx(musb, ep_num);
1384 if (is_peripheral_capable())
1385 musb_g_tx(musb, ep_num);
1392 /* finish handling "global" interrupts after handling fifos */
1394 retval |= musb_stage2_irq(musb,
1395 musb->int_usb, devctl, power);
1401 #ifndef CONFIG_USB_INVENTRA_FIFO
1402 static int __devinitdata use_dma = is_dma_capable();
1404 /* "modprobe ... use_dma=0" etc */
1405 module_param(use_dma, bool, 0);
1406 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1408 void musb_dma_completion(struct musb *musb, u8 bLocalEnd, u8 bTransmit)
1410 u8 devctl = musb_readb(musb->pRegs, MGC_O_HDRC_DEVCTL);
1412 /* called with controller lock already held */
1415 #if !(defined(CONFIG_USB_TI_CPPI_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA))
1417 if (devctl & MGC_M_DEVCTL_HM)
1418 musb_h_ep0_irq(musb);
1420 musb_g_ep0_irq(musb);
1423 /* endpoints 1..15 */
1425 if (devctl & MGC_M_DEVCTL_HM) {
1426 if (is_host_capable())
1427 musb_host_tx(musb, bLocalEnd);
1429 if (is_peripheral_capable())
1430 musb_g_tx(musb, bLocalEnd);
1434 if (devctl & MGC_M_DEVCTL_HM) {
1435 if (is_host_capable())
1436 musb_host_rx(musb, bLocalEnd);
1438 if (is_peripheral_capable())
1439 musb_g_rx(musb, bLocalEnd);
1446 #define use_dma is_dma_capable()
1449 /*-------------------------------------------------------------------------*/
1454 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1456 struct musb *musb = dev_to_musb(dev);
1457 unsigned long flags;
1460 spin_lock_irqsave(&musb->Lock, flags);
1461 switch (musb->board_mode) {
1463 ret = sprintf(buf, "host\n");
1465 case MUSB_PERIPHERAL:
1466 ret = sprintf(buf, "peripheral\n");
1469 ret = sprintf(buf, "otg\n");
1472 spin_unlock_irqrestore(&musb->Lock, flags);
1476 static DEVICE_ATTR(mode, S_IRUGO, musb_mode_show, NULL);
1479 musb_cable_show(struct device *dev, struct device_attribute *attr, char *buf)
1481 struct musb *musb = dev_to_musb(dev);
1482 char *v1= "", *v2 = "?";
1483 unsigned long flags;
1486 spin_lock_irqsave(&musb->Lock, flags);
1487 #ifdef CONFIG_USB_TUSB6010
1488 /* REVISIT: connect-A != connect-B ... */
1489 vbus = musb_platform_get_vbus_status(musb);
1493 v2 = "disconnected";
1495 /* NOTE: board-specific issues, like too-big capacitors keeping
1496 * VBUS high for a long time after power has been removed, can
1497 * cause temporary false indications of a connection.
1499 vbus = musb_readb(musb->pRegs, MGC_O_HDRC_DEVCTL);
1501 /* REVISIT retest on real OTG hardware */
1502 switch (musb->board_mode) {
1506 case MUSB_PERIPHERAL:
1511 v2 = (vbus & MGC_M_DEVCTL_BDEVICE) ? "B" : "A";
1514 } else /* VBUS level below A-Valid */
1515 v2 = "disconnected";
1517 musb_platform_try_idle(musb);
1518 spin_unlock_irqrestore(&musb->Lock, flags);
1520 return sprintf(buf, "%s%s\n", v1, v2);
1522 static DEVICE_ATTR(cable, S_IRUGO, musb_cable_show, NULL);
1526 /* Only used to provide cable state change events */
1527 static void musb_irq_work(void *data)
1529 struct musb *musb = (struct musb *)data;
1531 sysfs_notify(&musb->controller->kobj, NULL, "cable");
1534 /* --------------------------------------------------------------------------
1538 static struct musb *__devinit
1539 allocate_instance(struct device *dev, void __iomem *mbase)
1542 struct musb_hw_ep *ep;
1544 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1545 struct usb_hcd *hcd;
1547 hcd = usb_create_hcd(&musb_hc_driver, dev, dev->bus_id);
1550 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1552 musb = hcd_to_musb(hcd);
1553 INIT_LIST_HEAD(&musb->control);
1554 INIT_LIST_HEAD(&musb->in_bulk);
1555 INIT_LIST_HEAD(&musb->out_bulk);
1557 hcd->uses_new_polling = 1;
1559 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1561 musb = kzalloc(sizeof *musb, GFP_KERNEL);
1564 dev_set_drvdata(dev, musb);
1568 musb->pRegs = mbase;
1569 musb->ctrl_base = mbase;
1570 musb->nIrq = -ENODEV;
1571 for (epnum = 0, ep = musb->aLocalEnd;
1572 epnum < MUSB_C_NUM_EPS;
1576 ep->bLocalEnd = epnum;
1579 musb->controller = dev;
1583 static void musb_free(struct musb *musb)
1585 /* this has multiple entry modes. it handles fault cleanup after
1586 * probe(), where things may be partially set up, as well as rmmod
1587 * cleanup after everything's been de-activated.
1591 device_remove_file(musb->controller, &dev_attr_mode);
1592 device_remove_file(musb->controller, &dev_attr_cable);
1595 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1596 musb_gadget_cleanup(musb);
1599 if (musb->nIrq >= 0) {
1600 disable_irq_wake(musb->nIrq);
1601 free_irq(musb->nIrq, musb);
1603 if (is_dma_capable() && musb->pDmaController) {
1604 struct dma_controller *c = musb->pDmaController;
1607 (void) c->stop(c->pPrivateData);
1608 dma_controller_factory.destroy(c);
1611 musb_writeb(musb->pRegs, MGC_O_HDRC_DEVCTL, 0);
1612 musb_platform_exit(musb);
1613 musb_writeb(musb->pRegs, MGC_O_HDRC_DEVCTL, 0);
1616 clk_disable(musb->clock);
1617 clk_put(musb->clock);
1620 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1621 usb_put_hcd(musb_to_hcd(musb));
1628 * Perform generic per-controller initialization.
1630 * @pDevice: the controller (already clocked, etc)
1632 * @pRegs: virtual address of controller registers,
1633 * not yet corrected for platform-specific offsets
1635 static int __devinit
1636 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1640 struct musb_hdrc_platform_data *plat = dev->platform_data;
1642 /* The driver might handle more features than the board; OK.
1643 * Fail when the board needs a feature that's not enabled.
1646 dev_dbg(dev, "no platform_data?\n");
1649 switch (plat->mode) {
1651 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1656 case MUSB_PERIPHERAL:
1657 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1663 #ifdef CONFIG_USB_MUSB_OTG
1669 dev_dbg(dev, "incompatible Kconfig role setting\n");
1674 pThis = allocate_instance(dev, ctrl);
1678 spin_lock_init(&pThis->Lock);
1679 pThis->board_mode = plat->mode;
1680 pThis->board_set_power = plat->set_power;
1681 pThis->min_power = plat->min_power;
1683 /* assume vbus is off */
1685 /* platform adjusts pThis->pRegs and pThis->isr if needed,
1686 * and activates clocks
1688 pThis->isr = generic_interrupt;
1689 status = musb_platform_init(pThis);
1698 #ifndef CONFIG_USB_INVENTRA_FIFO
1699 if (use_dma && dev->dma_mask) {
1700 struct dma_controller *c;
1702 c = dma_controller_factory.create(pThis, pThis->pRegs);
1703 pThis->pDmaController = c;
1705 (void) c->start(c->pPrivateData);
1708 /* ideally this would be abstracted in platform setup */
1709 if (!is_dma_capable() || !pThis->pDmaController)
1710 dev->dma_mask = NULL;
1712 /* be sure interrupts are disabled before connecting ISR */
1713 musb_platform_disable(pThis);
1715 /* setup musb parts of the core (especially endpoints) */
1716 status = musb_core_init(plat->multipoint
1717 ? MUSB_CONTROLLER_MHDRC
1718 : MUSB_CONTROLLER_HDRC, pThis);
1722 /* attach to the IRQ */
1723 if (request_irq (nIrq, pThis->isr, 0, dev->bus_id, pThis)) {
1724 dev_err(dev, "request_irq %d failed!\n", nIrq);
1728 (void) enable_irq_wake(nIrq);
1730 device_init_wakeup(dev, 1);
1732 pr_info("%s: USB %s mode controller at %p using %s, IRQ %d\n",
1735 switch (pThis->board_mode) {
1736 case MUSB_HOST: s = "Host"; break;
1737 case MUSB_PERIPHERAL: s = "Peripheral"; break;
1738 default: s = "OTG"; break;
1741 (is_dma_capable() && pThis->pDmaController)
1745 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1746 /* host side needs more setup, except for no-host modes */
1747 if (pThis->board_mode != MUSB_PERIPHERAL) {
1748 struct usb_hcd *hcd = musb_to_hcd(pThis);
1750 if (pThis->board_mode == MUSB_OTG)
1751 hcd->self.otg_port = 1;
1752 pThis->xceiv.host = &hcd->self;
1753 hcd->power_budget = 2 * (plat->power ? : 250);
1755 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
1757 #ifdef CONFIG_USB_MUSB_OTG
1758 /* if present, this gets used even on non-otg boards */
1759 MGC_OtgMachineInit(&pThis->OtgMachine, pThis);
1762 /* For the host-only role, we can activate right away.
1763 * (We expect the ID pin to be forcibly grounded!!)
1764 * Otherwise, wait till the gadget driver hooks up.
1766 pThis->xceiv.state = OTG_STATE_B_IDLE;
1767 pThis->xceiv.default_a = 0;
1769 if (is_otg_enabled(pThis)) {
1770 MUSB_OTG_MODE(pThis);
1771 status = musb_gadget_setup(pThis);
1773 DBG(1, "%s mode, status %d, dev%02x\n",
1775 musb_readb(pThis->pRegs, MGC_O_HDRC_DEVCTL));
1777 } else if (is_host_enabled(pThis)) {
1778 MUSB_HST_MODE(pThis);
1779 pThis->xceiv.default_a = 1;
1780 pThis->xceiv.state = OTG_STATE_A_IDLE;
1782 status = usb_add_hcd(musb_to_hcd(pThis), -1, 0);
1784 DBG(1, "%s mode, status %d, devctl %02x %c\n",
1786 musb_readb(pThis->pRegs, MGC_O_HDRC_DEVCTL),
1787 (musb_readb(pThis->pRegs, MGC_O_HDRC_DEVCTL)
1788 & MGC_M_DEVCTL_BDEVICE
1791 } else /* peripheral is enabled */ {
1792 MUSB_DEV_MODE(pThis);
1793 status = musb_gadget_setup(pThis);
1795 DBG(1, "%s mode, status %d, dev%02x\n",
1796 "PERIPHERAL", status,
1797 musb_readb(pThis->pRegs, MGC_O_HDRC_DEVCTL));
1802 musb_debug_create("driver/musb_hdrc", pThis);
1805 device_init_wakeup(dev, 0);
1810 INIT_WORK(&pThis->irq_work, musb_irq_work, pThis);
1813 device_create_file(dev, &dev_attr_mode);
1814 device_create_file(dev, &dev_attr_cable);
1820 musb_platform_exit(pThis);
1824 /*-------------------------------------------------------------------------*/
1826 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
1827 * bridge to a platform device; this driver then suffices.
1830 static int __devinit musb_probe(struct platform_device *pdev)
1832 struct device *dev = &pdev->dev;
1833 int irq = platform_get_irq(pdev, 0);
1834 struct resource *iomem;
1837 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1838 if (!iomem || irq == 0)
1841 base = ioremap(iomem->start, iomem->end - iomem->start + 1);
1843 dev_err(dev, "ioremap failed\n");
1847 return musb_init_controller(dev, irq, base);
1850 static int __devexit musb_remove(struct platform_device *pdev)
1852 struct musb *musb = dev_to_musb(&pdev->dev);
1854 /* this gets called on rmmod.
1855 * - Host mode: host may still be active
1856 * - Peripheral mode: peripheral is deactivated (or never-activated)
1857 * - OTG mode: both roles are deactivated (or never-activated)
1859 musb_shutdown(pdev);
1860 musb_debug_delete("driver/musb_hdrc", musb);
1861 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1862 if (musb->board_mode == MUSB_HOST)
1863 usb_remove_hcd(musb_to_hcd(musb));
1866 device_init_wakeup(&pdev->dev, 0);
1872 static int musb_suspend(struct platform_device *pdev, pm_message_t message)
1874 unsigned long flags;
1875 struct musb *musb = dev_to_musb(&pdev->dev);
1880 spin_lock_irqsave(&musb->Lock, flags);
1882 if (is_peripheral_active(musb)) {
1883 /* FIXME force disconnect unless we know USB will wake
1884 * the system up quickly enough to respond ...
1886 } else if (is_host_active(musb)) {
1887 /* we know all the children are suspended; sometimes
1888 * they will even be wakeup-enabled.
1892 clk_disable(musb->clock);
1893 spin_unlock_irqrestore(&musb->Lock, flags);
1897 static int musb_resume(struct platform_device *pdev)
1899 unsigned long flags;
1900 struct musb *musb = dev_to_musb(&pdev->dev);
1905 spin_lock_irqsave(&musb->Lock, flags);
1906 clk_enable(musb->clock);
1907 /* for static cmos like DaVinci, register values were preserved
1908 * unless for some reason the whole soc powered down and we're
1909 * not treating that as a whole-system restart (e.g. swsusp)
1911 spin_unlock_irqrestore(&musb->Lock, flags);
1916 #define musb_suspend NULL
1917 #define musb_resume NULL
1920 static struct platform_driver musb_driver = {
1922 .name = (char *)musb_driver_name,
1923 .bus = &platform_bus_type,
1924 .owner = THIS_MODULE,
1926 .probe = musb_probe,
1927 .remove = __devexit_p(musb_remove),
1928 .shutdown = musb_shutdown,
1929 .suspend = musb_suspend,
1930 .resume = musb_resume,
1933 /*-------------------------------------------------------------------------*/
1935 static int __init musb_init(void)
1937 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1942 pr_info("%s: version " MUSB_VERSION ", "
1943 #ifdef CONFIG_USB_INVENTRA_FIFO
1945 #elif defined(CONFIG_USB_TI_CPPI_DMA)
1947 #elif defined(CONFIG_USB_INVENTRA_DMA)
1949 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
1955 #ifdef CONFIG_USB_MUSB_OTG
1956 "otg (peripheral+host)"
1957 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
1959 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
1963 musb_driver_name, debug);
1964 return platform_driver_register(&musb_driver);
1967 /* make us init after usbcore and before usb
1968 * gadget and host-side drivers start to register
1970 subsys_initcall(musb_init);
1972 static void __exit musb_cleanup(void)
1974 platform_driver_unregister(&musb_driver);
1976 module_exit(musb_cleanup);