1 /*****************************************************************
2 * Copyright 2005 Mentor Graphics Corporation
3 * Copyright (C) 2005-2006 by Texas Instruments
4 * Copyright (C) 2006 by Nokia Corporation
6 * This file is part of the Inventra Controller Driver for Linux.
8 * The Inventra Controller Driver for Linux is free software; you
9 * can redistribute it and/or modify it under the terms of the GNU
10 * General Public License version 2 as published by the Free Software
13 * The Inventra Controller Driver for Linux is distributed in
14 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
15 * without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 * License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with The Inventra Controller Driver for Linux ; if not,
21 * write to the Free Software Foundation, Inc., 59 Temple Place,
22 * Suite 330, Boston, MA 02111-1307 USA
24 * ANY DOWNLOAD, USE, REPRODUCTION, MODIFICATION OR DISTRIBUTION
25 * OF THIS DRIVER INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE
26 * OF THOSE TERMS.THIS DRIVER IS PROVIDED "AS IS" AND MENTOR GRAPHICS
27 * MAKES NO WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THIS DRIVER.
28 * MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES
29 * OF MERCHANTABILITY; FITNESS FOR A PARTICULAR PURPOSE AND
30 * NON-INFRINGEMENT. MENTOR GRAPHICS DOES NOT PROVIDE SUPPORT
31 * SERVICES OR UPDATES FOR THIS DRIVER, EVEN IF YOU ARE A MENTOR
32 * GRAPHICS SUPPORT CUSTOMER.
33 ******************************************************************/
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - <asm/arch/hdrc_cnf.h> for SOC or family details
86 * - platform_device for addressing, irq, and platform_data
87 * - platform_data is mostly for board-specific informarion
89 * Most of the conditional compilation will (someday) vanish.
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/platform_device.h>
104 #include <asm/arch/hardware.h>
105 #include <asm/arch/memory.h>
106 #include <asm/mach-types.h>
109 #include "musbdefs.h"
112 #ifdef CONFIG_ARCH_DAVINCI
119 unsigned debug = MUSB_DEBUG;
120 module_param(debug, uint, 0);
121 MODULE_PARM_DESC(debug, "initial debug message level");
123 #define MUSB_VERSION_SUFFIX "/dbg"
126 const char *otg_state_string(struct musb *musb)
130 snprintf(buf, sizeof buf, "otg-%d", musb->xceiv.state);
135 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
136 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
138 #define MUSB_VERSION_BASE "2.2a/db-0.5.2"
140 #ifndef MUSB_VERSION_SUFFIX
141 #define MUSB_VERSION_SUFFIX ""
143 #define MUSB_VERSION MUSB_VERSION_BASE MUSB_VERSION_SUFFIX
145 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
147 const char musb_driver_name[] = "musb_hdrc";
149 MODULE_DESCRIPTION(DRIVER_INFO);
150 MODULE_AUTHOR(DRIVER_AUTHOR);
151 MODULE_LICENSE("GPL");
154 /*-------------------------------------------------------------------------*/
156 static inline struct musb *dev_to_musb(struct device *dev)
158 #ifdef CONFIG_USB_MUSB_HDRC_HCD
159 /* usbcore insists dev->driver_data is a "struct hcd *" */
160 return hcd_to_musb(dev_get_drvdata(dev));
162 return dev_get_drvdata(dev);
166 /*-------------------------------------------------------------------------*/
168 #ifndef CONFIG_USB_TUSB6010
170 * Load an endpoint's FIFO
172 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 wCount, const u8 *pSource)
174 void __iomem *fifo = hw_ep->fifo;
176 prefetch((u8 *)pSource);
178 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
179 'T', hw_ep->bLocalEnd, fifo, wCount, pSource);
181 /* we can't assume unaligned reads work */
182 if (likely((0x01 & (unsigned long) pSource) == 0)) {
185 /* best case is 32bit-aligned source address */
186 if ((0x02 & (unsigned long) pSource) == 0) {
188 writesl(fifo, pSource + index, wCount >> 2);
189 index += wCount & ~0x03;
192 musb_writew(fifo, 0, *(u16*)&pSource[index]);
197 writesw(fifo, pSource + index, wCount >> 1);
198 index += wCount & ~0x01;
202 musb_writeb(fifo, 0, pSource[index]);
205 writesb(fifo, pSource, wCount);
210 * Unload an endpoint's FIFO
212 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 wCount, u8 *pDest)
214 void __iomem *fifo = hw_ep->fifo;
216 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
217 'R', hw_ep->bLocalEnd, fifo, wCount, pDest);
219 /* we can't assume unaligned writes work */
220 if (likely((0x01 & (unsigned long) pDest) == 0)) {
223 /* best case is 32bit-aligned destination address */
224 if ((0x02 & (unsigned long) pDest) == 0) {
226 readsl(fifo, pDest, wCount >> 2);
227 index = wCount & ~0x03;
230 *(u16*)&pDest[index] = musb_readw(fifo, 0);
235 readsw(fifo, pDest, wCount >> 1);
236 index = wCount & ~0x01;
240 pDest[index] = musb_readb(fifo, 0);
243 readsb(fifo, pDest, wCount);
247 #endif /* normal PIO */
250 /*-------------------------------------------------------------------------*/
252 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
253 static const u8 musb_test_packet[53] = {
254 /* implicit SYNC then DATA0 to start */
257 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
259 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
261 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
262 /* JJJJJJJKKKKKKK x8 */
263 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
265 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
266 /* JKKKKKKK x10, JK */
267 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
269 /* implicit CRC16 then EOP to end */
272 void musb_load_testpacket(struct musb *musb)
274 void __iomem *regs = musb->aLocalEnd[0].regs;
276 MGC_SelectEnd(musb->pRegs, 0);
277 musb_write_fifo(musb->control_ep,
278 sizeof(musb_test_packet), musb_test_packet);
279 musb_writew(regs, MGC_O_HDRC_CSR0, MGC_M_CSR0_TXPKTRDY);
282 /*-------------------------------------------------------------------------*/
285 * Interrupt Service Routine to record USB "global" interrupts.
286 * Since these do not happen often and signify things of
287 * paramount importance, it seems OK to check them individually;
288 * the order of the tests is specified in the manual
290 * @param pThis instance pointer
291 * @param bIntrUSB register contents
296 #define STAGE0_MASK (MGC_M_INTR_RESUME | MGC_M_INTR_SESSREQ \
297 | MGC_M_INTR_VBUSERROR | MGC_M_INTR_CONNECT \
300 static irqreturn_t musb_stage0_irq(struct musb * pThis, u8 bIntrUSB,
303 irqreturn_t handled = IRQ_NONE;
304 #ifdef CONFIG_USB_MUSB_HDRC_HCD
305 void __iomem *pBase = pThis->pRegs;
308 DBG(3, "<== Power=%02x, DevCtl=%02x, bIntrUSB=0x%x\n", power, devctl,
311 /* in host mode, the peripheral may issue remote wakeup.
312 * in peripheral mode, the host may resume the link.
313 * spurious RESUME irqs happen too, paired with SUSPEND.
315 if (bIntrUSB & MGC_M_INTR_RESUME) {
316 handled = IRQ_HANDLED;
317 DBG(3, "RESUME (%s)\n", otg_state_string(pThis));
319 if (devctl & MGC_M_DEVCTL_HM) {
320 #ifdef CONFIG_USB_MUSB_HDRC_HCD
321 switch (pThis->xceiv.state) {
322 case OTG_STATE_A_SUSPEND:
323 /* remote wakeup? later, GetPortStatus
324 * will stop RESUME signaling
326 if (power & MGC_M_POWER_RESUME) {
327 power &= ~MGC_M_POWER_SUSPENDM;
328 musb_writeb(pBase, MGC_O_HDRC_POWER,
329 power | MGC_M_POWER_RESUME);
331 pThis->port1_status |=
332 (USB_PORT_STAT_C_SUSPEND << 16)
333 | MUSB_PORT_STAT_RESUME;
334 pThis->rh_timer = jiffies
335 + msecs_to_jiffies(20);
337 pThis->xceiv.state = OTG_STATE_A_HOST;
338 pThis->is_active = 1;
339 usb_hcd_resume_root_hub(
342 } else if (power & MGC_M_POWER_SUSPENDM) {
344 pThis->int_usb &= ~MGC_M_INTR_SUSPEND;
347 case OTG_STATE_B_WAIT_ACON:
348 pThis->xceiv.state = OTG_STATE_B_PERIPHERAL;
349 pThis->is_active = 1;
350 MUSB_DEV_MODE(pThis);
353 WARN("bogus %s RESUME (%s)\n",
355 otg_state_string(pThis));
359 switch (pThis->xceiv.state) {
360 #ifdef CONFIG_USB_MUSB_HDRC_HCD
361 case OTG_STATE_A_SUSPEND:
362 /* possibly DISCONNECT is upcoming */
363 pThis->xceiv.state = OTG_STATE_A_HOST;
364 usb_hcd_resume_root_hub(musb_to_hcd(pThis));
367 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
368 case OTG_STATE_B_WAIT_ACON:
369 case OTG_STATE_B_PERIPHERAL:
370 /* disconnect while suspended? we may
371 * not get a disconnect irq...
373 if ((devctl & MGC_M_DEVCTL_VBUS)
374 != (3 << MGC_S_DEVCTL_VBUS)) {
375 pThis->int_usb |= MGC_M_INTR_DISCONNECT;
376 pThis->int_usb &= ~MGC_M_INTR_SUSPEND;
379 musb_g_resume(pThis);
381 case OTG_STATE_B_IDLE:
382 pThis->int_usb &= ~MGC_M_INTR_SUSPEND;
386 WARN("bogus %s RESUME (%s)\n",
388 otg_state_string(pThis));
393 #ifdef CONFIG_USB_MUSB_HDRC_HCD
394 /* see manual for the order of the tests */
395 if (bIntrUSB & MGC_M_INTR_SESSREQ) {
396 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(pThis));
398 /* IRQ arrives from ID pin sense or (later, if VBUS power
399 * is removed) SRP. responses are time critical:
400 * - turn on VBUS (with silicon-specific mechanism)
401 * - go through A_WAIT_VRISE
402 * - ... to A_WAIT_BCON.
403 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
405 musb_writeb(pBase, MGC_O_HDRC_DEVCTL, MGC_M_DEVCTL_SESSION);
406 pThis->bEnd0Stage = MGC_END0_START;
407 pThis->xceiv.state = OTG_STATE_A_IDLE;
408 MUSB_HST_MODE(pThis);
409 musb_set_vbus(pThis, 1);
411 handled = IRQ_HANDLED;
414 if (bIntrUSB & MGC_M_INTR_VBUSERROR) {
417 /* During connection as an A-Device, we may see a short
418 * current spikes causing voltage drop, because of cable
419 * and peripheral capacitance combined with vbus draw.
420 * (So: less common with truly self-powered devices, where
421 * vbus doesn't act like a power supply.)
423 * Such spikes are short; usually less than ~500 usec, max
424 * of ~2 msec. That is, they're not sustained overcurrent
425 * errors, though they're reported using VBUSERROR irqs.
427 * Workarounds: (a) hardware: use self powered devices.
428 * (b) software: ignore non-repeated VBUS errors.
430 * REVISIT: do delays from lots of DEBUG_KERNEL checks
431 * make trouble here, keeping VBUS < 4.4V ?
433 switch (pThis->xceiv.state) {
434 case OTG_STATE_A_HOST:
435 /* recovery is dicey once we've gotten past the
436 * initial stages of enumeration, but if VBUS
437 * stayed ok at the other end of the link, and
438 * another reset is due (at least for high speed,
439 * to redo the chirp etc), it might work OK...
441 case OTG_STATE_A_WAIT_BCON:
442 case OTG_STATE_A_WAIT_VRISE:
443 if (pThis->vbuserr_retry) {
444 pThis->vbuserr_retry--;
446 devctl |= MGC_M_DEVCTL_SESSION;
447 musb_writeb(pBase, MGC_O_HDRC_DEVCTL, devctl);
449 pThis->port1_status |=
450 (1 << USB_PORT_FEAT_OVER_CURRENT)
451 | (1 << USB_PORT_FEAT_C_OVER_CURRENT);
458 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
459 otg_state_string(pThis),
462 switch (devctl & MGC_M_DEVCTL_VBUS) {
463 case 0 << MGC_S_DEVCTL_VBUS:
464 s = "<SessEnd"; break;
465 case 1 << MGC_S_DEVCTL_VBUS:
466 s = "<AValid"; break;
467 case 2 << MGC_S_DEVCTL_VBUS:
468 s = "<VBusValid"; break;
469 //case 3 << MGC_S_DEVCTL_VBUS:
473 VBUSERR_RETRY_COUNT - pThis->vbuserr_retry,
474 pThis->port1_status);
476 /* go through A_WAIT_VFALL then start a new session */
478 musb_set_vbus(pThis, 0);
479 handled = IRQ_HANDLED;
482 if (bIntrUSB & MGC_M_INTR_CONNECT) {
483 struct usb_hcd *hcd = musb_to_hcd(pThis);
485 handled = IRQ_HANDLED;
486 pThis->is_active = 1;
487 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
489 pThis->bEnd0Stage = MGC_END0_START;
491 #ifdef CONFIG_USB_MUSB_OTG
492 /* flush endpoints when transitioning from Device Mode */
493 if (is_peripheral_active(pThis)) {
494 // REVISIT HNP; just force disconnect
496 pThis->bDelayPortPowerOff = FALSE;
498 pThis->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
499 |USB_PORT_STAT_HIGH_SPEED
500 |USB_PORT_STAT_ENABLE
502 pThis->port1_status |= USB_PORT_STAT_CONNECTION
503 |(USB_PORT_STAT_C_CONNECTION << 16);
505 /* high vs full speed is just a guess until after reset */
506 if (devctl & MGC_M_DEVCTL_LSDEV)
507 pThis->port1_status |= USB_PORT_STAT_LOW_SPEED;
510 usb_hcd_poll_rh_status(hcd);
512 usb_hcd_resume_root_hub(hcd);
514 MUSB_HST_MODE(pThis);
516 /* indicate new connection to OTG machine */
517 switch (pThis->xceiv.state) {
518 case OTG_STATE_B_WAIT_ACON:
519 pThis->xceiv.state = OTG_STATE_B_HOST;
522 if ((devctl & MGC_M_DEVCTL_VBUS)
523 == (3 << MGC_S_DEVCTL_VBUS))
524 pThis->xceiv.state = OTG_STATE_A_HOST;
527 DBG(1, "CONNECT (%s) devctl %02x\n",
528 otg_state_string(pThis), devctl);
530 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
532 /* mentor saves a bit: bus reset and babble share the same irq.
533 * only host sees babble; only peripheral sees bus reset.
535 if (bIntrUSB & MGC_M_INTR_RESET) {
536 if (devctl & MGC_M_DEVCTL_HM) {
539 /* REVISIT it's unclear how to handle this. Mentor's
540 * code stopped the whole USB host, which is clearly
541 * very wrong. Docs say (15.1) that babble ends the
542 * current sesssion, so shutdown _with restart_ would
543 * be appropriate ... except that seems to be wrong,
544 * at least some lowspeed enumerations trigger the
545 * babbles without aborting the session!
547 * (A "babble" IRQ seems quite pointless...)
551 DBG(1, "BUS RESET\n");
554 schedule_work(&pThis->irq_work);
557 handled = IRQ_HANDLED;
564 * Interrupt Service Routine to record USB "global" interrupts.
565 * Since these do not happen often and signify things of
566 * paramount importance, it seems OK to check them individually;
567 * the order of the tests is specified in the manual
569 * @param pThis instance pointer
570 * @param bIntrUSB register contents
574 static irqreturn_t musb_stage2_irq(struct musb * pThis, u8 bIntrUSB,
577 irqreturn_t handled = IRQ_NONE;
580 /* REVISIT ... this would be for multiplexing periodic endpoints, or
581 * supporting transfer phasing to prevent exceeding ISO bandwidth
582 * limits of a given frame or microframe.
584 * It's not needed for peripheral side, which dedicates endpoints;
585 * though it _might_ use SOF irqs for other purposes.
587 * And it's not currently needed for host side, which also dedicates
588 * endpoints, relies on TX/RX interval registers, and isn't claimed
589 * to support ISO transfers yet.
591 if (bIntrUSB & MGC_M_INTR_SOF) {
592 void __iomem *pBase = pThis->pRegs;
593 struct musb_hw_ep *ep;
597 DBG(6, "START_OF_FRAME\n");
598 handled = IRQ_HANDLED;
600 /* start any periodic Tx transfers waiting for current frame */
601 wFrame = musb_readw(pBase, MGC_O_HDRC_FRAME);
602 ep = pThis->aLocalEnd;
603 for (bEnd = 1; (bEnd < pThis->bEndCount)
604 && (pThis->wEndMask >= (1 << bEnd));
606 // FIXME handle framecounter wraps (12 bits)
607 // eliminate duplicated StartUrb logic
608 if (ep->dwWaitFrame >= wFrame) {
610 printk("SOF --> periodic TX%s on %d\n",
611 ep->tx_channel ? " DMA" : "",
614 musb_h_tx_start(pThis, bEnd);
616 cppi_hostdma_start(pThis, bEnd);
618 } /* end of for loop */
622 if ((bIntrUSB & MGC_M_INTR_DISCONNECT) && !pThis->bIgnoreDisconnect) {
623 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
624 otg_state_string(pThis),
625 MUSB_MODE(pThis), devctl);
626 handled = IRQ_HANDLED;
628 switch (pThis->xceiv.state) {
629 #ifdef CONFIG_USB_MUSB_HDRC_HCD
630 case OTG_STATE_A_HOST:
631 case OTG_STATE_A_SUSPEND:
632 musb_root_disconnect(pThis);
635 #ifdef CONFIG_USB_MUSB_OTG
636 case OTG_STATE_A_PERIPHERAL:
637 case OTG_STATE_B_HOST:
638 musb_root_disconnect(pThis);
640 case OTG_STATE_B_WAIT_ACON:
642 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
643 case OTG_STATE_B_PERIPHERAL:
644 musb_g_disconnect(pThis);
648 WARN("unhandled DISCONNECT transition (%s)\n",
649 otg_state_string(pThis));
653 schedule_work(&pThis->irq_work);
656 if (bIntrUSB & MGC_M_INTR_SUSPEND) {
657 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
658 otg_state_string(pThis), devctl, power);
659 handled = IRQ_HANDLED;
661 switch (pThis->xceiv.state) {
662 case OTG_STATE_B_PERIPHERAL:
663 musb_g_suspend(pThis);
664 pThis->is_active = is_otg_enabled(pThis)
665 && pThis->xceiv.gadget->b_hnp_enable;
666 if (pThis->is_active) {
667 pThis->xceiv.state = OTG_STATE_B_WAIT_ACON;
668 /* REVISIT timeout for b_ase0_brst, etc */
671 case OTG_STATE_A_HOST:
672 pThis->xceiv.state = OTG_STATE_A_SUSPEND;
673 pThis->is_active = is_otg_enabled(pThis)
674 && pThis->xceiv.host->b_hnp_enable;
677 /* "should not happen" */
678 pThis->is_active = 0;
687 /*-------------------------------------------------------------------------*/
690 * Program the HDRC to start (enable interrupts, dma, etc.).
692 void musb_start(struct musb *musb)
694 void __iomem *regs = musb->pRegs;
695 u8 devctl = musb_readb(regs, MGC_O_HDRC_DEVCTL);
697 DBG(2, "<== devctl %02x\n", devctl);
699 /* Set INT enable registers, enable interrupts */
700 musb_writew(regs, MGC_O_HDRC_INTRTXE, musb->wEndMask);
701 musb_writew(regs, MGC_O_HDRC_INTRRXE, musb->wEndMask & 0xfffe);
702 musb_writeb(regs, MGC_O_HDRC_INTRUSBE, 0xf7);
704 musb_writeb(regs, MGC_O_HDRC_TESTMODE, 0);
706 /* put into basic highspeed mode and start session */
707 musb_writeb(regs, MGC_O_HDRC_POWER, MGC_M_POWER_ISOUPDATE
708 | MGC_M_POWER_SOFTCONN
710 /* ENSUSPEND wedges tusb */
711 // | MGC_M_POWER_ENSUSPEND
715 devctl = musb_readb(regs, MGC_O_HDRC_DEVCTL);
716 devctl &= ~MGC_M_DEVCTL_SESSION;
718 if (is_otg_enabled(musb)) {
719 /* session started after:
720 * (a) ID-grounded irq, host mode;
721 * (b) vbus present/connect IRQ, peripheral mode;
722 * (c) peripheral initiates, using SRP
724 if ((devctl & MGC_M_DEVCTL_VBUS) == MGC_M_DEVCTL_VBUS)
727 devctl |= MGC_M_DEVCTL_SESSION;
729 } else if (is_host_enabled(musb)) {
730 /* assume ID pin is hard-wired to ground */
731 devctl |= MGC_M_DEVCTL_SESSION;
733 } else /* peripheral is enabled */ {
734 if ((devctl & MGC_M_DEVCTL_VBUS) == MGC_M_DEVCTL_VBUS)
737 musb_platform_enable(musb);
738 musb_writeb(regs, MGC_O_HDRC_DEVCTL, devctl);
742 static void musb_generic_disable(struct musb *pThis)
744 void __iomem *pBase = pThis->pRegs;
747 /* disable interrupts */
748 musb_writeb(pBase, MGC_O_HDRC_INTRUSBE, 0);
749 musb_writew(pBase, MGC_O_HDRC_INTRTX, 0);
750 musb_writew(pBase, MGC_O_HDRC_INTRRX, 0);
753 musb_writeb(pBase, MGC_O_HDRC_DEVCTL, 0);
755 /* flush pending interrupts */
756 temp = musb_readb(pBase, MGC_O_HDRC_INTRUSB);
757 temp = musb_readw(pBase, MGC_O_HDRC_INTRTX);
758 temp = musb_readw(pBase, MGC_O_HDRC_INTRRX);
763 * Make the HDRC stop (disable interrupts, etc.);
764 * reversible by musb_start
765 * called on gadget driver unregister
766 * with controller locked, irqs blocked
767 * acts as a NOP unless some role activated the hardware
769 void musb_stop(struct musb *musb)
771 /* stop IRQs, timers, ... */
772 musb_platform_disable(musb);
773 musb_generic_disable(musb);
774 DBG(3, "HDRC disabled\n");
777 * - mark host and/or peripheral drivers unusable/inactive
778 * - disable DMA (and enable it in HdrcStart)
779 * - make sure we can musb_start() after musb_stop(); with
780 * OTG mode, gadget driver module rmmod/modprobe cycles that
783 musb_platform_try_idle(musb);
786 static void musb_shutdown(struct platform_device *pdev)
788 struct musb *musb = dev_to_musb(&pdev->dev);
791 spin_lock_irqsave(&musb->Lock, flags);
792 musb_platform_disable(musb);
793 musb_generic_disable(musb);
795 clk_put(musb->clock);
798 spin_unlock_irqrestore(&musb->Lock, flags);
800 /* FIXME power down */
804 /*-------------------------------------------------------------------------*/
807 * The silicon either has hard-wired endpoint configurations, or else
808 * "dynamic fifo" sizing. The driver has support for both, though at this
809 * writing only the dynamic sizing is very well tested. We use normal
810 * idioms to so both modes are compile-tested, but dead code elimination
811 * leaves only the relevant one in the object file.
813 * We don't currently use dynamic fifo setup capability to do anything
814 * more than selecting one of a bunch of predefined configurations.
816 #ifdef MUSB_C_DYNFIFO_DEF
817 #define can_dynfifo() 1
819 #define can_dynfifo() 0
822 #ifdef CONFIG_USB_TUSB6010
823 static ushort __initdata fifo_mode = 4;
825 static ushort __initdata fifo_mode = 2;
828 /* "modprobe ... fifo_mode=1" etc */
829 module_param(fifo_mode, ushort, 0);
830 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
833 #define DYN_FIFO_SIZE (1<<(MUSB_C_RAM_BITS+2))
835 enum fifo_style { FIFO_RXTX, FIFO_TX, FIFO_RX } __attribute__ ((packed));
836 enum buf_mode { BUF_SINGLE, BUF_DOUBLE } __attribute__ ((packed));
840 enum fifo_style style;
846 * tables defining fifo_mode values. define more if you like.
847 * for host side, make sure both halves of ep1 are set up.
850 /* mode 0 - fits in 2KB */
851 static struct fifo_cfg __initdata mode_0_cfg[] = {
852 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
853 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
854 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
855 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
856 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
859 /* mode 1 - fits in 4KB */
860 static struct fifo_cfg __initdata mode_1_cfg[] = {
861 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
862 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
863 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
864 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
865 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
868 /* mode 2 - fits in 4KB */
869 static struct fifo_cfg __initdata mode_2_cfg[] = {
870 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
871 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
872 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
873 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
874 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
875 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
878 /* mode 3 - fits in 4KB */
879 static struct fifo_cfg __initdata mode_3_cfg[] = {
880 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
881 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
882 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
883 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
884 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
885 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
888 /* mode 4 - fits in 16KB */
889 static struct fifo_cfg __initdata mode_4_cfg[] = {
890 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
891 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
892 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
893 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
894 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
895 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
896 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
897 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
898 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
899 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
900 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
901 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
902 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
903 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
904 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
905 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
906 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
907 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
908 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 512, },
909 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 512, },
910 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 512, },
911 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 512, },
912 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 512, },
913 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 512, },
914 { .hw_ep_num = 13, .style = FIFO_TX, .maxpacket = 512, },
915 { .hw_ep_num = 13, .style = FIFO_RX, .maxpacket = 512, },
916 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
917 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
922 * configure a fifo; for non-shared endpoints, this may be called
923 * once for a tx fifo and once for an rx fifo.
925 * returns negative errno or offset for next fifo.
928 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
929 const struct fifo_cfg *cfg, u16 offset)
931 void __iomem *mbase = musb->pRegs;
933 u16 maxpacket = cfg->maxpacket;
934 u16 c_off = offset >> 3;
937 /* expect hw_ep has already been zero-initialized */
939 size = ffs(max(maxpacket, (u16) 8)) - 1;
940 maxpacket = 1 << size;
943 if (cfg->mode == BUF_DOUBLE) {
944 if ((offset + (maxpacket << 1)) > DYN_FIFO_SIZE)
946 c_size |= MGC_M_FIFOSZ_DPB;
948 if ((offset + maxpacket) > DYN_FIFO_SIZE)
952 /* configure the FIFO */
953 musb_writeb(mbase, MGC_O_HDRC_INDEX, hw_ep->bLocalEnd);
955 #ifdef CONFIG_USB_MUSB_HDRC_HCD
956 /* EP0 reserved endpoint for control, bidirectional;
957 * EP1 reserved for bulk, two unidirection halves.
959 if (hw_ep->bLocalEnd == 1)
960 musb->bulk_ep = hw_ep;
961 /* REVISIT error check: be sure ep0 can both rx and tx ... */
963 switch (cfg->style) {
965 musb_writeb(mbase, MGC_O_HDRC_TXFIFOSZ, c_size);
966 musb_writew(mbase, MGC_O_HDRC_TXFIFOADD, c_off);
967 hw_ep->tx_double_buffered = !!(c_size & MGC_M_FIFOSZ_DPB);
968 hw_ep->wMaxPacketSizeTx = maxpacket;
971 musb_writeb(mbase, MGC_O_HDRC_RXFIFOSZ, c_size);
972 musb_writew(mbase, MGC_O_HDRC_RXFIFOADD, c_off);
973 hw_ep->rx_double_buffered = !!(c_size & MGC_M_FIFOSZ_DPB);
974 hw_ep->wMaxPacketSizeRx = maxpacket;
977 musb_writeb(mbase, MGC_O_HDRC_TXFIFOSZ, c_size);
978 musb_writew(mbase, MGC_O_HDRC_TXFIFOADD, c_off);
979 hw_ep->rx_double_buffered = !!(c_size & MGC_M_FIFOSZ_DPB);
980 hw_ep->wMaxPacketSizeRx = maxpacket;
982 musb_writeb(mbase, MGC_O_HDRC_RXFIFOSZ, c_size);
983 musb_writew(mbase, MGC_O_HDRC_RXFIFOADD, c_off);
984 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
985 hw_ep->wMaxPacketSizeTx = maxpacket;
987 hw_ep->bIsSharedFifo = TRUE;
991 /* NOTE rx and tx endpoint irqs aren't managed separately,
992 * which happens to be ok
994 musb->wEndMask |= (1 << hw_ep->bLocalEnd);
996 return offset + (maxpacket << ((c_size & MGC_M_FIFOSZ_DPB) ? 1 : 0));
999 static struct fifo_cfg __initdata ep0_cfg = {
1000 .style = FIFO_RXTX, .maxpacket = 64,
1003 static int __init ep_config_from_table(struct musb *musb)
1005 const struct fifo_cfg *cfg;
1008 struct musb_hw_ep *hw_ep = musb->aLocalEnd;
1010 switch (fifo_mode) {
1016 n = ARRAY_SIZE(mode_0_cfg);
1020 n = ARRAY_SIZE(mode_1_cfg);
1024 n = ARRAY_SIZE(mode_2_cfg);
1028 n = ARRAY_SIZE(mode_3_cfg);
1032 n = ARRAY_SIZE(mode_4_cfg);
1036 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1037 musb_driver_name, fifo_mode);
1040 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1041 // assert(offset > 0)
1043 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1044 * be better than static MUSB_C_NUM_EPS and DYN_FIFO_SIZE...
1047 for (i = 0; i < n; i++) {
1048 u8 epn = cfg->hw_ep_num;
1050 if (epn >= MUSB_C_NUM_EPS) {
1051 pr_debug( "%s: invalid ep %d\n",
1052 musb_driver_name, epn);
1055 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1057 pr_debug( "%s: mem overrun, ep %d\n",
1058 musb_driver_name, epn);
1062 musb->bEndCount = max(epn, musb->bEndCount);
1065 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1067 n + 1, MUSB_C_NUM_EPS * 2 - 1,
1068 offset, DYN_FIFO_SIZE);
1070 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1071 if (!musb->bulk_ep) {
1072 pr_debug( "%s: missing bulk\n", musb_driver_name);
1082 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1083 * @param pThis the controller
1085 static int __init ep_config_from_hw(struct musb *musb)
1088 struct musb_hw_ep *pEnd;
1089 void *pBase = musb->pRegs;
1091 DBG(2, "<== static silicon ep config\n");
1093 /* FIXME pick up ep0 maxpacket size */
1095 for (bEnd = 1; bEnd < MUSB_C_NUM_EPS; bEnd++) {
1096 MGC_SelectEnd(pBase, bEnd);
1097 pEnd = musb->aLocalEnd + bEnd;
1099 /* read from core using indexed model */
1100 reg = musb_readb(pEnd->regs, 0x10 + MGC_O_HDRC_FIFOSIZE);
1102 /* 0's returned when no more endpoints */
1106 musb->wEndMask |= (1 << bEnd);
1108 pEnd->wMaxPacketSizeTx = 1 << (reg & 0x0f);
1110 /* shared TX/RX FIFO? */
1111 if ((reg & 0xf0) == 0xf0) {
1112 pEnd->wMaxPacketSizeRx = pEnd->wMaxPacketSizeTx;
1113 pEnd->bIsSharedFifo = TRUE;
1116 pEnd->wMaxPacketSizeRx = 1 << ((reg & 0xf0) >> 4);
1117 pEnd->bIsSharedFifo = FALSE;
1120 /* FIXME set up pEnd->{rx,tx}_double_buffered */
1122 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1123 /* pick an RX/TX endpoint for bulk */
1124 if (pEnd->wMaxPacketSizeTx < 512
1125 || pEnd->wMaxPacketSizeRx < 512)
1128 /* REVISIT: this algorithm is lazy, we should at least
1129 * try to pick a double buffered endpoint.
1133 musb->bulk_ep = pEnd;
1137 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1138 if (!musb->bulk_ep) {
1139 pr_debug( "%s: missing bulk\n", musb_driver_name);
1147 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1149 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1150 * configure endpoints, or take their config from silicon
1152 static int __init musb_core_init(u16 wType, struct musb *pThis)
1159 u16 wRelease, wRelMajor, wRelMinor;
1160 char aInfo[78], aRevision[32], aDate[12];
1161 void __iomem *pBase = pThis->pRegs;
1165 /* log core options (read using indexed model) */
1166 MGC_SelectEnd(pBase, 0);
1167 reg = musb_readb(pBase, 0x10 + MGC_O_HDRC_CONFIGDATA);
1169 strcpy(aInfo, (reg & MGC_M_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1170 if (reg & MGC_M_CONFIGDATA_DYNFIFO) {
1171 strcat(aInfo, ", dyn FIFOs");
1173 if (reg & MGC_M_CONFIGDATA_MPRXE) {
1174 strcat(aInfo, ", bulk combine");
1176 pThis->bBulkCombine = TRUE;
1178 strcat(aInfo, " (X)"); /* no driver support */
1181 if (reg & MGC_M_CONFIGDATA_MPTXE) {
1182 strcat(aInfo, ", bulk split");
1184 pThis->bBulkSplit = TRUE;
1186 strcat(aInfo, " (X)"); /* no driver support */
1189 if (reg & MGC_M_CONFIGDATA_HBRXE) {
1190 strcat(aInfo, ", HB-ISO Rx");
1191 strcat(aInfo, " (X)"); /* no driver support */
1193 if (reg & MGC_M_CONFIGDATA_HBTXE) {
1194 strcat(aInfo, ", HB-ISO Tx");
1195 strcat(aInfo, " (X)"); /* no driver support */
1197 if (reg & MGC_M_CONFIGDATA_SOFTCONE) {
1198 strcat(aInfo, ", SoftConn");
1201 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1202 musb_driver_name, reg, aInfo);
1205 dwData = musb_readl(pBase, 0x404);
1206 sprintf(aDate, "%04d-%02x-%02x", (dwData & 0xffff),
1207 (dwData >> 16) & 0xff, (dwData >> 24) & 0xff);
1208 /* FIXME ID2 and ID3 are unused */
1209 dwData = musb_readl(pBase, 0x408);
1210 printk("ID2=%lx\n", (long unsigned)dwData);
1211 dwData = musb_readl(pBase, 0x40c);
1212 printk("ID3=%lx\n", (long unsigned)dwData);
1213 reg = musb_readb(pBase, 0x400);
1214 wType = ('M' == reg) ? MUSB_CONTROLLER_MHDRC : MUSB_CONTROLLER_HDRC;
1218 if (MUSB_CONTROLLER_MHDRC == wType) {
1219 pThis->bIsMultipoint = 1;
1222 pThis->bIsMultipoint = 0;
1224 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1225 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1227 "%s: kernel must blacklist external hubs\n",
1233 /* log release info */
1234 wRelease = musb_readw(pBase, MGC_O_HDRC_HWVERS);
1235 wRelMajor = (wRelease >> 10) & 0x1f;
1236 wRelMinor = wRelease & 0x3ff;
1237 snprintf(aRevision, 32, "%d.%d%s", wRelMajor,
1238 wRelMinor, (wRelease & 0x8000) ? "RC" : "");
1239 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1240 musb_driver_name, type, aRevision, aDate);
1243 pThis->aLocalEnd[0].wMaxPacketSizeTx = MGC_END0_FIFOSIZE;
1244 pThis->aLocalEnd[0].wMaxPacketSizeRx = MGC_END0_FIFOSIZE;
1246 /* discover endpoint configuration */
1247 pThis->bEndCount = 1;
1248 pThis->wEndMask = 1;
1250 if (reg & MGC_M_CONFIGDATA_DYNFIFO) {
1252 status = ep_config_from_table(pThis);
1254 ERR("reconfigure software for Dynamic FIFOs\n");
1259 status = ep_config_from_hw(pThis);
1261 ERR("reconfigure software for static FIFOs\n");
1269 /* finish init, and print endpoint config */
1270 for (i = 0; i < pThis->bEndCount; i++) {
1271 struct musb_hw_ep *hw_ep = pThis->aLocalEnd + i;
1273 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + pBase;
1274 #ifdef CONFIG_USB_TUSB6010
1275 hw_ep->fifo_async = pThis->async + 0x400 + MUSB_FIFO_OFFSET(i);
1276 hw_ep->fifo_sync = pThis->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1278 hw_ep->conf = pBase - 0x400 + TUSB_EP0_CONF;
1280 hw_ep->conf = pBase + 0x400 + (((i - 1) & 0xf) << 2);
1283 hw_ep->regs = MGC_END_OFFSET(i, 0) + pBase;
1284 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1285 hw_ep->target_regs = MGC_BUSCTL_OFFSET(i, 0) + pBase;
1286 hw_ep->rx_reinit = 1;
1287 hw_ep->tx_reinit = 1;
1290 if (hw_ep->wMaxPacketSizeTx) {
1292 "%s: hw_ep %d%s, %smax %d\n",
1293 musb_driver_name, i,
1294 hw_ep->bIsSharedFifo ? "shared" : "tx",
1295 hw_ep->tx_double_buffered
1296 ? "doublebuffer, " : "",
1297 hw_ep->wMaxPacketSizeTx);
1299 if (hw_ep->wMaxPacketSizeRx && !hw_ep->bIsSharedFifo) {
1301 "%s: hw_ep %d%s, %smax %d\n",
1302 musb_driver_name, i,
1304 hw_ep->rx_double_buffered
1305 ? "doublebuffer, " : "",
1306 hw_ep->wMaxPacketSizeRx);
1308 if (!(hw_ep->wMaxPacketSizeTx || hw_ep->wMaxPacketSizeRx))
1309 DBG(1, "hw_ep %d not configured\n", i);
1315 /*-------------------------------------------------------------------------*/
1317 #ifdef CONFIG_ARCH_OMAP243X
1319 static irqreturn_t generic_interrupt(int irq, void *__hci)
1321 unsigned long flags;
1322 irqreturn_t retval = IRQ_NONE;
1323 struct musb *musb = __hci;
1325 spin_lock_irqsave(&musb->Lock, flags);
1327 musb->int_usb = musb_readb(musb->pRegs, MGC_O_HDRC_INTRUSB);
1328 musb->int_tx = musb_readw(musb->pRegs, MGC_O_HDRC_INTRTX);
1329 musb->int_rx = musb_readw(musb->pRegs, MGC_O_HDRC_INTRRX);
1331 if (musb->int_usb || musb->int_tx || musb->int_rx)
1332 retval = musb_interrupt(musb);
1334 spin_unlock_irqrestore(&musb->Lock, flags);
1336 /* REVISIT we sometimes get spurious IRQs on g_ep0
1339 if (retval != IRQ_HANDLED)
1340 DBG(5, "spurious?\n");
1346 #define generic_interrupt NULL
1350 * handle all the irqs defined by the HDRC core. for now we expect: other
1351 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1352 * will be assigned, and the irq will already have been acked.
1354 * called in irq context with spinlock held, irqs blocked
1356 irqreturn_t musb_interrupt(struct musb *musb)
1358 irqreturn_t retval = IRQ_NONE;
1363 devctl = musb_readb(musb->pRegs, MGC_O_HDRC_DEVCTL);
1364 power = musb_readb(musb->pRegs, MGC_O_HDRC_POWER);
1366 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
1367 (devctl & MGC_M_DEVCTL_HM) ? "host" : "peripheral",
1368 musb->int_usb, musb->int_tx, musb->int_rx);
1370 /* the core can interrupt us for multiple reasons; docs have
1371 * a generic interrupt flowchart to follow
1373 if (musb->int_usb & STAGE0_MASK)
1374 retval |= musb_stage0_irq(musb, musb->int_usb,
1377 /* "stage 1" is handling endpoint irqs */
1379 /* handle endpoint 0 first */
1380 if (musb->int_tx & 1) {
1381 if (devctl & MGC_M_DEVCTL_HM)
1382 retval |= musb_h_ep0_irq(musb);
1384 retval |= musb_g_ep0_irq(musb);
1387 /* RX on endpoints 1-15 */
1388 reg = musb->int_rx >> 1;
1392 // MGC_SelectEnd(musb->pRegs, ep_num);
1393 /* REVISIT just retval = ep->rx_irq(...) */
1394 retval = IRQ_HANDLED;
1395 if (devctl & MGC_M_DEVCTL_HM) {
1396 if (is_host_capable())
1397 musb_host_rx(musb, ep_num);
1399 if (is_peripheral_capable())
1400 musb_g_rx(musb, ep_num);
1408 /* TX on endpoints 1-15 */
1409 reg = musb->int_tx >> 1;
1413 // MGC_SelectEnd(musb->pRegs, ep_num);
1414 /* REVISIT just retval |= ep->tx_irq(...) */
1415 retval = IRQ_HANDLED;
1416 if (devctl & MGC_M_DEVCTL_HM) {
1417 if (is_host_capable())
1418 musb_host_tx(musb, ep_num);
1420 if (is_peripheral_capable())
1421 musb_g_tx(musb, ep_num);
1428 /* finish handling "global" interrupts after handling fifos */
1430 retval |= musb_stage2_irq(musb,
1431 musb->int_usb, devctl, power);
1437 #ifndef CONFIG_USB_INVENTRA_FIFO
1438 static int __initdata use_dma = 1;
1440 /* "modprobe ... use_dma=0" etc */
1441 module_param(use_dma, bool, 0);
1442 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1444 void musb_dma_completion(struct musb *musb, u8 bLocalEnd, u8 bTransmit)
1446 u8 devctl = musb_readb(musb->pRegs, MGC_O_HDRC_DEVCTL);
1448 /* called with controller lock already held */
1451 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1452 if (!is_cppi_enabled()) {
1454 if (devctl & MGC_M_DEVCTL_HM)
1455 musb_h_ep0_irq(musb);
1457 musb_g_ep0_irq(musb);
1461 /* endpoints 1..15 */
1463 if (devctl & MGC_M_DEVCTL_HM) {
1464 if (is_host_capable())
1465 musb_host_tx(musb, bLocalEnd);
1467 if (is_peripheral_capable())
1468 musb_g_tx(musb, bLocalEnd);
1472 if (devctl & MGC_M_DEVCTL_HM) {
1473 if (is_host_capable())
1474 musb_host_rx(musb, bLocalEnd);
1476 if (is_peripheral_capable())
1477 musb_g_rx(musb, bLocalEnd);
1487 /*-------------------------------------------------------------------------*/
1492 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1494 struct musb *musb = dev_to_musb(dev);
1495 unsigned long flags;
1498 spin_lock_irqsave(&musb->Lock, flags);
1499 switch (musb->board_mode) {
1501 ret = sprintf(buf, "host\n");
1503 case MUSB_PERIPHERAL:
1504 ret = sprintf(buf, "peripheral\n");
1507 ret = sprintf(buf, "otg\n");
1510 spin_unlock_irqrestore(&musb->Lock, flags);
1514 static DEVICE_ATTR(mode, S_IRUGO, musb_mode_show, NULL);
1517 musb_cable_show(struct device *dev, struct device_attribute *attr, char *buf)
1519 struct musb *musb = dev_to_musb(dev);
1520 char *v1= "", *v2 = "?";
1521 unsigned long flags;
1524 spin_lock_irqsave(&musb->Lock, flags);
1525 #if defined(CONFIG_USB_TUSB6010) && !defined(CONFIG_USB_MUSB_OTG)
1526 /* REVISIT: connect-A != connect-B ... */
1527 vbus = musb_platform_get_vbus_status(musb);
1531 v2 = "disconnected";
1533 /* NOTE: board-specific issues, like too-big capacitors keeping
1534 * VBUS high for a long time after power has been removed, can
1535 * cause temporary false indications of a connection.
1537 vbus = musb_readb(musb->pRegs, MGC_O_HDRC_DEVCTL);
1539 /* REVISIT retest on real OTG hardware */
1540 switch (musb->board_mode) {
1544 case MUSB_PERIPHERAL:
1549 v2 = (vbus & MGC_M_DEVCTL_BDEVICE) ? "B" : "A";
1552 } else /* VBUS level below A-Valid */
1553 v2 = "disconnected";
1555 musb_platform_try_idle(musb);
1556 spin_unlock_irqrestore(&musb->Lock, flags);
1558 return sprintf(buf, "%s%s\n", v1, v2);
1560 static DEVICE_ATTR(cable, S_IRUGO, musb_cable_show, NULL);
1564 /* Only used to provide cable state change events */
1565 static void musb_irq_work(struct work_struct *data)
1567 struct musb *musb = container_of(data, struct musb, irq_work);
1569 sysfs_notify(&musb->controller->kobj, NULL, "cable");
1572 /* --------------------------------------------------------------------------
1576 static struct musb *__init
1577 allocate_instance(struct device *dev, void __iomem *mbase)
1580 struct musb_hw_ep *ep;
1582 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1583 struct usb_hcd *hcd;
1585 hcd = usb_create_hcd(&musb_hc_driver, dev, dev->bus_id);
1588 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1590 musb = hcd_to_musb(hcd);
1591 INIT_LIST_HEAD(&musb->control);
1592 INIT_LIST_HEAD(&musb->in_bulk);
1593 INIT_LIST_HEAD(&musb->out_bulk);
1595 hcd->uses_new_polling = 1;
1597 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1599 musb = kzalloc(sizeof *musb, GFP_KERNEL);
1602 dev_set_drvdata(dev, musb);
1606 musb->pRegs = mbase;
1607 musb->ctrl_base = mbase;
1608 musb->nIrq = -ENODEV;
1609 for (epnum = 0, ep = musb->aLocalEnd;
1610 epnum < MUSB_C_NUM_EPS;
1614 ep->bLocalEnd = epnum;
1617 musb->controller = dev;
1621 static void musb_free(struct musb *musb)
1623 /* this has multiple entry modes. it handles fault cleanup after
1624 * probe(), where things may be partially set up, as well as rmmod
1625 * cleanup after everything's been de-activated.
1629 device_remove_file(musb->controller, &dev_attr_mode);
1630 device_remove_file(musb->controller, &dev_attr_cable);
1633 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1634 musb_gadget_cleanup(musb);
1637 if (musb->nIrq >= 0) {
1638 disable_irq_wake(musb->nIrq);
1639 free_irq(musb->nIrq, musb);
1641 if (is_dma_capable() && musb->pDmaController) {
1642 struct dma_controller *c = musb->pDmaController;
1644 (void) c->stop(c->pPrivateData);
1645 dma_controller_destroy(c);
1648 musb_writeb(musb->pRegs, MGC_O_HDRC_DEVCTL, 0);
1649 musb_platform_exit(musb);
1650 musb_writeb(musb->pRegs, MGC_O_HDRC_DEVCTL, 0);
1653 clk_disable(musb->clock);
1654 clk_put(musb->clock);
1657 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1658 usb_put_hcd(musb_to_hcd(musb));
1665 * Perform generic per-controller initialization.
1667 * @pDevice: the controller (already clocked, etc)
1669 * @pRegs: virtual address of controller registers,
1670 * not yet corrected for platform-specific offsets
1673 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1677 struct musb_hdrc_platform_data *plat = dev->platform_data;
1679 /* The driver might handle more features than the board; OK.
1680 * Fail when the board needs a feature that's not enabled.
1683 dev_dbg(dev, "no platform_data?\n");
1686 switch (plat->mode) {
1688 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1693 case MUSB_PERIPHERAL:
1694 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1700 #ifdef CONFIG_USB_MUSB_OTG
1706 dev_err(dev, "incompatible Kconfig role setting\n");
1711 pThis = allocate_instance(dev, ctrl);
1715 spin_lock_init(&pThis->Lock);
1716 pThis->board_mode = plat->mode;
1717 pThis->board_set_power = plat->set_power;
1718 pThis->set_clock = plat->set_clock;
1719 pThis->min_power = plat->min_power;
1721 /* Clock usage is chip-specific ... functional clock (DaVinci,
1722 * OMAP2430), or PHY ref (some TUSB6010 boards). All this core
1723 * code does is make sure a clock handle is available; platform
1724 * code manages it during start/stop and suspend/resume.
1727 pThis->clock = clk_get(dev, plat->clock);
1728 if (IS_ERR(pThis->clock)) {
1729 status = PTR_ERR(pThis->clock);
1730 pThis->clock = NULL;
1735 /* assume vbus is off */
1737 /* platform adjusts pThis->pRegs and pThis->isr if needed,
1738 * and activates clocks
1740 pThis->isr = generic_interrupt;
1741 status = musb_platform_init(pThis);
1750 #ifndef CONFIG_USB_INVENTRA_FIFO
1751 if (use_dma && dev->dma_mask) {
1752 struct dma_controller *c;
1754 c = dma_controller_create(pThis, pThis->pRegs);
1755 pThis->pDmaController = c;
1757 (void) c->start(c->pPrivateData);
1760 /* ideally this would be abstracted in platform setup */
1761 if (!is_dma_capable() || !pThis->pDmaController)
1762 dev->dma_mask = NULL;
1764 /* be sure interrupts are disabled before connecting ISR */
1765 musb_platform_disable(pThis);
1767 /* setup musb parts of the core (especially endpoints) */
1768 status = musb_core_init(plat->multipoint
1769 ? MUSB_CONTROLLER_MHDRC
1770 : MUSB_CONTROLLER_HDRC, pThis);
1774 /* attach to the IRQ */
1775 if (request_irq (nIrq, pThis->isr, 0, dev->bus_id, pThis)) {
1776 dev_err(dev, "request_irq %d failed!\n", nIrq);
1781 // FIXME this handles wakeup irqs wrong
1782 if (enable_irq_wake(nIrq) == 0)
1783 device_init_wakeup(dev, 1);
1785 pr_info("%s: USB %s mode controller at %p using %s, IRQ %d\n",
1788 switch (pThis->board_mode) {
1789 case MUSB_HOST: s = "Host"; break;
1790 case MUSB_PERIPHERAL: s = "Peripheral"; break;
1791 default: s = "OTG"; break;
1794 (is_dma_capable() && pThis->pDmaController)
1798 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1799 /* host side needs more setup, except for no-host modes */
1800 if (pThis->board_mode != MUSB_PERIPHERAL) {
1801 struct usb_hcd *hcd = musb_to_hcd(pThis);
1803 if (pThis->board_mode == MUSB_OTG)
1804 hcd->self.otg_port = 1;
1805 pThis->xceiv.host = &hcd->self;
1806 hcd->power_budget = 2 * (plat->power ? : 250);
1808 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
1810 /* For the host-only role, we can activate right away.
1811 * (We expect the ID pin to be forcibly grounded!!)
1812 * Otherwise, wait till the gadget driver hooks up.
1814 if (!is_otg_enabled(pThis) && is_host_enabled(pThis)) {
1815 MUSB_HST_MODE(pThis);
1816 pThis->xceiv.default_a = 1;
1817 pThis->xceiv.state = OTG_STATE_A_IDLE;
1819 status = usb_add_hcd(musb_to_hcd(pThis), -1, 0);
1821 DBG(1, "%s mode, status %d, devctl %02x %c\n",
1823 musb_readb(pThis->pRegs, MGC_O_HDRC_DEVCTL),
1824 (musb_readb(pThis->pRegs, MGC_O_HDRC_DEVCTL)
1825 & MGC_M_DEVCTL_BDEVICE
1828 } else /* peripheral is enabled */ {
1829 MUSB_DEV_MODE(pThis);
1830 pThis->xceiv.default_a = 0;
1831 pThis->xceiv.state = OTG_STATE_B_IDLE;
1833 status = musb_gadget_setup(pThis);
1835 DBG(1, "%s mode, status %d, dev%02x\n",
1836 is_otg_enabled(pThis) ? "OTG" : "PERIPHERAL",
1838 musb_readb(pThis->pRegs, MGC_O_HDRC_DEVCTL));
1843 musb_debug_create("driver/musb_hdrc", pThis);
1847 clk_put(pThis->clock);
1848 device_init_wakeup(dev, 0);
1853 INIT_WORK(&pThis->irq_work, musb_irq_work);
1856 status = device_create_file(dev, &dev_attr_mode);
1857 status = device_create_file(dev, &dev_attr_cable);
1864 musb_platform_exit(pThis);
1868 /*-------------------------------------------------------------------------*/
1870 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
1871 * bridge to a platform device; this driver then suffices.
1874 #ifndef CONFIG_USB_INVENTRA_FIFO
1875 static u64 *orig_dma_mask;
1878 static int __init musb_probe(struct platform_device *pdev)
1880 struct device *dev = &pdev->dev;
1881 int irq = platform_get_irq(pdev, 0);
1882 struct resource *iomem;
1885 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1886 if (!iomem || irq == 0)
1889 base = ioremap(iomem->start, iomem->end - iomem->start + 1);
1891 dev_err(dev, "ioremap failed\n");
1895 #ifndef CONFIG_USB_INVENTRA_FIFO
1896 /* clobbered by use_dma=n */
1897 orig_dma_mask = dev->dma_mask;
1899 return musb_init_controller(dev, irq, base);
1902 static int __devexit musb_remove(struct platform_device *pdev)
1904 struct musb *musb = dev_to_musb(&pdev->dev);
1905 void __iomem *ctrl_base = musb->ctrl_base;
1907 /* this gets called on rmmod.
1908 * - Host mode: host may still be active
1909 * - Peripheral mode: peripheral is deactivated (or never-activated)
1910 * - OTG mode: both roles are deactivated (or never-activated)
1912 musb_shutdown(pdev);
1913 musb_debug_delete("driver/musb_hdrc", musb);
1914 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1915 if (musb->board_mode == MUSB_HOST)
1916 usb_remove_hcd(musb_to_hcd(musb));
1920 device_init_wakeup(&pdev->dev, 0);
1921 #ifndef CONFIG_USB_INVENTRA_FIFO
1922 pdev->dev.dma_mask = orig_dma_mask;
1929 static int musb_suspend(struct platform_device *pdev, pm_message_t message)
1931 unsigned long flags;
1932 struct musb *musb = dev_to_musb(&pdev->dev);
1937 spin_lock_irqsave(&musb->Lock, flags);
1939 if (is_peripheral_active(musb)) {
1940 /* FIXME force disconnect unless we know USB will wake
1941 * the system up quickly enough to respond ...
1943 } else if (is_host_active(musb)) {
1944 /* we know all the children are suspended; sometimes
1945 * they will even be wakeup-enabled.
1949 clk_disable(musb->clock);
1950 spin_unlock_irqrestore(&musb->Lock, flags);
1954 static int musb_resume(struct platform_device *pdev)
1956 unsigned long flags;
1957 struct musb *musb = dev_to_musb(&pdev->dev);
1962 spin_lock_irqsave(&musb->Lock, flags);
1963 clk_enable(musb->clock);
1964 /* for static cmos like DaVinci, register values were preserved
1965 * unless for some reason the whole soc powered down and we're
1966 * not treating that as a whole-system restart (e.g. swsusp)
1968 spin_unlock_irqrestore(&musb->Lock, flags);
1973 #define musb_suspend NULL
1974 #define musb_resume NULL
1977 static struct platform_driver musb_driver = {
1979 .name = (char *)musb_driver_name,
1980 .bus = &platform_bus_type,
1981 .owner = THIS_MODULE,
1983 .remove = __devexit_p(musb_remove),
1984 .shutdown = musb_shutdown,
1985 .suspend = musb_suspend,
1986 .resume = musb_resume,
1989 /*-------------------------------------------------------------------------*/
1991 static int __init musb_init(void)
1993 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1998 pr_info("%s: version " MUSB_VERSION ", "
1999 #ifdef CONFIG_USB_INVENTRA_FIFO
2001 #elif defined(CONFIG_USB_TI_CPPI_DMA)
2003 #elif defined(CONFIG_USB_INVENTRA_DMA)
2005 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
2011 #ifdef CONFIG_USB_MUSB_OTG
2012 "otg (peripheral+host)"
2013 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
2015 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2019 musb_driver_name, debug);
2020 return platform_driver_probe(&musb_driver, musb_probe);
2023 /* make us init after usbcore and before usb
2024 * gadget and host-side drivers start to register
2026 subsys_initcall(musb_init);
2028 static void __exit musb_cleanup(void)
2030 platform_driver_unregister(&musb_driver);
2032 module_exit(musb_cleanup);