1 /*****************************************************************
2 * Copyright 2005 Mentor Graphics Corporation
3 * Copyright (C) 2005-2006 by Texas Instruments
4 * Copyright (C) 2006 by Nokia Corporation
6 * This file is part of the Inventra Controller Driver for Linux.
8 * The Inventra Controller Driver for Linux is free software; you
9 * can redistribute it and/or modify it under the terms of the GNU
10 * General Public License version 2 as published by the Free Software
13 * The Inventra Controller Driver for Linux is distributed in
14 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
15 * without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 * License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with The Inventra Controller Driver for Linux ; if not,
21 * write to the Free Software Foundation, Inc., 59 Temple Place,
22 * Suite 330, Boston, MA 02111-1307 USA
24 * ANY DOWNLOAD, USE, REPRODUCTION, MODIFICATION OR DISTRIBUTION
25 * OF THIS DRIVER INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE
26 * OF THOSE TERMS.THIS DRIVER IS PROVIDED "AS IS" AND MENTOR GRAPHICS
27 * MAKES NO WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THIS DRIVER.
28 * MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES
29 * OF MERCHANTABILITY; FITNESS FOR A PARTICULAR PURPOSE AND
30 * NON-INFRINGEMENT. MENTOR GRAPHICS DOES NOT PROVIDE SUPPORT
31 * SERVICES OR UPDATES FOR THIS DRIVER, EVEN IF YOU ARE A MENTOR
32 * GRAPHICS SUPPORT CUSTOMER.
33 ******************************************************************/
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - <asm/arch/hdrc_cnf.h> for SOC or family details
86 * - platform_device for addressing, irq, and platform_data
87 * - platform_data is mostly for board-specific informarion
89 * Most of the conditional compilation will (someday) vanish.
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/platform_device.h>
104 #include <asm/arch/hardware.h>
105 #include <asm/arch/memory.h>
106 #include <asm/mach-types.h>
109 #include "musbdefs.h"
112 #ifdef CONFIG_ARCH_DAVINCI
119 unsigned debug = MUSB_DEBUG;
120 module_param(debug, uint, 0);
121 MODULE_PARM_DESC(debug, "initial debug message level");
123 #define MUSB_VERSION_SUFFIX "/dbg"
126 const char *otg_state_string(struct musb *musb)
130 snprintf(buf, sizeof buf, "otg-%d", musb->xceiv.state);
135 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
136 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
138 #define MUSB_VERSION_BASE "2.2a/db-0.5.2"
140 #ifndef MUSB_VERSION_SUFFIX
141 #define MUSB_VERSION_SUFFIX ""
143 #define MUSB_VERSION MUSB_VERSION_BASE MUSB_VERSION_SUFFIX
145 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
147 const char musb_driver_name[] = "musb_hdrc";
149 MODULE_DESCRIPTION(DRIVER_INFO);
150 MODULE_AUTHOR(DRIVER_AUTHOR);
151 MODULE_LICENSE("GPL");
154 /*-------------------------------------------------------------------------*/
156 static inline struct musb *dev_to_musb(struct device *dev)
158 #ifdef CONFIG_USB_MUSB_HDRC_HCD
159 /* usbcore insists dev->driver_data is a "struct hcd *" */
160 return hcd_to_musb(dev_get_drvdata(dev));
162 return dev_get_drvdata(dev);
166 /*-------------------------------------------------------------------------*/
168 #ifndef CONFIG_USB_TUSB6010
170 * Load an endpoint's FIFO
172 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 wCount, const u8 *pSource)
174 void __iomem *fifo = hw_ep->fifo;
176 prefetch((u8 *)pSource);
178 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
179 'T', hw_ep->bLocalEnd, fifo, wCount, pSource);
181 /* we can't assume unaligned reads work */
182 if (likely((0x01 & (unsigned long) pSource) == 0)) {
185 /* best case is 32bit-aligned source address */
186 if ((0x02 & (unsigned long) pSource) == 0) {
188 writesl(fifo, pSource + index, wCount >> 2);
189 index += wCount & ~0x03;
192 musb_writew(fifo, 0, *(u16*)&pSource[index]);
197 writesw(fifo, pSource + index, wCount >> 1);
198 index += wCount & ~0x01;
202 musb_writeb(fifo, 0, pSource[index]);
205 writesb(fifo, pSource, wCount);
210 * Unload an endpoint's FIFO
212 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 wCount, u8 *pDest)
214 void __iomem *fifo = hw_ep->fifo;
216 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
217 'R', hw_ep->bLocalEnd, fifo, wCount, pDest);
219 /* we can't assume unaligned writes work */
220 if (likely((0x01 & (unsigned long) pDest) == 0)) {
223 /* best case is 32bit-aligned destination address */
224 if ((0x02 & (unsigned long) pDest) == 0) {
226 readsl(fifo, pDest, wCount >> 2);
227 index = wCount & ~0x03;
230 *(u16*)&pDest[index] = musb_readw(fifo, 0);
235 readsw(fifo, pDest, wCount >> 1);
236 index = wCount & ~0x01;
240 pDest[index] = musb_readb(fifo, 0);
243 readsb(fifo, pDest, wCount);
247 #endif /* normal PIO */
250 /*-------------------------------------------------------------------------*/
252 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
253 static const u8 musb_test_packet[53] = {
254 /* implicit SYNC then DATA0 to start */
257 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
259 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
261 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
262 /* JJJJJJJKKKKKKK x8 */
263 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
265 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
266 /* JKKKKKKK x10, JK */
267 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
269 /* implicit CRC16 then EOP to end */
272 void musb_load_testpacket(struct musb *musb)
274 void __iomem *regs = musb->aLocalEnd[0].regs;
276 MGC_SelectEnd(musb->pRegs, 0);
277 musb_write_fifo(musb->control_ep,
278 sizeof(musb_test_packet), musb_test_packet);
279 musb_writew(regs, MGC_O_HDRC_CSR0, MGC_M_CSR0_TXPKTRDY);
282 /*-------------------------------------------------------------------------*/
285 * Interrupt Service Routine to record USB "global" interrupts.
286 * Since these do not happen often and signify things of
287 * paramount importance, it seems OK to check them individually;
288 * the order of the tests is specified in the manual
290 * @param pThis instance pointer
291 * @param bIntrUSB register contents
296 #define STAGE0_MASK (MGC_M_INTR_RESUME | MGC_M_INTR_SESSREQ \
297 | MGC_M_INTR_VBUSERROR | MGC_M_INTR_CONNECT \
300 static irqreturn_t musb_stage0_irq(struct musb * pThis, u8 bIntrUSB,
303 irqreturn_t handled = IRQ_NONE;
304 #ifdef CONFIG_USB_MUSB_HDRC_HCD
305 void __iomem *pBase = pThis->pRegs;
308 DBG(3, "<== Power=%02x, DevCtl=%02x, bIntrUSB=0x%x\n", power, devctl,
311 /* in host mode, the peripheral may issue remote wakeup.
312 * in peripheral mode, the host may resume the link.
313 * spurious RESUME irqs happen too, paired with SUSPEND.
315 if (bIntrUSB & MGC_M_INTR_RESUME) {
316 handled = IRQ_HANDLED;
317 DBG(3, "RESUME (%s)\n", otg_state_string(pThis));
319 if (devctl & MGC_M_DEVCTL_HM) {
320 #ifdef CONFIG_USB_MUSB_HDRC_HCD
321 switch (pThis->xceiv.state) {
322 case OTG_STATE_A_SUSPEND:
323 /* remote wakeup? later, GetPortStatus
324 * will stop RESUME signaling
326 if (power & MGC_M_POWER_RESUME) {
327 power &= ~MGC_M_POWER_SUSPENDM;
328 musb_writeb(pBase, MGC_O_HDRC_POWER,
329 power | MGC_M_POWER_RESUME);
331 pThis->port1_status |=
332 (USB_PORT_STAT_C_SUSPEND << 16)
333 | MUSB_PORT_STAT_RESUME;
334 pThis->rh_timer = jiffies
335 + msecs_to_jiffies(20);
337 pThis->xceiv.state = OTG_STATE_A_HOST;
338 pThis->is_active = 1;
339 usb_hcd_resume_root_hub(
342 } else if (power & MGC_M_POWER_SUSPENDM) {
344 pThis->int_usb &= ~MGC_M_INTR_SUSPEND;
347 case OTG_STATE_B_WAIT_ACON:
348 pThis->xceiv.state = OTG_STATE_B_PERIPHERAL;
349 pThis->is_active = 1;
350 MUSB_DEV_MODE(pThis);
353 WARN("bogus %s RESUME (%s)\n",
355 otg_state_string(pThis));
359 switch (pThis->xceiv.state) {
360 #ifdef CONFIG_USB_MUSB_HDRC_HCD
361 case OTG_STATE_A_SUSPEND:
362 /* possibly DISCONNECT is upcoming */
363 pThis->xceiv.state = OTG_STATE_A_HOST;
364 usb_hcd_resume_root_hub(musb_to_hcd(pThis));
367 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
368 case OTG_STATE_B_WAIT_ACON:
369 case OTG_STATE_B_PERIPHERAL:
370 /* disconnect while suspended? we may
371 * not get a disconnect irq...
373 if ((devctl & MGC_M_DEVCTL_VBUS)
374 != (3 << MGC_S_DEVCTL_VBUS)) {
375 pThis->int_usb |= MGC_M_INTR_DISCONNECT;
376 pThis->int_usb &= ~MGC_M_INTR_SUSPEND;
379 musb_g_resume(pThis);
381 case OTG_STATE_B_IDLE:
382 pThis->int_usb &= ~MGC_M_INTR_SUSPEND;
386 WARN("bogus %s RESUME (%s)\n",
388 otg_state_string(pThis));
393 #ifdef CONFIG_USB_MUSB_HDRC_HCD
394 /* see manual for the order of the tests */
395 if (bIntrUSB & MGC_M_INTR_SESSREQ) {
396 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(pThis));
398 /* IRQ arrives from ID pin sense or (later, if VBUS power
399 * is removed) SRP. responses are time critical:
400 * - turn on VBUS (with silicon-specific mechanism)
401 * - go through A_WAIT_VRISE
402 * - ... to A_WAIT_BCON.
403 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
405 musb_writeb(pBase, MGC_O_HDRC_DEVCTL, MGC_M_DEVCTL_SESSION);
406 pThis->bEnd0Stage = MGC_END0_START;
407 pThis->xceiv.state = OTG_STATE_A_IDLE;
408 MUSB_HST_MODE(pThis);
409 musb_set_vbus(pThis, 1);
411 handled = IRQ_HANDLED;
414 if (bIntrUSB & MGC_M_INTR_VBUSERROR) {
417 /* During connection as an A-Device, we may see a short
418 * current spikes causing voltage drop, because of cable
419 * and peripheral capacitance combined with vbus draw.
420 * (So: less common with truly self-powered devices, where
421 * vbus doesn't act like a power supply.)
423 * Such spikes are short; usually less than ~500 usec, max
424 * of ~2 msec. That is, they're not sustained overcurrent
425 * errors, though they're reported using VBUSERROR irqs.
427 * Workarounds: (a) hardware: use self powered devices.
428 * (b) software: ignore non-repeated VBUS errors.
430 * REVISIT: do delays from lots of DEBUG_KERNEL checks
431 * make trouble here, keeping VBUS < 4.4V ?
433 switch (pThis->xceiv.state) {
434 case OTG_STATE_A_HOST:
435 /* recovery is dicey once we've gotten past the
436 * initial stages of enumeration, but if VBUS
437 * stayed ok at the other end of the link, and
438 * another reset is due (at least for high speed,
439 * to redo the chirp etc), it might work OK...
441 case OTG_STATE_A_WAIT_BCON:
442 case OTG_STATE_A_WAIT_VRISE:
443 if (pThis->vbuserr_retry) {
444 pThis->vbuserr_retry--;
446 devctl |= MGC_M_DEVCTL_SESSION;
447 musb_writeb(pBase, MGC_O_HDRC_DEVCTL, devctl);
449 pThis->port1_status |=
450 (1 << USB_PORT_FEAT_OVER_CURRENT)
451 | (1 << USB_PORT_FEAT_C_OVER_CURRENT);
458 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
459 otg_state_string(pThis),
462 switch (devctl & MGC_M_DEVCTL_VBUS) {
463 case 0 << MGC_S_DEVCTL_VBUS:
464 s = "<SessEnd"; break;
465 case 1 << MGC_S_DEVCTL_VBUS:
466 s = "<AValid"; break;
467 case 2 << MGC_S_DEVCTL_VBUS:
468 s = "<VBusValid"; break;
469 //case 3 << MGC_S_DEVCTL_VBUS:
473 VBUSERR_RETRY_COUNT - pThis->vbuserr_retry,
474 pThis->port1_status);
476 /* go through A_WAIT_VFALL then start a new session */
478 musb_set_vbus(pThis, 0);
479 handled = IRQ_HANDLED;
482 if (bIntrUSB & MGC_M_INTR_CONNECT) {
483 struct usb_hcd *hcd = musb_to_hcd(pThis);
485 handled = IRQ_HANDLED;
486 pThis->is_active = 1;
487 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
489 pThis->bEnd0Stage = MGC_END0_START;
491 #ifdef CONFIG_USB_MUSB_OTG
492 /* flush endpoints when transitioning from Device Mode */
493 if (is_peripheral_active(pThis)) {
494 // REVISIT HNP; just force disconnect
496 pThis->bDelayPortPowerOff = FALSE;
497 musb_writew(pBase, MGC_O_HDRC_INTRTXE, pThis->wEndMask);
498 musb_writew(pBase, MGC_O_HDRC_INTRRXE, pThis->wEndMask & 0xfffe);
499 musb_writeb(pBase, MGC_O_HDRC_INTRUSBE, 0xf7);
501 pThis->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
502 |USB_PORT_STAT_HIGH_SPEED
503 |USB_PORT_STAT_ENABLE
505 pThis->port1_status |= USB_PORT_STAT_CONNECTION
506 |(USB_PORT_STAT_C_CONNECTION << 16);
508 /* high vs full speed is just a guess until after reset */
509 if (devctl & MGC_M_DEVCTL_LSDEV)
510 pThis->port1_status |= USB_PORT_STAT_LOW_SPEED;
513 usb_hcd_poll_rh_status(hcd);
515 usb_hcd_resume_root_hub(hcd);
517 MUSB_HST_MODE(pThis);
519 /* indicate new connection to OTG machine */
520 switch (pThis->xceiv.state) {
521 case OTG_STATE_B_WAIT_ACON:
522 pThis->xceiv.state = OTG_STATE_B_HOST;
525 if ((devctl & MGC_M_DEVCTL_VBUS)
526 == (3 << MGC_S_DEVCTL_VBUS))
527 pThis->xceiv.state = OTG_STATE_A_HOST;
530 DBG(1, "CONNECT (%s) devctl %02x\n",
531 otg_state_string(pThis), devctl);
533 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
535 /* mentor saves a bit: bus reset and babble share the same irq.
536 * only host sees babble; only peripheral sees bus reset.
538 if (bIntrUSB & MGC_M_INTR_RESET) {
539 if (devctl & MGC_M_DEVCTL_HM) {
541 * BABBLE is an error condition, so the solution is
542 * to avoid babble in the first place and fix whatever
543 * causes BABBLE. When BABBLE happens we can only stop
546 ERR("Stopping host session because of babble\n");
547 musb_writeb(pBase, MGC_O_HDRC_DEVCTL, 0);
549 DBG(1, "BUS RESET\n");
552 schedule_work(&pThis->irq_work);
555 handled = IRQ_HANDLED;
562 * Interrupt Service Routine to record USB "global" interrupts.
563 * Since these do not happen often and signify things of
564 * paramount importance, it seems OK to check them individually;
565 * the order of the tests is specified in the manual
567 * @param pThis instance pointer
568 * @param bIntrUSB register contents
572 static irqreturn_t musb_stage2_irq(struct musb * pThis, u8 bIntrUSB,
575 irqreturn_t handled = IRQ_NONE;
578 /* REVISIT ... this would be for multiplexing periodic endpoints, or
579 * supporting transfer phasing to prevent exceeding ISO bandwidth
580 * limits of a given frame or microframe.
582 * It's not needed for peripheral side, which dedicates endpoints;
583 * though it _might_ use SOF irqs for other purposes.
585 * And it's not currently needed for host side, which also dedicates
586 * endpoints, relies on TX/RX interval registers, and isn't claimed
587 * to support ISO transfers yet.
589 if (bIntrUSB & MGC_M_INTR_SOF) {
590 void __iomem *pBase = pThis->pRegs;
591 struct musb_hw_ep *ep;
595 DBG(6, "START_OF_FRAME\n");
596 handled = IRQ_HANDLED;
598 /* start any periodic Tx transfers waiting for current frame */
599 wFrame = musb_readw(pBase, MGC_O_HDRC_FRAME);
600 ep = pThis->aLocalEnd;
601 for (bEnd = 1; (bEnd < pThis->bEndCount)
602 && (pThis->wEndMask >= (1 << bEnd));
604 // FIXME handle framecounter wraps (12 bits)
605 // eliminate duplicated StartUrb logic
606 if (ep->dwWaitFrame >= wFrame) {
608 printk("SOF --> periodic TX%s on %d\n",
609 ep->tx_channel ? " DMA" : "",
612 musb_h_tx_start(pThis, bEnd);
614 cppi_hostdma_start(pThis, bEnd);
616 } /* end of for loop */
620 if ((bIntrUSB & MGC_M_INTR_DISCONNECT) && !pThis->bIgnoreDisconnect) {
621 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
622 otg_state_string(pThis),
623 MUSB_MODE(pThis), devctl);
624 handled = IRQ_HANDLED;
626 switch (pThis->xceiv.state) {
627 #ifdef CONFIG_USB_MUSB_HDRC_HCD
628 case OTG_STATE_A_HOST:
629 case OTG_STATE_A_SUSPEND:
630 musb_root_disconnect(pThis);
633 #ifdef CONFIG_USB_MUSB_OTG
634 case OTG_STATE_A_PERIPHERAL:
635 case OTG_STATE_B_HOST:
636 musb_root_disconnect(pThis);
638 case OTG_STATE_B_WAIT_ACON:
640 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
641 case OTG_STATE_B_PERIPHERAL:
642 musb_g_disconnect(pThis);
646 WARN("unhandled DISCONNECT transition (%s)\n",
647 otg_state_string(pThis));
651 schedule_work(&pThis->irq_work);
654 if (bIntrUSB & MGC_M_INTR_SUSPEND) {
655 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
656 otg_state_string(pThis), devctl, power);
657 handled = IRQ_HANDLED;
659 switch (pThis->xceiv.state) {
660 case OTG_STATE_B_PERIPHERAL:
661 musb_g_suspend(pThis);
662 pThis->is_active = is_otg_enabled(pThis)
663 && pThis->xceiv.gadget->b_hnp_enable;
664 if (pThis->is_active) {
665 pThis->xceiv.state = OTG_STATE_B_WAIT_ACON;
666 /* REVISIT timeout for b_ase0_brst, etc */
669 case OTG_STATE_A_HOST:
670 pThis->xceiv.state = OTG_STATE_A_SUSPEND;
671 pThis->is_active = is_otg_enabled(pThis)
672 && pThis->xceiv.host->b_hnp_enable;
675 /* "should not happen" */
676 pThis->is_active = 0;
685 /*-------------------------------------------------------------------------*/
688 * Program the HDRC to start (enable interrupts, dma, etc.).
690 void musb_start(struct musb *musb)
692 void __iomem *regs = musb->pRegs;
693 u8 devctl = musb_readb(regs, MGC_O_HDRC_DEVCTL);
695 DBG(2, "<== devctl %02x\n", devctl);
697 /* Set INT enable registers, enable interrupts */
698 musb_writew(regs, MGC_O_HDRC_INTRTXE, musb->wEndMask);
699 musb_writew(regs, MGC_O_HDRC_INTRRXE, musb->wEndMask & 0xfffe);
700 musb_writeb(regs, MGC_O_HDRC_INTRUSBE, 0xf7);
702 musb_writeb(regs, MGC_O_HDRC_TESTMODE, 0);
704 /* put into basic highspeed mode and start session */
705 musb_writeb(regs, MGC_O_HDRC_POWER, MGC_M_POWER_ISOUPDATE
706 | MGC_M_POWER_SOFTCONN
708 /* ENSUSPEND wedges tusb */
709 // | MGC_M_POWER_ENSUSPEND
713 devctl = musb_readb(regs, MGC_O_HDRC_DEVCTL);
714 devctl &= ~MGC_M_DEVCTL_SESSION;
716 if (is_otg_enabled(musb)) {
717 /* session started after:
718 * (a) ID-grounded irq, host mode;
719 * (b) vbus present/connect IRQ, peripheral mode;
720 * (c) peripheral initiates, using SRP
722 if ((devctl & MGC_M_DEVCTL_VBUS) == MGC_M_DEVCTL_VBUS)
725 devctl |= MGC_M_DEVCTL_SESSION;
727 } else if (is_host_enabled(musb)) {
728 /* assume ID pin is hard-wired to ground */
729 devctl |= MGC_M_DEVCTL_SESSION;
731 } else /* peripheral is enabled */ {
732 if ((devctl & MGC_M_DEVCTL_VBUS) == MGC_M_DEVCTL_VBUS)
735 musb_platform_enable(musb);
736 musb_writeb(regs, MGC_O_HDRC_DEVCTL, devctl);
740 static void musb_generic_disable(struct musb *pThis)
742 void __iomem *pBase = pThis->pRegs;
745 /* disable interrupts */
746 musb_writeb(pBase, MGC_O_HDRC_INTRUSBE, 0);
747 musb_writew(pBase, MGC_O_HDRC_INTRTXE, 0);
748 musb_writew(pBase, MGC_O_HDRC_INTRRXE, 0);
751 musb_writeb(pBase, MGC_O_HDRC_DEVCTL, 0);
753 /* flush pending interrupts */
754 temp = musb_readb(pBase, MGC_O_HDRC_INTRUSB);
755 temp = musb_readw(pBase, MGC_O_HDRC_INTRTX);
756 temp = musb_readw(pBase, MGC_O_HDRC_INTRRX);
761 * Make the HDRC stop (disable interrupts, etc.);
762 * reversible by musb_start
763 * called on gadget driver unregister
764 * with controller locked, irqs blocked
765 * acts as a NOP unless some role activated the hardware
767 void musb_stop(struct musb *musb)
769 /* stop IRQs, timers, ... */
770 musb_platform_disable(musb);
771 musb_generic_disable(musb);
772 DBG(3, "HDRC disabled\n");
775 * - mark host and/or peripheral drivers unusable/inactive
776 * - disable DMA (and enable it in HdrcStart)
777 * - make sure we can musb_start() after musb_stop(); with
778 * OTG mode, gadget driver module rmmod/modprobe cycles that
781 musb_platform_try_idle(musb);
784 static void musb_shutdown(struct platform_device *pdev)
786 struct musb *musb = dev_to_musb(&pdev->dev);
789 spin_lock_irqsave(&musb->Lock, flags);
790 musb_platform_disable(musb);
791 musb_generic_disable(musb);
793 clk_put(musb->clock);
796 spin_unlock_irqrestore(&musb->Lock, flags);
798 /* FIXME power down */
802 /*-------------------------------------------------------------------------*/
805 * The silicon either has hard-wired endpoint configurations, or else
806 * "dynamic fifo" sizing. The driver has support for both, though at this
807 * writing only the dynamic sizing is very well tested. We use normal
808 * idioms to so both modes are compile-tested, but dead code elimination
809 * leaves only the relevant one in the object file.
811 * We don't currently use dynamic fifo setup capability to do anything
812 * more than selecting one of a bunch of predefined configurations.
814 #ifdef MUSB_C_DYNFIFO_DEF
815 #define can_dynfifo() 1
817 #define can_dynfifo() 0
820 #ifdef CONFIG_USB_TUSB6010
821 static ushort __initdata fifo_mode = 4;
823 static ushort __initdata fifo_mode = 2;
826 /* "modprobe ... fifo_mode=1" etc */
827 module_param(fifo_mode, ushort, 0);
828 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
831 #define DYN_FIFO_SIZE (1<<(MUSB_C_RAM_BITS+2))
833 enum fifo_style { FIFO_RXTX, FIFO_TX, FIFO_RX } __attribute__ ((packed));
834 enum buf_mode { BUF_SINGLE, BUF_DOUBLE } __attribute__ ((packed));
838 enum fifo_style style;
844 * tables defining fifo_mode values. define more if you like.
845 * for host side, make sure both halves of ep1 are set up.
848 /* mode 0 - fits in 2KB */
849 static struct fifo_cfg __initdata mode_0_cfg[] = {
850 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
851 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
852 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
853 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
854 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
857 /* mode 1 - fits in 4KB */
858 static struct fifo_cfg __initdata mode_1_cfg[] = {
859 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
860 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
861 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
862 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
863 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
866 /* mode 2 - fits in 4KB */
867 static struct fifo_cfg __initdata mode_2_cfg[] = {
868 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
869 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
870 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
871 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
872 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
873 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
876 /* mode 3 - fits in 4KB */
877 static struct fifo_cfg __initdata mode_3_cfg[] = {
878 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
879 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
880 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
881 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
882 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
883 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
886 /* mode 4 - fits in 16KB */
887 static struct fifo_cfg __initdata mode_4_cfg[] = {
888 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
889 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
890 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
891 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
892 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
893 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
894 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
895 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
896 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
897 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
898 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
899 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
900 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
901 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
902 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
903 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
904 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
905 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
906 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 512, },
907 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 512, },
908 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 512, },
909 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 512, },
910 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 512, },
911 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 512, },
912 { .hw_ep_num = 13, .style = FIFO_TX, .maxpacket = 512, },
913 { .hw_ep_num = 13, .style = FIFO_RX, .maxpacket = 512, },
914 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
915 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
920 * configure a fifo; for non-shared endpoints, this may be called
921 * once for a tx fifo and once for an rx fifo.
923 * returns negative errno or offset for next fifo.
926 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
927 const struct fifo_cfg *cfg, u16 offset)
929 void __iomem *mbase = musb->pRegs;
931 u16 maxpacket = cfg->maxpacket;
932 u16 c_off = offset >> 3;
935 /* expect hw_ep has already been zero-initialized */
937 size = ffs(max(maxpacket, (u16) 8)) - 1;
938 maxpacket = 1 << size;
941 if (cfg->mode == BUF_DOUBLE) {
942 if ((offset + (maxpacket << 1)) > DYN_FIFO_SIZE)
944 c_size |= MGC_M_FIFOSZ_DPB;
946 if ((offset + maxpacket) > DYN_FIFO_SIZE)
950 /* configure the FIFO */
951 musb_writeb(mbase, MGC_O_HDRC_INDEX, hw_ep->bLocalEnd);
953 #ifdef CONFIG_USB_MUSB_HDRC_HCD
954 /* EP0 reserved endpoint for control, bidirectional;
955 * EP1 reserved for bulk, two unidirection halves.
957 if (hw_ep->bLocalEnd == 1)
958 musb->bulk_ep = hw_ep;
959 /* REVISIT error check: be sure ep0 can both rx and tx ... */
961 switch (cfg->style) {
963 musb_writeb(mbase, MGC_O_HDRC_TXFIFOSZ, c_size);
964 musb_writew(mbase, MGC_O_HDRC_TXFIFOADD, c_off);
965 hw_ep->tx_double_buffered = !!(c_size & MGC_M_FIFOSZ_DPB);
966 hw_ep->wMaxPacketSizeTx = maxpacket;
969 musb_writeb(mbase, MGC_O_HDRC_RXFIFOSZ, c_size);
970 musb_writew(mbase, MGC_O_HDRC_RXFIFOADD, c_off);
971 hw_ep->rx_double_buffered = !!(c_size & MGC_M_FIFOSZ_DPB);
972 hw_ep->wMaxPacketSizeRx = maxpacket;
975 musb_writeb(mbase, MGC_O_HDRC_TXFIFOSZ, c_size);
976 musb_writew(mbase, MGC_O_HDRC_TXFIFOADD, c_off);
977 hw_ep->rx_double_buffered = !!(c_size & MGC_M_FIFOSZ_DPB);
978 hw_ep->wMaxPacketSizeRx = maxpacket;
980 musb_writeb(mbase, MGC_O_HDRC_RXFIFOSZ, c_size);
981 musb_writew(mbase, MGC_O_HDRC_RXFIFOADD, c_off);
982 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
983 hw_ep->wMaxPacketSizeTx = maxpacket;
985 hw_ep->bIsSharedFifo = TRUE;
989 /* NOTE rx and tx endpoint irqs aren't managed separately,
990 * which happens to be ok
992 musb->wEndMask |= (1 << hw_ep->bLocalEnd);
994 return offset + (maxpacket << ((c_size & MGC_M_FIFOSZ_DPB) ? 1 : 0));
997 static struct fifo_cfg __initdata ep0_cfg = {
998 .style = FIFO_RXTX, .maxpacket = 64,
1001 static int __init ep_config_from_table(struct musb *musb)
1003 const struct fifo_cfg *cfg;
1006 struct musb_hw_ep *hw_ep = musb->aLocalEnd;
1008 switch (fifo_mode) {
1014 n = ARRAY_SIZE(mode_0_cfg);
1018 n = ARRAY_SIZE(mode_1_cfg);
1022 n = ARRAY_SIZE(mode_2_cfg);
1026 n = ARRAY_SIZE(mode_3_cfg);
1030 n = ARRAY_SIZE(mode_4_cfg);
1034 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1035 musb_driver_name, fifo_mode);
1038 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1039 // assert(offset > 0)
1041 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1042 * be better than static MUSB_C_NUM_EPS and DYN_FIFO_SIZE...
1045 for (i = 0; i < n; i++) {
1046 u8 epn = cfg->hw_ep_num;
1048 if (epn >= MUSB_C_NUM_EPS) {
1049 pr_debug( "%s: invalid ep %d\n",
1050 musb_driver_name, epn);
1053 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1055 pr_debug( "%s: mem overrun, ep %d\n",
1056 musb_driver_name, epn);
1060 musb->bEndCount = max(epn, musb->bEndCount);
1063 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1065 n + 1, MUSB_C_NUM_EPS * 2 - 1,
1066 offset, DYN_FIFO_SIZE);
1068 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1069 if (!musb->bulk_ep) {
1070 pr_debug( "%s: missing bulk\n", musb_driver_name);
1080 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1081 * @param pThis the controller
1083 static int __init ep_config_from_hw(struct musb *musb)
1086 struct musb_hw_ep *pEnd;
1087 void *pBase = musb->pRegs;
1089 DBG(2, "<== static silicon ep config\n");
1091 /* FIXME pick up ep0 maxpacket size */
1093 for (bEnd = 1; bEnd < MUSB_C_NUM_EPS; bEnd++) {
1094 MGC_SelectEnd(pBase, bEnd);
1095 pEnd = musb->aLocalEnd + bEnd;
1097 /* read from core using indexed model */
1098 reg = musb_readb(pEnd->regs, 0x10 + MGC_O_HDRC_FIFOSIZE);
1100 /* 0's returned when no more endpoints */
1104 musb->wEndMask |= (1 << bEnd);
1106 pEnd->wMaxPacketSizeTx = 1 << (reg & 0x0f);
1108 /* shared TX/RX FIFO? */
1109 if ((reg & 0xf0) == 0xf0) {
1110 pEnd->wMaxPacketSizeRx = pEnd->wMaxPacketSizeTx;
1111 pEnd->bIsSharedFifo = TRUE;
1114 pEnd->wMaxPacketSizeRx = 1 << ((reg & 0xf0) >> 4);
1115 pEnd->bIsSharedFifo = FALSE;
1118 /* FIXME set up pEnd->{rx,tx}_double_buffered */
1120 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1121 /* pick an RX/TX endpoint for bulk */
1122 if (pEnd->wMaxPacketSizeTx < 512
1123 || pEnd->wMaxPacketSizeRx < 512)
1126 /* REVISIT: this algorithm is lazy, we should at least
1127 * try to pick a double buffered endpoint.
1131 musb->bulk_ep = pEnd;
1135 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1136 if (!musb->bulk_ep) {
1137 pr_debug( "%s: missing bulk\n", musb_driver_name);
1145 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1147 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1148 * configure endpoints, or take their config from silicon
1150 static int __init musb_core_init(u16 wType, struct musb *pThis)
1157 u16 wRelease, wRelMajor, wRelMinor;
1158 char aInfo[78], aRevision[32], aDate[12];
1159 void __iomem *pBase = pThis->pRegs;
1163 /* log core options (read using indexed model) */
1164 MGC_SelectEnd(pBase, 0);
1165 reg = musb_readb(pBase, 0x10 + MGC_O_HDRC_CONFIGDATA);
1167 strcpy(aInfo, (reg & MGC_M_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1168 if (reg & MGC_M_CONFIGDATA_DYNFIFO) {
1169 strcat(aInfo, ", dyn FIFOs");
1171 if (reg & MGC_M_CONFIGDATA_MPRXE) {
1172 strcat(aInfo, ", bulk combine");
1174 pThis->bBulkCombine = TRUE;
1176 strcat(aInfo, " (X)"); /* no driver support */
1179 if (reg & MGC_M_CONFIGDATA_MPTXE) {
1180 strcat(aInfo, ", bulk split");
1182 pThis->bBulkSplit = TRUE;
1184 strcat(aInfo, " (X)"); /* no driver support */
1187 if (reg & MGC_M_CONFIGDATA_HBRXE) {
1188 strcat(aInfo, ", HB-ISO Rx");
1189 strcat(aInfo, " (X)"); /* no driver support */
1191 if (reg & MGC_M_CONFIGDATA_HBTXE) {
1192 strcat(aInfo, ", HB-ISO Tx");
1193 strcat(aInfo, " (X)"); /* no driver support */
1195 if (reg & MGC_M_CONFIGDATA_SOFTCONE) {
1196 strcat(aInfo, ", SoftConn");
1199 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1200 musb_driver_name, reg, aInfo);
1203 dwData = musb_readl(pBase, 0x404);
1204 sprintf(aDate, "%04d-%02x-%02x", (dwData & 0xffff),
1205 (dwData >> 16) & 0xff, (dwData >> 24) & 0xff);
1206 /* FIXME ID2 and ID3 are unused */
1207 dwData = musb_readl(pBase, 0x408);
1208 printk("ID2=%lx\n", (long unsigned)dwData);
1209 dwData = musb_readl(pBase, 0x40c);
1210 printk("ID3=%lx\n", (long unsigned)dwData);
1211 reg = musb_readb(pBase, 0x400);
1212 wType = ('M' == reg) ? MUSB_CONTROLLER_MHDRC : MUSB_CONTROLLER_HDRC;
1216 if (MUSB_CONTROLLER_MHDRC == wType) {
1217 pThis->bIsMultipoint = 1;
1220 pThis->bIsMultipoint = 0;
1222 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1223 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1225 "%s: kernel must blacklist external hubs\n",
1231 /* log release info */
1232 wRelease = musb_readw(pBase, MGC_O_HDRC_HWVERS);
1233 wRelMajor = (wRelease >> 10) & 0x1f;
1234 wRelMinor = wRelease & 0x3ff;
1235 snprintf(aRevision, 32, "%d.%d%s", wRelMajor,
1236 wRelMinor, (wRelease & 0x8000) ? "RC" : "");
1237 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1238 musb_driver_name, type, aRevision, aDate);
1241 pThis->aLocalEnd[0].wMaxPacketSizeTx = MGC_END0_FIFOSIZE;
1242 pThis->aLocalEnd[0].wMaxPacketSizeRx = MGC_END0_FIFOSIZE;
1244 /* discover endpoint configuration */
1245 pThis->bEndCount = 1;
1246 pThis->wEndMask = 1;
1248 if (reg & MGC_M_CONFIGDATA_DYNFIFO) {
1250 status = ep_config_from_table(pThis);
1252 ERR("reconfigure software for Dynamic FIFOs\n");
1257 status = ep_config_from_hw(pThis);
1259 ERR("reconfigure software for static FIFOs\n");
1267 /* finish init, and print endpoint config */
1268 for (i = 0; i < pThis->bEndCount; i++) {
1269 struct musb_hw_ep *hw_ep = pThis->aLocalEnd + i;
1271 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + pBase;
1272 #ifdef CONFIG_USB_TUSB6010
1273 hw_ep->fifo_async = pThis->async + 0x400 + MUSB_FIFO_OFFSET(i);
1274 hw_ep->fifo_sync = pThis->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1275 hw_ep->fifo_sync_va =
1276 pThis->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1279 hw_ep->conf = pBase - 0x400 + TUSB_EP0_CONF;
1281 hw_ep->conf = pBase + 0x400 + (((i - 1) & 0xf) << 2);
1284 hw_ep->regs = MGC_END_OFFSET(i, 0) + pBase;
1285 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1286 hw_ep->target_regs = MGC_BUSCTL_OFFSET(i, 0) + pBase;
1287 hw_ep->rx_reinit = 1;
1288 hw_ep->tx_reinit = 1;
1291 if (hw_ep->wMaxPacketSizeTx) {
1293 "%s: hw_ep %d%s, %smax %d\n",
1294 musb_driver_name, i,
1295 hw_ep->bIsSharedFifo ? "shared" : "tx",
1296 hw_ep->tx_double_buffered
1297 ? "doublebuffer, " : "",
1298 hw_ep->wMaxPacketSizeTx);
1300 if (hw_ep->wMaxPacketSizeRx && !hw_ep->bIsSharedFifo) {
1302 "%s: hw_ep %d%s, %smax %d\n",
1303 musb_driver_name, i,
1305 hw_ep->rx_double_buffered
1306 ? "doublebuffer, " : "",
1307 hw_ep->wMaxPacketSizeRx);
1309 if (!(hw_ep->wMaxPacketSizeTx || hw_ep->wMaxPacketSizeRx))
1310 DBG(1, "hw_ep %d not configured\n", i);
1316 /*-------------------------------------------------------------------------*/
1318 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
1320 static irqreturn_t generic_interrupt(int irq, void *__hci)
1322 unsigned long flags;
1323 irqreturn_t retval = IRQ_NONE;
1324 struct musb *musb = __hci;
1326 spin_lock_irqsave(&musb->Lock, flags);
1328 musb->int_usb = musb_readb(musb->pRegs, MGC_O_HDRC_INTRUSB);
1329 musb->int_tx = musb_readw(musb->pRegs, MGC_O_HDRC_INTRTX);
1330 musb->int_rx = musb_readw(musb->pRegs, MGC_O_HDRC_INTRRX);
1332 if (musb->int_usb || musb->int_tx || musb->int_rx)
1333 retval = musb_interrupt(musb);
1335 spin_unlock_irqrestore(&musb->Lock, flags);
1337 /* REVISIT we sometimes get spurious IRQs on g_ep0
1340 if (retval != IRQ_HANDLED)
1341 DBG(5, "spurious?\n");
1347 #define generic_interrupt NULL
1351 * handle all the irqs defined by the HDRC core. for now we expect: other
1352 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1353 * will be assigned, and the irq will already have been acked.
1355 * called in irq context with spinlock held, irqs blocked
1357 irqreturn_t musb_interrupt(struct musb *musb)
1359 irqreturn_t retval = IRQ_NONE;
1364 devctl = musb_readb(musb->pRegs, MGC_O_HDRC_DEVCTL);
1365 power = musb_readb(musb->pRegs, MGC_O_HDRC_POWER);
1367 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
1368 (devctl & MGC_M_DEVCTL_HM) ? "host" : "peripheral",
1369 musb->int_usb, musb->int_tx, musb->int_rx);
1371 /* the core can interrupt us for multiple reasons; docs have
1372 * a generic interrupt flowchart to follow
1374 if (musb->int_usb & STAGE0_MASK)
1375 retval |= musb_stage0_irq(musb, musb->int_usb,
1378 /* "stage 1" is handling endpoint irqs */
1380 /* handle endpoint 0 first */
1381 if (musb->int_tx & 1) {
1382 if (devctl & MGC_M_DEVCTL_HM)
1383 retval |= musb_h_ep0_irq(musb);
1385 retval |= musb_g_ep0_irq(musb);
1388 /* RX on endpoints 1-15 */
1389 reg = musb->int_rx >> 1;
1393 // MGC_SelectEnd(musb->pRegs, ep_num);
1394 /* REVISIT just retval = ep->rx_irq(...) */
1395 retval = IRQ_HANDLED;
1396 if (devctl & MGC_M_DEVCTL_HM) {
1397 if (is_host_capable())
1398 musb_host_rx(musb, ep_num);
1400 if (is_peripheral_capable())
1401 musb_g_rx(musb, ep_num);
1409 /* TX on endpoints 1-15 */
1410 reg = musb->int_tx >> 1;
1414 // MGC_SelectEnd(musb->pRegs, ep_num);
1415 /* REVISIT just retval |= ep->tx_irq(...) */
1416 retval = IRQ_HANDLED;
1417 if (devctl & MGC_M_DEVCTL_HM) {
1418 if (is_host_capable())
1419 musb_host_tx(musb, ep_num);
1421 if (is_peripheral_capable())
1422 musb_g_tx(musb, ep_num);
1429 /* finish handling "global" interrupts after handling fifos */
1431 retval |= musb_stage2_irq(musb,
1432 musb->int_usb, devctl, power);
1438 #ifndef CONFIG_USB_INVENTRA_FIFO
1439 static int __initdata use_dma = 1;
1441 /* "modprobe ... use_dma=0" etc */
1442 module_param(use_dma, bool, 0);
1443 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1445 void musb_dma_completion(struct musb *musb, u8 bLocalEnd, u8 bTransmit)
1447 u8 devctl = musb_readb(musb->pRegs, MGC_O_HDRC_DEVCTL);
1449 /* called with controller lock already held */
1452 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1453 if (!is_cppi_enabled()) {
1455 if (devctl & MGC_M_DEVCTL_HM)
1456 musb_h_ep0_irq(musb);
1458 musb_g_ep0_irq(musb);
1462 /* endpoints 1..15 */
1464 if (devctl & MGC_M_DEVCTL_HM) {
1465 if (is_host_capable())
1466 musb_host_tx(musb, bLocalEnd);
1468 if (is_peripheral_capable())
1469 musb_g_tx(musb, bLocalEnd);
1473 if (devctl & MGC_M_DEVCTL_HM) {
1474 if (is_host_capable())
1475 musb_host_rx(musb, bLocalEnd);
1477 if (is_peripheral_capable())
1478 musb_g_rx(musb, bLocalEnd);
1488 /*-------------------------------------------------------------------------*/
1493 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1495 struct musb *musb = dev_to_musb(dev);
1496 unsigned long flags;
1499 spin_lock_irqsave(&musb->Lock, flags);
1500 switch (musb->board_mode) {
1502 ret = sprintf(buf, "host\n");
1504 case MUSB_PERIPHERAL:
1505 ret = sprintf(buf, "peripheral\n");
1508 ret = sprintf(buf, "otg\n");
1511 spin_unlock_irqrestore(&musb->Lock, flags);
1517 musb_mode_store(struct device *dev, struct device_attribute *attr,
1518 const char *buf, size_t n)
1520 struct musb *musb = dev_to_musb(dev);
1521 unsigned long flags;
1523 spin_lock_irqsave(&musb->Lock, flags);
1524 if (!strncmp(buf, "host", 4))
1525 musb_platform_set_mode(musb, MUSB_HOST);
1526 if (!strncmp(buf, "peripheral", 10))
1527 musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1528 if (!strncmp(buf, "otg", 3))
1529 musb_platform_set_mode(musb, MUSB_OTG);
1530 spin_unlock_irqrestore(&musb->Lock, flags);
1534 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1537 musb_cable_show(struct device *dev, struct device_attribute *attr, char *buf)
1539 struct musb *musb = dev_to_musb(dev);
1540 char *v1= "", *v2 = "?";
1541 unsigned long flags;
1544 spin_lock_irqsave(&musb->Lock, flags);
1545 #if defined(CONFIG_USB_TUSB6010) && !defined(CONFIG_USB_MUSB_OTG)
1546 /* REVISIT: connect-A != connect-B ... */
1547 vbus = musb_platform_get_vbus_status(musb);
1551 v2 = "disconnected";
1553 /* NOTE: board-specific issues, like too-big capacitors keeping
1554 * VBUS high for a long time after power has been removed, can
1555 * cause temporary false indications of a connection.
1557 vbus = musb_readb(musb->pRegs, MGC_O_HDRC_DEVCTL);
1559 /* REVISIT retest on real OTG hardware */
1560 switch (musb->board_mode) {
1564 case MUSB_PERIPHERAL:
1569 v2 = (vbus & MGC_M_DEVCTL_BDEVICE) ? "B" : "A";
1572 } else /* VBUS level below A-Valid */
1573 v2 = "disconnected";
1575 musb_platform_try_idle(musb);
1576 spin_unlock_irqrestore(&musb->Lock, flags);
1578 return sprintf(buf, "%s%s\n", v1, v2);
1580 static DEVICE_ATTR(cable, S_IRUGO, musb_cable_show, NULL);
1584 /* Only used to provide cable state change events */
1585 static void musb_irq_work(struct work_struct *data)
1587 struct musb *musb = container_of(data, struct musb, irq_work);
1589 sysfs_notify(&musb->controller->kobj, NULL, "cable");
1592 /* --------------------------------------------------------------------------
1596 static struct musb *__init
1597 allocate_instance(struct device *dev, void __iomem *mbase)
1600 struct musb_hw_ep *ep;
1602 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1603 struct usb_hcd *hcd;
1605 hcd = usb_create_hcd(&musb_hc_driver, dev, dev->bus_id);
1608 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1610 musb = hcd_to_musb(hcd);
1611 INIT_LIST_HEAD(&musb->control);
1612 INIT_LIST_HEAD(&musb->in_bulk);
1613 INIT_LIST_HEAD(&musb->out_bulk);
1615 hcd->uses_new_polling = 1;
1617 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1619 musb = kzalloc(sizeof *musb, GFP_KERNEL);
1622 dev_set_drvdata(dev, musb);
1626 musb->pRegs = mbase;
1627 musb->ctrl_base = mbase;
1628 musb->nIrq = -ENODEV;
1629 for (epnum = 0, ep = musb->aLocalEnd;
1630 epnum < MUSB_C_NUM_EPS;
1634 ep->bLocalEnd = epnum;
1637 musb->controller = dev;
1641 static void musb_free(struct musb *musb)
1643 /* this has multiple entry modes. it handles fault cleanup after
1644 * probe(), where things may be partially set up, as well as rmmod
1645 * cleanup after everything's been de-activated.
1649 device_remove_file(musb->controller, &dev_attr_mode);
1650 device_remove_file(musb->controller, &dev_attr_cable);
1653 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1654 musb_gadget_cleanup(musb);
1657 if (musb->nIrq >= 0) {
1658 disable_irq_wake(musb->nIrq);
1659 free_irq(musb->nIrq, musb);
1661 if (is_dma_capable() && musb->pDmaController) {
1662 struct dma_controller *c = musb->pDmaController;
1664 (void) c->stop(c->pPrivateData);
1665 dma_controller_destroy(c);
1668 musb_writeb(musb->pRegs, MGC_O_HDRC_DEVCTL, 0);
1669 musb_platform_exit(musb);
1670 musb_writeb(musb->pRegs, MGC_O_HDRC_DEVCTL, 0);
1673 clk_disable(musb->clock);
1674 clk_put(musb->clock);
1677 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1678 usb_put_hcd(musb_to_hcd(musb));
1685 * Perform generic per-controller initialization.
1687 * @pDevice: the controller (already clocked, etc)
1689 * @pRegs: virtual address of controller registers,
1690 * not yet corrected for platform-specific offsets
1693 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1697 struct musb_hdrc_platform_data *plat = dev->platform_data;
1699 /* The driver might handle more features than the board; OK.
1700 * Fail when the board needs a feature that's not enabled.
1703 dev_dbg(dev, "no platform_data?\n");
1706 switch (plat->mode) {
1708 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1713 case MUSB_PERIPHERAL:
1714 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1720 #ifdef CONFIG_USB_MUSB_OTG
1726 dev_err(dev, "incompatible Kconfig role setting\n");
1731 pThis = allocate_instance(dev, ctrl);
1735 spin_lock_init(&pThis->Lock);
1736 pThis->board_mode = plat->mode;
1737 pThis->board_set_power = plat->set_power;
1738 pThis->set_clock = plat->set_clock;
1739 pThis->min_power = plat->min_power;
1741 /* Clock usage is chip-specific ... functional clock (DaVinci,
1742 * OMAP2430), or PHY ref (some TUSB6010 boards). All this core
1743 * code does is make sure a clock handle is available; platform
1744 * code manages it during start/stop and suspend/resume.
1747 pThis->clock = clk_get(dev, plat->clock);
1748 if (IS_ERR(pThis->clock)) {
1749 status = PTR_ERR(pThis->clock);
1750 pThis->clock = NULL;
1755 /* assume vbus is off */
1757 /* platform adjusts pThis->pRegs and pThis->isr if needed,
1758 * and activates clocks
1760 pThis->isr = generic_interrupt;
1761 status = musb_platform_init(pThis);
1770 #ifndef CONFIG_USB_INVENTRA_FIFO
1771 if (use_dma && dev->dma_mask) {
1772 struct dma_controller *c;
1774 c = dma_controller_create(pThis, pThis->pRegs);
1775 pThis->pDmaController = c;
1777 (void) c->start(c->pPrivateData);
1780 /* ideally this would be abstracted in platform setup */
1781 if (!is_dma_capable() || !pThis->pDmaController)
1782 dev->dma_mask = NULL;
1784 /* be sure interrupts are disabled before connecting ISR */
1785 musb_platform_disable(pThis);
1786 musb_generic_disable(pThis);
1788 /* setup musb parts of the core (especially endpoints) */
1789 status = musb_core_init(plat->multipoint
1790 ? MUSB_CONTROLLER_MHDRC
1791 : MUSB_CONTROLLER_HDRC, pThis);
1795 /* attach to the IRQ */
1796 if (request_irq (nIrq, pThis->isr, 0, dev->bus_id, pThis)) {
1797 dev_err(dev, "request_irq %d failed!\n", nIrq);
1802 // FIXME this handles wakeup irqs wrong
1803 if (enable_irq_wake(nIrq) == 0)
1804 device_init_wakeup(dev, 1);
1806 pr_info("%s: USB %s mode controller at %p using %s, IRQ %d\n",
1809 switch (pThis->board_mode) {
1810 case MUSB_HOST: s = "Host"; break;
1811 case MUSB_PERIPHERAL: s = "Peripheral"; break;
1812 default: s = "OTG"; break;
1815 (is_dma_capable() && pThis->pDmaController)
1819 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1820 /* host side needs more setup, except for no-host modes */
1821 if (pThis->board_mode != MUSB_PERIPHERAL) {
1822 struct usb_hcd *hcd = musb_to_hcd(pThis);
1824 if (pThis->board_mode == MUSB_OTG)
1825 hcd->self.otg_port = 1;
1826 pThis->xceiv.host = &hcd->self;
1827 hcd->power_budget = 2 * (plat->power ? : 250);
1829 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
1831 /* For the host-only role, we can activate right away.
1832 * (We expect the ID pin to be forcibly grounded!!)
1833 * Otherwise, wait till the gadget driver hooks up.
1835 if (!is_otg_enabled(pThis) && is_host_enabled(pThis)) {
1836 MUSB_HST_MODE(pThis);
1837 pThis->xceiv.default_a = 1;
1838 pThis->xceiv.state = OTG_STATE_A_IDLE;
1840 status = usb_add_hcd(musb_to_hcd(pThis), -1, 0);
1842 DBG(1, "%s mode, status %d, devctl %02x %c\n",
1844 musb_readb(pThis->pRegs, MGC_O_HDRC_DEVCTL),
1845 (musb_readb(pThis->pRegs, MGC_O_HDRC_DEVCTL)
1846 & MGC_M_DEVCTL_BDEVICE
1849 } else /* peripheral is enabled */ {
1850 MUSB_DEV_MODE(pThis);
1851 pThis->xceiv.default_a = 0;
1852 pThis->xceiv.state = OTG_STATE_B_IDLE;
1854 status = musb_gadget_setup(pThis);
1856 DBG(1, "%s mode, status %d, dev%02x\n",
1857 is_otg_enabled(pThis) ? "OTG" : "PERIPHERAL",
1859 musb_readb(pThis->pRegs, MGC_O_HDRC_DEVCTL));
1864 musb_debug_create("driver/musb_hdrc", pThis);
1868 clk_put(pThis->clock);
1869 device_init_wakeup(dev, 0);
1874 INIT_WORK(&pThis->irq_work, musb_irq_work);
1877 status = device_create_file(dev, &dev_attr_mode);
1878 status = device_create_file(dev, &dev_attr_cable);
1885 musb_platform_exit(pThis);
1889 /*-------------------------------------------------------------------------*/
1891 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
1892 * bridge to a platform device; this driver then suffices.
1895 #ifndef CONFIG_USB_INVENTRA_FIFO
1896 static u64 *orig_dma_mask;
1899 static int __init musb_probe(struct platform_device *pdev)
1901 struct device *dev = &pdev->dev;
1902 int irq = platform_get_irq(pdev, 0);
1903 struct resource *iomem;
1906 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1907 if (!iomem || irq == 0)
1910 base = ioremap(iomem->start, iomem->end - iomem->start + 1);
1912 dev_err(dev, "ioremap failed\n");
1916 #ifndef CONFIG_USB_INVENTRA_FIFO
1917 /* clobbered by use_dma=n */
1918 orig_dma_mask = dev->dma_mask;
1920 return musb_init_controller(dev, irq, base);
1923 static int __devexit musb_remove(struct platform_device *pdev)
1925 struct musb *musb = dev_to_musb(&pdev->dev);
1926 void __iomem *ctrl_base = musb->ctrl_base;
1928 /* this gets called on rmmod.
1929 * - Host mode: host may still be active
1930 * - Peripheral mode: peripheral is deactivated (or never-activated)
1931 * - OTG mode: both roles are deactivated (or never-activated)
1933 musb_shutdown(pdev);
1934 musb_debug_delete("driver/musb_hdrc", musb);
1935 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1936 if (musb->board_mode == MUSB_HOST)
1937 usb_remove_hcd(musb_to_hcd(musb));
1941 device_init_wakeup(&pdev->dev, 0);
1942 #ifndef CONFIG_USB_INVENTRA_FIFO
1943 pdev->dev.dma_mask = orig_dma_mask;
1950 static int musb_suspend(struct platform_device *pdev, pm_message_t message)
1952 unsigned long flags;
1953 struct musb *musb = dev_to_musb(&pdev->dev);
1958 spin_lock_irqsave(&musb->Lock, flags);
1960 if (is_peripheral_active(musb)) {
1961 /* FIXME force disconnect unless we know USB will wake
1962 * the system up quickly enough to respond ...
1964 } else if (is_host_active(musb)) {
1965 /* we know all the children are suspended; sometimes
1966 * they will even be wakeup-enabled.
1970 clk_disable(musb->clock);
1971 spin_unlock_irqrestore(&musb->Lock, flags);
1975 static int musb_resume(struct platform_device *pdev)
1977 unsigned long flags;
1978 struct musb *musb = dev_to_musb(&pdev->dev);
1983 spin_lock_irqsave(&musb->Lock, flags);
1984 clk_enable(musb->clock);
1985 /* for static cmos like DaVinci, register values were preserved
1986 * unless for some reason the whole soc powered down and we're
1987 * not treating that as a whole-system restart (e.g. swsusp)
1989 spin_unlock_irqrestore(&musb->Lock, flags);
1994 #define musb_suspend NULL
1995 #define musb_resume NULL
1998 static struct platform_driver musb_driver = {
2000 .name = (char *)musb_driver_name,
2001 .bus = &platform_bus_type,
2002 .owner = THIS_MODULE,
2004 .remove = __devexit_p(musb_remove),
2005 .shutdown = musb_shutdown,
2006 .suspend = musb_suspend,
2007 .resume = musb_resume,
2010 /*-------------------------------------------------------------------------*/
2012 static int __init musb_init(void)
2014 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2019 pr_info("%s: version " MUSB_VERSION ", "
2020 #ifdef CONFIG_USB_INVENTRA_FIFO
2022 #elif defined(CONFIG_USB_TI_CPPI_DMA)
2024 #elif defined(CONFIG_USB_INVENTRA_DMA)
2026 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
2032 #ifdef CONFIG_USB_MUSB_OTG
2033 "otg (peripheral+host)"
2034 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
2036 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2040 musb_driver_name, debug);
2041 return platform_driver_probe(&musb_driver, musb_probe);
2044 /* make us init after usbcore and before usb
2045 * gadget and host-side drivers start to register
2047 subsys_initcall(musb_init);
2049 static void __exit musb_cleanup(void)
2051 platform_driver_unregister(&musb_driver);
2053 module_exit(musb_cleanup);