2 * Copyright (C) 2005-2007 by Texas Instruments
3 * Some code has been taken from tusb6010.c
4 * Copyrights for that are attributable to:
5 * Copyright (C) 2006 Nokia Corporation
6 * Jarkko Nikula <jarkko.nikula@nokia.com>
7 * Tony Lindgren <tony@atomide.com>
9 * This file is part of the Inventra Controller Driver for Linux.
11 * The Inventra Controller Driver for Linux is free software; you
12 * can redistribute it and/or modify it under the terms of the GNU
13 * General Public License version 2 as published by the Free Software
16 * The Inventra Controller Driver for Linux is distributed in
17 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
18 * without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 * License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with The Inventra Controller Driver for Linux ; if not,
24 * write to the Free Software Foundation, Inc., 59 Temple Place,
25 * Suite 330, Boston, MA 02111-1307 USA
28 #include <linux/module.h>
29 #include <linux/kernel.h>
30 #include <linux/sched.h>
31 #include <linux/slab.h>
32 #include <linux/init.h>
33 #include <linux/list.h>
34 #include <linux/clk.h>
37 #include <asm/mach-types.h>
38 #include <asm/arch/hardware.h>
39 #include <asm/arch/mux.h>
41 #include "musb_core.h"
44 #ifdef CONFIG_ARCH_OMAP3430
45 #define get_cpu_rev() 2
48 #define MUSB_TIMEOUT_A_WAIT_BCON 1100
50 static struct timer_list musb_idle_timer;
52 static void musb_do_idle(unsigned long _musb)
54 struct musb *musb = (void *)_musb;
59 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
61 spin_lock_irqsave(&musb->lock, flags);
63 switch (musb->xceiv.state) {
64 case OTG_STATE_A_WAIT_BCON:
65 devctl &= ~MUSB_DEVCTL_SESSION;
66 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
68 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
69 if (devctl & MUSB_DEVCTL_BDEVICE) {
70 musb->xceiv.state = OTG_STATE_B_IDLE;
73 musb->xceiv.state = OTG_STATE_A_IDLE;
77 #ifdef CONFIG_USB_MUSB_HDRC_HCD
78 case OTG_STATE_A_SUSPEND:
79 /* finish RESUME signaling? */
80 if (musb->port1_status & MUSB_PORT_STAT_RESUME) {
81 power = musb_readb(musb->mregs, MUSB_POWER);
82 power &= ~MUSB_POWER_RESUME;
83 DBG(1, "root port resume stopped, power %02x\n", power);
84 musb_writeb(musb->mregs, MUSB_POWER, power);
86 musb->port1_status &= ~(USB_PORT_STAT_SUSPEND
87 | MUSB_PORT_STAT_RESUME);
88 musb->port1_status |= USB_PORT_STAT_C_SUSPEND << 16;
89 usb_hcd_poll_rh_status(musb_to_hcd(musb));
90 /* NOTE: it might really be A_WAIT_BCON ... */
91 musb->xceiv.state = OTG_STATE_A_HOST;
95 #ifdef CONFIG_USB_MUSB_HDRC_HCD
96 case OTG_STATE_A_HOST:
97 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
98 if (devctl & MUSB_DEVCTL_BDEVICE)
99 musb->xceiv.state = OTG_STATE_B_IDLE;
101 musb->xceiv.state = OTG_STATE_A_WAIT_BCON;
106 spin_unlock_irqrestore(&musb->lock, flags);
110 void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
112 unsigned long default_timeout = jiffies + msecs_to_jiffies(3);
113 static unsigned long last_timer;
116 timeout = default_timeout;
118 /* Never idle if active, or when VBUS timeout is not set as host */
119 if (musb->is_active || ((musb->a_wait_bcon == 0)
120 && (musb->xceiv.state == OTG_STATE_A_WAIT_BCON))) {
121 DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
122 del_timer(&musb_idle_timer);
123 last_timer = jiffies;
127 if (time_after(last_timer, timeout)) {
128 if (!timer_pending(&musb_idle_timer))
129 last_timer = timeout;
131 DBG(4, "Longer idle timer already pending, ignoring\n");
135 last_timer = timeout;
137 DBG(4, "%s inactive, for idle timer for %lu ms\n",
138 otg_state_string(musb),
139 (unsigned long)jiffies_to_msecs(timeout - jiffies));
140 mod_timer(&musb_idle_timer, timeout);
143 void musb_platform_enable(struct musb *musb)
146 void musb_platform_disable(struct musb *musb)
149 static void omap_vbus_power(struct musb *musb, int is_on, int sleeping)
153 static void omap_set_vbus(struct musb *musb, int is_on)
156 /* HDRC controls CPEN, but beware current surges during device
157 * connect. They can trigger transient overcurrent conditions
158 * that must be ignored.
161 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
165 musb->xceiv.default_a = 1;
166 musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
167 devctl |= MUSB_DEVCTL_SESSION;
173 /* NOTE: we're skipping A_WAIT_VFALL -> A_IDLE and
174 * jumping right to B_IDLE...
177 musb->xceiv.default_a = 0;
178 musb->xceiv.state = OTG_STATE_B_IDLE;
179 devctl &= ~MUSB_DEVCTL_SESSION;
183 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
185 DBG(1, "VBUS %s, devctl %02x "
186 /* otg %3x conf %08x prcm %08x */ "\n",
187 otg_state_string(musb),
188 musb_readb(musb->mregs, MUSB_DEVCTL));
190 static int omap_set_power(struct otg_transceiver *x, unsigned mA)
195 int musb_platform_resume(struct musb *musb);
197 void musb_platform_set_mode(struct musb *musb, u8 musb_mode)
199 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
201 devctl |= MUSB_DEVCTL_SESSION;
202 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
206 otg_set_host(&musb->xceiv, musb->xceiv.host);
208 case MUSB_PERIPHERAL:
209 otg_set_peripheral(&musb->xceiv, musb->xceiv.gadget);
216 int __init musb_platform_init(struct musb *musb)
218 struct otg_transceiver *xceiv = otg_get_transceiver();
220 #if defined(CONFIG_ARCH_OMAP2430)
221 omap_cfg_reg(AE5_2430_USB0HS_STP);
224 musb->xceiv = *xceiv;
225 musb_platform_resume(musb);
227 OTG_INTERFSEL_REG |= ULPI_12PIN;
229 pr_debug("HS USB OTG: revision 0x%x, sysconfig 0x%02x, "
230 "sysstatus 0x%x, intrfsel 0x%x, simenable 0x%x\n",
231 OTG_REVISION_REG, OTG_SYSCONFIG_REG, OTG_SYSSTATUS_REG,
232 OTG_INTERFSEL_REG, OTG_SIMENABLE_REG);
234 omap_vbus_power(musb, musb->board_mode == MUSB_HOST, 1);
236 if (is_host_enabled(musb))
237 musb->board_set_vbus = omap_set_vbus;
238 if (is_peripheral_enabled(musb))
239 musb->xceiv.set_power = omap_set_power;
240 musb->a_wait_bcon = MUSB_TIMEOUT_A_WAIT_BCON;
242 setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
247 int musb_platform_suspend(struct musb *musb)
250 OTG_FORCESTDBY_REG &= ~ENABLEFORCE; /* disable MSTANDBY */
251 OTG_SYSCONFIG_REG &= FORCESTDBY; /* enable force standby */
252 OTG_SYSCONFIG_REG &= ~AUTOIDLE; /* disable auto idle */
253 OTG_SYSCONFIG_REG |= SMARTIDLE; /* enable smart idle */
254 OTG_FORCESTDBY_REG |= ENABLEFORCE; /* enable MSTANDBY */
255 OTG_SYSCONFIG_REG |= AUTOIDLE; /* enable auto idle */
257 if (musb->xceiv.set_suspend)
258 musb->xceiv.set_suspend(&musb->xceiv, 1);
263 int musb_platform_resume(struct musb *musb)
265 if (musb->xceiv.set_suspend)
266 musb->xceiv.set_suspend(&musb->xceiv, 0);
268 OTG_FORCESTDBY_REG &= ~ENABLEFORCE; /* disable MSTANDBY */
269 OTG_SYSCONFIG_REG |= SMARTSTDBY; /* enable smart standby */
270 OTG_SYSCONFIG_REG &= ~AUTOIDLE; /* disable auto idle */
271 OTG_SYSCONFIG_REG |= SMARTIDLE; /* enable smart idle */
272 OTG_SYSCONFIG_REG |= AUTOIDLE; /* enable auto idle */
278 int musb_platform_exit(struct musb *musb)
281 omap_vbus_power(musb, 0 /*off*/, 1);
283 musb_platform_suspend(musb);
285 clk_put(musb->clock);