2 * MUSB OTG driver - support for Mentor's DMA controller
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2007 by Texas Instruments
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
24 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #include <linux/device.h>
34 #include <linux/interrupt.h>
35 #include <linux/platform_device.h>
36 #include "musb_core.h"
37 #include "musbhsdma.h"
39 static int dma_controller_start(struct dma_controller *c)
45 static void dma_channel_release(struct dma_channel *channel);
47 static int dma_controller_stop(struct dma_controller *c)
49 struct musb_dma_controller *controller = container_of(c,
50 struct musb_dma_controller, controller);
51 struct musb *musb = controller->private_data;
52 struct dma_channel *channel;
55 if (controller->used_channels != 0) {
56 dev_err(musb->controller,
57 "Stopping DMA controller while channel active\n");
59 for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
60 if (controller->used_channels & (1 << bit)) {
61 channel = &controller->channel[bit].channel;
62 dma_channel_release(channel);
64 if (!controller->used_channels)
73 static struct dma_channel *dma_channel_allocate(struct dma_controller *c,
74 struct musb_hw_ep *hw_ep, u8 transmit)
76 struct musb_dma_controller *controller = container_of(c,
77 struct musb_dma_controller, controller);
78 struct musb_dma_channel *musb_channel = NULL;
79 struct dma_channel *channel = NULL;
82 for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
83 if (!(controller->used_channels & (1 << bit))) {
84 controller->used_channels |= (1 << bit);
85 musb_channel = &(controller->channel[bit]);
86 musb_channel->controller = controller;
87 musb_channel->idx = bit;
88 musb_channel->epnum = hw_ep->epnum;
89 musb_channel->transmit = transmit;
90 channel = &(musb_channel->channel);
91 channel->private_data = musb_channel;
92 channel->status = MUSB_DMA_STATUS_FREE;
93 channel->max_len = 0x10000;
94 /* Tx => mode 1; Rx => mode 0 */
95 channel->desired_mode = transmit;
96 channel->actual_len = 0;
104 static void dma_channel_release(struct dma_channel *channel)
106 struct musb_dma_channel *musb_channel = channel->private_data;
108 channel->actual_len = 0;
109 musb_channel->start_addr = 0;
110 musb_channel->len = 0;
112 musb_channel->controller->used_channels &=
113 ~(1 << musb_channel->idx);
115 channel->status = MUSB_DMA_STATUS_UNKNOWN;
118 static void configure_channel(struct dma_channel *channel,
119 u16 packet_sz, u8 mode,
120 dma_addr_t dma_addr, u32 len)
122 struct musb_dma_channel *musb_channel = channel->private_data;
123 struct musb_dma_controller *controller = musb_channel->controller;
124 void __iomem *mbase = controller->base;
125 u8 bchannel = musb_channel->idx;
128 DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
129 channel, packet_sz, dma_addr, len, mode);
132 csr |= MUSB_HSDMA_BURSTMODE_INCR16;
133 else if (packet_sz >= 32)
134 csr |= MUSB_HSDMA_BURSTMODE_INCR8;
135 else if (packet_sz >= 16)
136 csr |= MUSB_HSDMA_BURSTMODE_INCR4;
138 csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
141 | MUSB_HSDMA_IRQENABLE
142 | (musb_channel->transmit
143 ? MUSB_HSDMA_TRANSMIT
147 musb_write_hsdma_addr(mbase, bchannel, dma_addr);
148 musb_write_hsdma_count(mbase, bchannel, len);
150 /* control (this should start things) */
152 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
156 static int dma_channel_program(struct dma_channel *channel,
157 u16 packet_sz, u8 mode,
158 dma_addr_t dma_addr, u32 len)
160 struct musb_dma_channel *musb_channel = channel->private_data;
162 DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
164 musb_channel->transmit ? "Tx" : "Rx",
165 packet_sz, dma_addr, len, mode);
167 BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
168 channel->status == MUSB_DMA_STATUS_BUSY);
170 channel->actual_len = 0;
171 musb_channel->start_addr = dma_addr;
172 musb_channel->len = len;
173 musb_channel->max_packet_sz = packet_sz;
174 channel->status = MUSB_DMA_STATUS_BUSY;
176 configure_channel(channel, packet_sz, mode, dma_addr, len);
181 static int dma_channel_abort(struct dma_channel *channel)
183 struct musb_dma_channel *musb_channel = channel->private_data;
184 void __iomem *mbase = musb_channel->controller->base;
186 u8 bchannel = musb_channel->idx;
189 if (channel->status == MUSB_DMA_STATUS_BUSY) {
190 if (musb_channel->transmit) {
192 csr = musb_readw(mbase,
193 MUSB_EP_OFFSET(musb_channel->epnum,
195 csr &= ~(MUSB_TXCSR_AUTOSET |
199 MUSB_EP_OFFSET(musb_channel->epnum, MUSB_TXCSR),
202 csr = musb_readw(mbase,
203 MUSB_EP_OFFSET(musb_channel->epnum,
205 csr &= ~(MUSB_RXCSR_AUTOCLEAR |
209 MUSB_EP_OFFSET(musb_channel->epnum, MUSB_RXCSR),
214 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
216 musb_write_hsdma_addr(mbase, bchannel, 0);
217 musb_write_hsdma_count(mbase, bchannel, 0);
218 channel->status = MUSB_DMA_STATUS_FREE;
224 static irqreturn_t dma_controller_irq(int irq, void *private_data)
226 struct musb_dma_controller *controller = private_data;
227 struct musb *musb = controller->private_data;
228 struct musb_dma_channel *musb_channel;
229 struct dma_channel *channel;
231 void __iomem *mbase = controller->base;
233 irqreturn_t retval = IRQ_NONE;
243 spin_lock_irqsave(&musb->lock, flags);
245 int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);
249 for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
250 if (int_hsdma & (1 << bchannel)) {
251 musb_channel = (struct musb_dma_channel *)
252 &(controller->channel[bchannel]);
253 channel = &musb_channel->channel;
255 csr = musb_readw(mbase,
256 MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
257 MUSB_HSDMA_CONTROL));
259 if (csr & MUSB_HSDMA_BUSERROR) {
260 musb_channel->channel.status =
261 MUSB_DMA_STATUS_BUS_ABORT;
265 addr = musb_read_hsdma_addr(mbase,
267 channel->actual_len = addr
268 - musb_channel->start_addr;
270 DBG(2, "ch %p, 0x%x -> 0x%x (%d / %d) %s\n",
271 channel, musb_channel->start_addr,
272 addr, channel->actual_len,
275 < musb_channel->len) ?
276 "=> reconfig 0" : "=> complete");
278 devctl = musb_readb(mbase, MUSB_DEVCTL);
280 channel->status = MUSB_DMA_STATUS_FREE;
283 if ((devctl & MUSB_DEVCTL_HM)
284 && (musb_channel->transmit)
285 && ((channel->desired_mode == 0)
286 || (channel->actual_len &
287 (musb_channel->max_packet_sz - 1)))
289 /* Send out the packet */
290 musb_ep_select(mbase,
291 musb_channel->epnum);
292 musb_writew(mbase, MUSB_EP_OFFSET(
295 MUSB_TXCSR_TXPKTRDY);
300 musb_channel->transmit);
306 #ifdef CONFIG_BLACKFIN
307 /* Clear DMA interrup flags */
308 musb_writeb(mbase, MUSB_HSDMA_INTR, int_hsdma);
311 retval = IRQ_HANDLED;
313 spin_unlock_irqrestore(&musb->lock, flags);
317 void dma_controller_destroy(struct dma_controller *c)
319 struct musb_dma_controller *controller = container_of(c,
320 struct musb_dma_controller, controller);
326 free_irq(controller->irq, c);
331 struct dma_controller *__init
332 dma_controller_create(struct musb *musb, void __iomem *base)
334 struct musb_dma_controller *controller;
335 struct device *dev = musb->controller;
336 struct platform_device *pdev = to_platform_device(dev);
337 int irq = platform_get_irq(pdev, 1);
340 dev_err(dev, "No DMA interrupt line!\n");
344 controller = kzalloc(sizeof(*controller), GFP_KERNEL);
348 controller->channel_count = MUSB_HSDMA_CHANNELS;
349 controller->private_data = musb;
350 controller->base = base;
352 controller->controller.start = dma_controller_start;
353 controller->controller.stop = dma_controller_stop;
354 controller->controller.channel_alloc = dma_channel_allocate;
355 controller->controller.channel_release = dma_channel_release;
356 controller->controller.channel_program = dma_channel_program;
357 controller->controller.channel_abort = dma_channel_abort;
359 if (request_irq(irq, dma_controller_irq, IRQF_DISABLED,
360 musb->controller->bus_id, &controller->controller)) {
361 dev_err(dev, "request_irq %d failed!\n", irq);
362 dma_controller_destroy(&controller->controller);
367 controller->irq = irq;
369 return &controller->controller;