2 * MUSB OTG driver peripheral support
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #include <linux/kernel.h>
36 #include <linux/list.h>
37 #include <linux/timer.h>
38 #include <linux/module.h>
39 #include <linux/smp.h>
40 #include <linux/spinlock.h>
41 #include <linux/delay.h>
42 #include <linux/moduleparam.h>
43 #include <linux/stat.h>
44 #include <linux/dma-mapping.h>
46 #include "musb_core.h"
49 /* MUSB PERIPHERAL status 3-mar-2006:
51 * - EP0 seems solid. It passes both USBCV and usbtest control cases.
54 * + remote wakeup to Linux hosts work, but saw USBCV failures;
55 * in one test run (operator error?)
56 * + endpoint halt tests -- in both usbtest and usbcv -- seem
57 * to break when dma is enabled ... is something wrongly
60 * - Mass storage behaved ok when last tested. Network traffic patterns
61 * (with lots of short transfers etc) need retesting; they turn up the
62 * worst cases of the DMA, since short packets are typical but are not
66 * + both pio and dma behave in with network and g_zero tests
67 * + no cppi throughput issues other than no-hw-queueing
68 * + failed with FLAT_REG (DaVinci)
69 * + seems to behave with double buffering, PIO -and- CPPI
70 * + with gadgetfs + AIO, requests got lost?
73 * + both pio and dma behave in with network and g_zero tests
74 * + dma is slow in typical case (short_not_ok is clear)
75 * + double buffering ok with PIO
76 * + double buffering *FAILS* with CPPI, wrong data bytes sometimes
77 * + request lossage observed with gadgetfs
79 * - ISO not tested ... might work, but only weakly isochronous
81 * - Gadget driver disabling of softconnect during bind() is ignored; so
82 * drivers can't hold off host requests until userspace is ready.
83 * (Workaround: they can turn it off later.)
85 * - PORTABILITY (assumes PIO works):
86 * + DaVinci, basically works with cppi dma
87 * + OMAP 2430, ditto with mentor dma
88 * + TUSB 6010, platform-specific dma in the works
91 /* ----------------------------------------------------------------------- */
94 * Immediately complete a request.
96 * @param request the request to complete
97 * @param status the status to complete the request with
98 * Context: controller locked, IRQs blocked.
100 void musb_g_giveback(
102 struct usb_request *request,
104 __releases(ep->musb->lock)
105 __acquires(ep->musb->lock)
107 struct musb_request *req;
111 req = to_musb_request(request);
113 list_del(&request->list);
114 if (req->request.status == -EINPROGRESS)
115 req->request.status = status;
119 spin_unlock(&musb->lock);
120 if (is_dma_capable()) {
122 dma_unmap_single(musb->controller,
128 req->request.dma = DMA_ADDR_INVALID;
130 } else if (req->request.dma != DMA_ADDR_INVALID)
131 dma_sync_single_for_cpu(musb->controller,
138 if (request->status == 0)
139 DBG(5, "%s done request %p, %d/%d\n",
140 ep->end_point.name, request,
141 req->request.actual, req->request.length);
143 DBG(2, "%s request %p, %d/%d fault %d\n",
144 ep->end_point.name, request,
145 req->request.actual, req->request.length,
147 req->request.complete(&req->ep->end_point, &req->request);
148 spin_lock(&musb->lock);
152 /* ----------------------------------------------------------------------- */
155 * Abort requests queued to an endpoint using the status. Synchronous.
156 * caller locked controller and blocked irqs, and selected this ep.
158 static void nuke(struct musb_ep *ep, const int status)
160 struct musb_request *req = NULL;
161 void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs;
165 if (is_dma_capable() && ep->dma) {
166 struct dma_controller *c = ep->musb->dma_controller;
169 musb_writew(epio, MUSB_TXCSR,
170 0 | MUSB_TXCSR_FLUSHFIFO);
171 musb_writew(epio, MUSB_TXCSR,
172 0 | MUSB_TXCSR_FLUSHFIFO);
174 musb_writew(epio, MUSB_RXCSR,
175 0 | MUSB_RXCSR_FLUSHFIFO);
176 musb_writew(epio, MUSB_RXCSR,
177 0 | MUSB_RXCSR_FLUSHFIFO);
180 value = c->channel_abort(ep->dma);
181 DBG(value ? 1 : 6, "%s: abort DMA --> %d\n", ep->name, value);
182 c->channel_release(ep->dma);
186 while (!list_empty(&(ep->req_list))) {
187 req = container_of(ep->req_list.next, struct musb_request,
189 musb_g_giveback(ep, &req->request, status);
193 /* ----------------------------------------------------------------------- */
195 /* Data transfers - pure PIO, pure DMA, or mixed mode */
198 * This assumes the separate CPPI engine is responding to DMA requests
199 * from the usb core ... sequenced a bit differently from mentor dma.
202 static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep)
204 if (can_bulk_split(musb, ep->type))
205 return ep->hw_ep->max_packet_sz_tx;
207 return ep->packet_sz;
211 #ifdef CONFIG_USB_INVENTRA_DMA
213 /* Peripheral tx (IN) using Mentor DMA works as follows:
214 Only mode 0 is used for transfers <= wPktSize,
215 mode 1 is used for larger transfers,
217 One of the following happens:
218 - Host sends IN token which causes an endpoint interrupt
220 -> if DMA is currently busy, exit.
221 -> if queue is non-empty, txstate().
223 - Request is queued by the gadget driver.
224 -> if queue was previously empty, txstate()
229 | (data is transferred to the FIFO, then sent out when
230 | IN token(s) are recd from Host.
231 | -> DMA interrupt on completion
233 | -> stop DMA, ~DmaEenab,
234 | -> set TxPktRdy for last short pkt or zlp
235 | -> Complete Request
236 | -> Continue next request (call txstate)
237 |___________________________________|
239 * Non-Mentor DMA engines can of course work differently, such as by
240 * upleveling from irq-per-packet to irq-per-buffer.
246 * An endpoint is transmitting data. This can be called either from
247 * the IRQ routine or from ep.queue() to kickstart a request on an
250 * Context: controller locked, IRQs blocked, endpoint selected
252 static void txstate(struct musb *musb, struct musb_request *req)
254 u8 epnum = req->epnum;
255 struct musb_ep *musb_ep;
256 void __iomem *epio = musb->endpoints[epnum].regs;
257 struct usb_request *request;
258 u16 fifo_count = 0, csr;
263 /* we shouldn't get here while DMA is active ... but we do ... */
264 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
265 DBG(4, "dma pending...\n");
269 /* read TXCSR before */
270 csr = musb_readw(epio, MUSB_TXCSR);
272 request = &req->request;
273 fifo_count = min(max_ep_writesize(musb, musb_ep),
274 (int)(request->length - request->actual));
276 if (csr & MUSB_TXCSR_TXPKTRDY) {
277 DBG(5, "%s old packet still ready , txcsr %03x\n",
278 musb_ep->end_point.name, csr);
282 if (csr & MUSB_TXCSR_P_SENDSTALL) {
283 DBG(5, "%s stalling, txcsr %03x\n",
284 musb_ep->end_point.name, csr);
288 DBG(4, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n",
289 epnum, musb_ep->packet_sz, fifo_count,
292 #ifndef CONFIG_MUSB_PIO_ONLY
293 if (is_dma_capable() && musb_ep->dma) {
294 struct dma_controller *c = musb->dma_controller;
296 use_dma = (request->dma != DMA_ADDR_INVALID);
298 /* MUSB_TXCSR_P_ISO is still set correctly */
300 #ifdef CONFIG_USB_INVENTRA_DMA
304 /* setup DMA, then program endpoint CSR */
305 request_size = min(request->length,
306 musb_ep->dma->max_len);
307 if (request_size <= musb_ep->packet_sz)
308 musb_ep->dma->desired_mode = 0;
310 musb_ep->dma->desired_mode = 1;
312 use_dma = use_dma && c->channel_program(
313 musb_ep->dma, musb_ep->packet_sz,
314 musb_ep->dma->desired_mode,
315 request->dma, request_size);
317 if (musb_ep->dma->desired_mode == 0) {
318 /* ASSERT: DMAENAB is clear */
319 csr &= ~(MUSB_TXCSR_AUTOSET |
321 csr |= (MUSB_TXCSR_DMAENAB |
323 /* against programming guide */
326 csr |= (MUSB_TXCSR_AUTOSET
331 csr &= ~MUSB_TXCSR_P_UNDERRUN;
332 musb_writew(epio, MUSB_TXCSR, csr);
336 #elif defined(CONFIG_USB_TI_CPPI_DMA)
337 /* program endpoint CSR first, then setup DMA */
338 csr &= ~(MUSB_TXCSR_AUTOSET
340 | MUSB_TXCSR_P_UNDERRUN
341 | MUSB_TXCSR_TXPKTRDY);
342 csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_DMAENAB;
343 musb_writew(epio, MUSB_TXCSR,
344 (MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN)
347 /* ensure writebuffer is empty */
348 csr = musb_readw(epio, MUSB_TXCSR);
350 /* NOTE host side sets DMAENAB later than this; both are
351 * OK since the transfer dma glue (between CPPI and Mentor
352 * fifos) just tells CPPI it could start. Data only moves
353 * to the USB TX fifo when both fifos are ready.
356 /* "mode" is irrelevant here; handle terminating ZLPs like
357 * PIO does, since the hardware RNDIS mode seems unreliable
358 * except for the last-packet-is-already-short case.
360 use_dma = use_dma && c->channel_program(
361 musb_ep->dma, musb_ep->packet_sz,
366 c->channel_release(musb_ep->dma);
368 /* ASSERT: DMAENAB clear */
369 csr &= ~(MUSB_TXCSR_DMAMODE | MUSB_TXCSR_MODE);
370 /* invariant: prequest->buf is non-null */
372 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
373 use_dma = use_dma && c->channel_program(
374 musb_ep->dma, musb_ep->packet_sz,
383 musb_write_fifo(musb_ep->hw_ep, fifo_count,
384 (u8 *) (request->buf + request->actual));
385 request->actual += fifo_count;
386 csr |= MUSB_TXCSR_TXPKTRDY;
387 csr &= ~MUSB_TXCSR_P_UNDERRUN;
388 musb_writew(epio, MUSB_TXCSR, csr);
391 /* host may already have the data when this message shows... */
392 DBG(3, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n",
393 musb_ep->end_point.name, use_dma ? "dma" : "pio",
394 request->actual, request->length,
395 musb_readw(epio, MUSB_TXCSR),
397 musb_readw(epio, MUSB_TXMAXP));
401 * FIFO state update (e.g. data ready).
402 * Called from IRQ, with controller locked.
404 void musb_g_tx(struct musb *musb, u8 epnum)
407 struct usb_request *request;
408 u8 __iomem *mbase = musb->mregs;
409 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in;
410 void __iomem *epio = musb->endpoints[epnum].regs;
411 struct dma_channel *dma;
413 musb_ep_select(mbase, epnum);
414 request = next_request(musb_ep);
416 csr = musb_readw(epio, MUSB_TXCSR);
417 DBG(4, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr);
419 dma = is_dma_capable() ? musb_ep->dma : NULL;
421 /* REVISIT for high bandwidth, MUSB_TXCSR_P_INCOMPTX
422 * probably rates reporting as a host error
424 if (csr & MUSB_TXCSR_P_SENTSTALL) {
425 csr |= MUSB_TXCSR_P_WZC_BITS;
426 csr &= ~MUSB_TXCSR_P_SENTSTALL;
427 musb_writew(epio, MUSB_TXCSR, csr);
428 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
429 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
430 musb->dma_controller->channel_abort(dma);
434 musb_g_giveback(musb_ep, request, -EPIPE);
439 if (csr & MUSB_TXCSR_P_UNDERRUN) {
440 /* we NAKed, no big deal ... little reason to care */
441 csr |= MUSB_TXCSR_P_WZC_BITS;
442 csr &= ~(MUSB_TXCSR_P_UNDERRUN
443 | MUSB_TXCSR_TXPKTRDY);
444 musb_writew(epio, MUSB_TXCSR, csr);
445 DBG(20, "underrun on ep%d, req %p\n", epnum, request);
448 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
449 /* SHOULD NOT HAPPEN ... has with cppi though, after
450 * changing SENDSTALL (and other cases); harmless?
452 DBG(5, "%s dma still busy?\n", musb_ep->end_point.name);
459 if (dma && (csr & MUSB_TXCSR_DMAENAB)) {
461 csr |= MUSB_TXCSR_P_WZC_BITS;
462 csr &= ~(MUSB_TXCSR_DMAENAB
463 | MUSB_TXCSR_P_UNDERRUN
464 | MUSB_TXCSR_TXPKTRDY);
465 musb_writew(epio, MUSB_TXCSR, csr);
466 /* ensure writebuffer is empty */
467 csr = musb_readw(epio, MUSB_TXCSR);
468 request->actual += musb_ep->dma->actual_len;
469 DBG(4, "TXCSR%d %04x, dma off, "
472 musb_ep->dma->actual_len,
476 if (is_dma || request->actual == request->length) {
478 /* First, maybe a terminating short packet.
479 * Some DMA engines might handle this by
485 % musb_ep->packet_sz)
487 #ifdef CONFIG_USB_INVENTRA_DMA
489 ((!dma->desired_mode) ||
491 (musb_ep->packet_sz - 1))))
494 /* on dma completion, fifo may not
495 * be available yet ...
497 if (csr & MUSB_TXCSR_TXPKTRDY)
500 DBG(4, "sending zero pkt\n");
501 musb_writew(epio, MUSB_TXCSR,
503 | MUSB_TXCSR_TXPKTRDY);
507 /* ... or if not, then complete it */
508 musb_g_giveback(musb_ep, request, 0);
510 /* kickstart next transfer if appropriate;
511 * the packet that just completed might not
512 * be transmitted for hours or days.
513 * REVISIT for double buffering...
514 * FIXME revisit for stalls too...
516 musb_ep_select(mbase, epnum);
517 csr = musb_readw(epio, MUSB_TXCSR);
518 if (csr & MUSB_TXCSR_FIFONOTEMPTY)
520 request = musb_ep->desc
521 ? next_request(musb_ep)
524 DBG(4, "%s idle now\n",
525 musb_ep->end_point.name);
530 txstate(musb, to_musb_request(request));
536 /* ------------------------------------------------------------ */
538 #ifdef CONFIG_USB_INVENTRA_DMA
540 /* Peripheral rx (OUT) using Mentor DMA works as follows:
541 - Only mode 0 is used.
543 - Request is queued by the gadget class driver.
544 -> if queue was previously empty, rxstate()
546 - Host sends OUT token which causes an endpoint interrupt
548 | -> if request queued, call rxstate
550 | | -> DMA interrupt on completion
554 | | -> if data recd = max expected
555 | | by the request, or host
556 | | sent a short packet,
557 | | complete the request,
558 | | and start the next one.
559 | |_____________________________________|
560 | else just wait for the host
561 | to send the next OUT token.
562 |__________________________________________________|
564 * Non-Mentor DMA engines can of course work differently.
570 * Context: controller locked, IRQs blocked, endpoint selected
572 static void rxstate(struct musb *musb, struct musb_request *req)
575 const u8 epnum = req->epnum;
576 struct usb_request *request = &req->request;
577 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_out;
578 void __iomem *epio = musb->endpoints[epnum].regs;
580 u16 len = musb_ep->packet_sz;
582 csr = musb_readw(epio, MUSB_RXCSR);
584 if (is_cppi_enabled() && musb_ep->dma) {
585 struct dma_controller *c = musb->dma_controller;
586 struct dma_channel *channel = musb_ep->dma;
588 /* NOTE: CPPI won't actually stop advancing the DMA
589 * queue after short packet transfers, so this is almost
590 * always going to run as IRQ-per-packet DMA so that
591 * faults will be handled correctly.
593 if (c->channel_program(channel,
595 !request->short_not_ok,
596 request->dma + request->actual,
597 request->length - request->actual)) {
599 /* make sure that if an rxpkt arrived after the irq,
600 * the cppi engine will be ready to take it as soon
603 csr &= ~(MUSB_RXCSR_AUTOCLEAR
604 | MUSB_RXCSR_DMAMODE);
605 csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS;
606 musb_writew(epio, MUSB_RXCSR, csr);
611 if (csr & MUSB_RXCSR_RXPKTRDY) {
612 len = musb_readw(epio, MUSB_RXCOUNT);
613 if (request->actual < request->length) {
614 #ifdef CONFIG_USB_INVENTRA_DMA
615 if (is_dma_capable() && musb_ep->dma) {
616 struct dma_controller *c;
617 struct dma_channel *channel;
620 c = musb->dma_controller;
621 channel = musb_ep->dma;
623 /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in
624 * mode 0 only. So we do not get endpoint interrupts due to DMA
625 * completion. We only get interrupts from DMA controller.
627 * We could operate in DMA mode 1 if we knew the size of the tranfer
628 * in advance. For mass storage class, request->length = what the host
629 * sends, so that'd work. But for pretty much everything else,
630 * request->length is routinely more than what the host sends. For
631 * most these gadgets, end of is signified either by a short packet,
632 * or filling the last byte of the buffer. (Sending extra data in
633 * that last pckate should trigger an overflow fault.) But in mode 1,
634 * we don't get DMA completion interrrupt for short packets.
636 * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1),
637 * to get endpoint interrupt on every DMA req, but that didn't seem
640 * REVISIT an updated g_file_storage can set req->short_not_ok, which
641 * then becomes usable as a runtime "use mode 1" hint...
644 csr |= MUSB_RXCSR_DMAENAB;
646 csr |= MUSB_RXCSR_AUTOCLEAR;
647 /* csr |= MUSB_RXCSR_DMAMODE; */
649 /* this special sequence (enabling and then
650 * disabling MUSB_RXCSR_DMAMODE) is required
651 * to get DMAReq to activate
653 musb_writew(epio, MUSB_RXCSR,
654 csr | MUSB_RXCSR_DMAMODE);
656 musb_writew(epio, MUSB_RXCSR, csr);
658 if (request->actual < request->length) {
659 int transfer_size = 0;
661 transfer_size = min(request->length,
666 if (transfer_size <= musb_ep->packet_sz)
667 musb_ep->dma->desired_mode = 0;
669 musb_ep->dma->desired_mode = 1;
671 use_dma = c->channel_program(
674 channel->desired_mode,
683 #endif /* Mentor's DMA */
685 fifo_count = request->length - request->actual;
686 DBG(3, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n",
687 musb_ep->end_point.name,
691 fifo_count = min(len, fifo_count);
693 #ifdef CONFIG_USB_TUSB_OMAP_DMA
694 if (tusb_dma_omap() && musb_ep->dma) {
695 struct dma_controller *c = musb->dma_controller;
696 struct dma_channel *channel = musb_ep->dma;
697 u32 dma_addr = request->dma + request->actual;
700 ret = c->channel_program(channel,
702 channel->desired_mode,
710 musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
711 (request->buf + request->actual));
712 request->actual += fifo_count;
714 /* REVISIT if we left anything in the fifo, flush
715 * it and report -EOVERFLOW
719 csr |= MUSB_RXCSR_P_WZC_BITS;
720 csr &= ~MUSB_RXCSR_RXPKTRDY;
721 musb_writew(epio, MUSB_RXCSR, csr);
725 /* reach the end or short packet detected */
726 if (request->actual == request->length || len < musb_ep->packet_sz)
727 musb_g_giveback(musb_ep, request, 0);
731 * Data ready for a request; called from IRQ
733 void musb_g_rx(struct musb *musb, u8 epnum)
736 struct usb_request *request;
737 void __iomem *mbase = musb->mregs;
738 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_out;
739 void __iomem *epio = musb->endpoints[epnum].regs;
740 struct dma_channel *dma;
742 musb_ep_select(mbase, epnum);
744 request = next_request(musb_ep);
746 csr = musb_readw(epio, MUSB_RXCSR);
747 dma = is_dma_capable() ? musb_ep->dma : NULL;
749 DBG(4, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name,
750 csr, dma ? " (dma)" : "", request);
752 if (csr & MUSB_RXCSR_P_SENTSTALL) {
753 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
754 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
755 (void) musb->dma_controller->channel_abort(dma);
756 request->actual += musb_ep->dma->actual_len;
759 csr |= MUSB_RXCSR_P_WZC_BITS;
760 csr &= ~MUSB_RXCSR_P_SENTSTALL;
761 musb_writew(epio, MUSB_RXCSR, csr);
764 musb_g_giveback(musb_ep, request, -EPIPE);
768 if (csr & MUSB_RXCSR_P_OVERRUN) {
769 /* csr |= MUSB_RXCSR_P_WZC_BITS; */
770 csr &= ~MUSB_RXCSR_P_OVERRUN;
771 musb_writew(epio, MUSB_RXCSR, csr);
773 DBG(3, "%s iso overrun on %p\n", musb_ep->name, request);
774 if (request && request->status == -EINPROGRESS)
775 request->status = -EOVERFLOW;
777 if (csr & MUSB_RXCSR_INCOMPRX) {
778 /* REVISIT not necessarily an error */
779 DBG(4, "%s, incomprx\n", musb_ep->end_point.name);
782 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
783 /* "should not happen"; likely RXPKTRDY pending for DMA */
784 DBG((csr & MUSB_RXCSR_DMAENAB) ? 4 : 1,
785 "%s busy, csr %04x\n",
786 musb_ep->end_point.name, csr);
790 if (dma && (csr & MUSB_RXCSR_DMAENAB)) {
791 csr &= ~(MUSB_RXCSR_AUTOCLEAR
793 | MUSB_RXCSR_DMAMODE);
794 musb_writew(epio, MUSB_RXCSR,
795 MUSB_RXCSR_P_WZC_BITS | csr);
797 request->actual += musb_ep->dma->actual_len;
799 DBG(4, "RXCSR%d %04x, dma off, %04x, len %Zd, req %p\n",
801 musb_readw(epio, MUSB_RXCSR),
802 musb_ep->dma->actual_len, request);
804 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA)
805 /* Autoclear doesn't clear RxPktRdy for short packets */
806 if ((dma->desired_mode == 0)
808 & (musb_ep->packet_sz - 1))) {
810 csr &= ~MUSB_RXCSR_RXPKTRDY;
811 musb_writew(epio, MUSB_RXCSR, csr);
814 /* incomplete, and not short? wait for next IN packet */
815 if ((request->actual < request->length)
816 && (musb_ep->dma->actual_len
817 == musb_ep->packet_sz))
820 musb_g_giveback(musb_ep, request, 0);
822 request = next_request(musb_ep);
826 /* don't start more i/o till the stall clears */
827 musb_ep_select(mbase, epnum);
828 csr = musb_readw(epio, MUSB_RXCSR);
829 if (csr & MUSB_RXCSR_P_SENDSTALL)
834 /* analyze request if the ep is hot */
836 rxstate(musb, to_musb_request(request));
838 DBG(3, "packet waiting for %s%s request\n",
839 musb_ep->desc ? "" : "inactive ",
840 musb_ep->end_point.name);
846 /* ------------------------------------------------------------ */
848 static int musb_gadget_enable(struct usb_ep *ep,
849 const struct usb_endpoint_descriptor *desc)
852 struct musb_ep *musb_ep;
853 struct musb_hw_ep *hw_ep;
860 int status = -EINVAL;
865 musb_ep = to_musb_ep(ep);
866 hw_ep = musb_ep->hw_ep;
868 musb = musb_ep->musb;
870 epnum = musb_ep->current_epnum;
872 spin_lock_irqsave(&musb->lock, flags);
878 musb_ep->type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
880 /* check direction and (later) maxpacket size against endpoint */
881 if ((desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK) != epnum)
884 /* REVISIT this rules out high bandwidth periodic transfers */
885 tmp = le16_to_cpu(desc->wMaxPacketSize);
888 musb_ep->packet_sz = tmp;
890 /* enable the interrupts for the endpoint, set the endpoint
891 * packet size (or fail), set the mode, clear the fifo
893 musb_ep_select(mbase, epnum);
894 if (desc->bEndpointAddress & USB_DIR_IN) {
895 u16 int_txe = musb_readw(mbase, MUSB_INTRTXE);
897 if (hw_ep->is_shared_fifo)
901 if (tmp > hw_ep->max_packet_sz_tx)
904 int_txe |= (1 << epnum);
905 musb_writew(mbase, MUSB_INTRTXE, int_txe);
907 /* REVISIT if can_bulk_split(), use by updating "tmp";
908 * likewise high bandwidth periodic tx
910 musb_writew(regs, MUSB_TXMAXP, tmp);
912 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG;
913 if (musb_readw(regs, MUSB_TXCSR)
914 & MUSB_TXCSR_FIFONOTEMPTY)
915 csr |= MUSB_TXCSR_FLUSHFIFO;
916 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
917 csr |= MUSB_TXCSR_P_ISO;
919 /* set twice in case of double buffering */
920 musb_writew(regs, MUSB_TXCSR, csr);
921 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
922 musb_writew(regs, MUSB_TXCSR, csr);
925 u16 int_rxe = musb_readw(mbase, MUSB_INTRRXE);
927 if (hw_ep->is_shared_fifo)
931 if (tmp > hw_ep->max_packet_sz_rx)
934 int_rxe |= (1 << epnum);
935 musb_writew(mbase, MUSB_INTRRXE, int_rxe);
937 /* REVISIT if can_bulk_combine() use by updating "tmp"
938 * likewise high bandwidth periodic rx
940 musb_writew(regs, MUSB_RXMAXP, tmp);
942 /* force shared fifo to OUT-only mode */
943 if (hw_ep->is_shared_fifo) {
944 csr = musb_readw(regs, MUSB_TXCSR);
945 csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY);
946 musb_writew(regs, MUSB_TXCSR, csr);
949 csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG;
950 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
951 csr |= MUSB_RXCSR_P_ISO;
952 else if (musb_ep->type == USB_ENDPOINT_XFER_INT)
953 csr |= MUSB_RXCSR_DISNYET;
955 /* set twice in case of double buffering */
956 musb_writew(regs, MUSB_RXCSR, csr);
957 musb_writew(regs, MUSB_RXCSR, csr);
960 /* NOTE: all the I/O code _should_ work fine without DMA, in case
961 * for some reason you run out of channels here.
963 if (is_dma_capable() && musb->dma_controller) {
964 struct dma_controller *c = musb->dma_controller;
966 musb_ep->dma = c->channel_alloc(c, hw_ep,
967 (desc->bEndpointAddress & USB_DIR_IN));
971 musb_ep->desc = desc;
975 pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
976 musb_driver_name, musb_ep->end_point.name,
977 ({ char *s; switch (musb_ep->type) {
978 case USB_ENDPOINT_XFER_BULK: s = "bulk"; break;
979 case USB_ENDPOINT_XFER_INT: s = "int"; break;
980 default: s = "iso"; break;
982 musb_ep->is_in ? "IN" : "OUT",
983 musb_ep->dma ? "dma, " : "",
986 schedule_work(&musb->irq_work);
989 spin_unlock_irqrestore(&musb->lock, flags);
994 * Disable an endpoint flushing all requests queued.
996 static int musb_gadget_disable(struct usb_ep *ep)
1001 struct musb_ep *musb_ep;
1005 musb_ep = to_musb_ep(ep);
1006 musb = musb_ep->musb;
1007 epnum = musb_ep->current_epnum;
1008 epio = musb->endpoints[epnum].regs;
1010 spin_lock_irqsave(&musb->lock, flags);
1011 musb_ep_select(musb->mregs, epnum);
1013 /* zero the endpoint sizes */
1014 if (musb_ep->is_in) {
1015 u16 int_txe = musb_readw(musb->mregs, MUSB_INTRTXE);
1016 int_txe &= ~(1 << epnum);
1017 musb_writew(musb->mregs, MUSB_INTRTXE, int_txe);
1018 musb_writew(epio, MUSB_TXMAXP, 0);
1020 u16 int_rxe = musb_readw(musb->mregs, MUSB_INTRRXE);
1021 int_rxe &= ~(1 << epnum);
1022 musb_writew(musb->mregs, MUSB_INTRRXE, int_rxe);
1023 musb_writew(epio, MUSB_RXMAXP, 0);
1026 musb_ep->desc = NULL;
1028 /* abort all pending DMA and requests */
1029 nuke(musb_ep, -ESHUTDOWN);
1031 schedule_work(&musb->irq_work);
1033 spin_unlock_irqrestore(&(musb->lock), flags);
1035 DBG(2, "%s\n", musb_ep->end_point.name);
1041 * Allocate a request for an endpoint.
1042 * Reused by ep0 code.
1044 struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1046 struct musb_ep *musb_ep = to_musb_ep(ep);
1047 struct musb_request *request = NULL;
1049 request = kzalloc(sizeof *request, gfp_flags);
1051 INIT_LIST_HEAD(&request->request.list);
1052 request->request.dma = DMA_ADDR_INVALID;
1053 request->epnum = musb_ep->current_epnum;
1054 request->ep = musb_ep;
1057 return &request->request;
1062 * Reused by ep0 code.
1064 void musb_free_request(struct usb_ep *ep, struct usb_request *req)
1066 kfree(to_musb_request(req));
1069 static LIST_HEAD(buffers);
1071 struct free_record {
1072 struct list_head list;
1079 * Context: controller locked, IRQs blocked.
1081 static void musb_ep_restart(struct musb *musb, struct musb_request *req)
1083 DBG(3, "<== %s request %p len %u on hw_ep%d\n",
1084 req->tx ? "TX/IN" : "RX/OUT",
1085 &req->request, req->request.length, req->epnum);
1087 musb_ep_select(musb->mregs, req->epnum);
1094 static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req,
1097 struct musb_ep *musb_ep;
1098 struct musb_request *request;
1101 unsigned long lockflags;
1108 musb_ep = to_musb_ep(ep);
1109 musb = musb_ep->musb;
1111 request = to_musb_request(req);
1112 request->musb = musb;
1114 if (request->ep != musb_ep)
1117 DBG(4, "<== to %s request=%p\n", ep->name, req);
1119 /* request is mine now... */
1120 request->request.actual = 0;
1121 request->request.status = -EINPROGRESS;
1122 request->epnum = musb_ep->current_epnum;
1123 request->tx = musb_ep->is_in;
1125 if (is_dma_capable() && musb_ep->dma) {
1126 if (request->request.dma == DMA_ADDR_INVALID) {
1127 request->request.dma = dma_map_single(
1129 request->request.buf,
1130 request->request.length,
1134 request->mapped = 1;
1136 dma_sync_single_for_device(musb->controller,
1137 request->request.dma,
1138 request->request.length,
1142 request->mapped = 0;
1144 } else if (!req->buf) {
1147 request->mapped = 0;
1149 spin_lock_irqsave(&musb->lock, lockflags);
1151 /* don't queue if the ep is down */
1152 if (!musb_ep->desc) {
1153 DBG(4, "req %p queued to %s while ep %s\n",
1154 req, ep->name, "disabled");
1155 status = -ESHUTDOWN;
1159 /* add request to the list */
1160 list_add_tail(&(request->request.list), &(musb_ep->req_list));
1162 /* it this is the head of the queue, start i/o ... */
1163 if (!musb_ep->busy && &request->request.list == musb_ep->req_list.next)
1164 musb_ep_restart(musb, request);
1167 spin_unlock_irqrestore(&musb->lock, lockflags);
1171 static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request)
1173 struct musb_ep *musb_ep = to_musb_ep(ep);
1174 struct usb_request *r;
1175 unsigned long flags;
1177 struct musb *musb = musb_ep->musb;
1179 if (!ep || !request || to_musb_request(request)->ep != musb_ep)
1182 spin_lock_irqsave(&musb->lock, flags);
1184 list_for_each_entry(r, &musb_ep->req_list, list) {
1189 DBG(3, "request %p not queued to %s\n", request, ep->name);
1194 /* if the hardware doesn't have the request, easy ... */
1195 if (musb_ep->req_list.next != &request->list || musb_ep->busy)
1196 musb_g_giveback(musb_ep, request, -ECONNRESET);
1198 /* ... else abort the dma transfer ... */
1199 else if (is_dma_capable() && musb_ep->dma) {
1200 struct dma_controller *c = musb->dma_controller;
1202 musb_ep_select(musb->mregs, musb_ep->current_epnum);
1203 if (c->channel_abort)
1204 status = c->channel_abort(musb_ep->dma);
1208 musb_g_giveback(musb_ep, request, -ECONNRESET);
1210 /* NOTE: by sticking to easily tested hardware/driver states,
1211 * we leave counting of in-flight packets imprecise.
1213 musb_g_giveback(musb_ep, request, -ECONNRESET);
1217 spin_unlock_irqrestore(&musb->lock, flags);
1222 * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any
1223 * data but will queue requests.
1225 * exported to ep0 code
1227 int musb_gadget_set_halt(struct usb_ep *ep, int value)
1229 struct musb_ep *musb_ep = to_musb_ep(ep);
1230 u8 epnum = musb_ep->current_epnum;
1231 struct musb *musb = musb_ep->musb;
1232 void __iomem *epio = musb->endpoints[epnum].regs;
1233 void __iomem *mbase;
1234 unsigned long flags;
1236 struct musb_request *request = NULL;
1241 mbase = musb->mregs;
1243 spin_lock_irqsave(&musb->lock, flags);
1245 if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) {
1250 musb_ep_select(mbase, epnum);
1252 /* cannot portably stall with non-empty FIFO */
1253 request = to_musb_request(next_request(musb_ep));
1254 if (value && musb_ep->is_in) {
1255 csr = musb_readw(epio, MUSB_TXCSR);
1256 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1257 DBG(3, "%s fifo busy, cannot halt\n", ep->name);
1258 spin_unlock_irqrestore(&musb->lock, flags);
1264 /* set/clear the stall and toggle bits */
1265 DBG(2, "%s: %s stall\n", ep->name, value ? "set" : "clear");
1266 if (musb_ep->is_in) {
1267 csr = musb_readw(epio, MUSB_TXCSR);
1268 if (csr & MUSB_TXCSR_FIFONOTEMPTY)
1269 csr |= MUSB_TXCSR_FLUSHFIFO;
1270 csr |= MUSB_TXCSR_P_WZC_BITS
1271 | MUSB_TXCSR_CLRDATATOG;
1273 csr |= MUSB_TXCSR_P_SENDSTALL;
1275 csr &= ~(MUSB_TXCSR_P_SENDSTALL
1276 | MUSB_TXCSR_P_SENTSTALL);
1277 csr &= ~MUSB_TXCSR_TXPKTRDY;
1278 musb_writew(epio, MUSB_TXCSR, csr);
1280 csr = musb_readw(epio, MUSB_RXCSR);
1281 csr |= MUSB_RXCSR_P_WZC_BITS
1282 | MUSB_RXCSR_FLUSHFIFO
1283 | MUSB_RXCSR_CLRDATATOG;
1285 csr |= MUSB_RXCSR_P_SENDSTALL;
1287 csr &= ~(MUSB_RXCSR_P_SENDSTALL
1288 | MUSB_RXCSR_P_SENTSTALL);
1289 musb_writew(epio, MUSB_RXCSR, csr);
1294 /* maybe start the first request in the queue */
1295 if (!musb_ep->busy && !value && request) {
1296 DBG(3, "restarting the request\n");
1297 musb_ep_restart(musb, request);
1300 spin_unlock_irqrestore(&musb->lock, flags);
1304 static int musb_gadget_fifo_status(struct usb_ep *ep)
1306 struct musb_ep *musb_ep = to_musb_ep(ep);
1307 void __iomem *epio = musb_ep->hw_ep->regs;
1308 int retval = -EINVAL;
1310 if (musb_ep->desc && !musb_ep->is_in) {
1311 struct musb *musb = musb_ep->musb;
1312 int epnum = musb_ep->current_epnum;
1313 void __iomem *mbase = musb->mregs;
1314 unsigned long flags;
1316 spin_lock_irqsave(&musb->lock, flags);
1318 musb_ep_select(mbase, epnum);
1319 /* FIXME return zero unless RXPKTRDY is set */
1320 retval = musb_readw(epio, MUSB_RXCOUNT);
1322 spin_unlock_irqrestore(&musb->lock, flags);
1327 static void musb_gadget_fifo_flush(struct usb_ep *ep)
1329 struct musb_ep *musb_ep = to_musb_ep(ep);
1330 struct musb *musb = musb_ep->musb;
1331 u8 epnum = musb_ep->current_epnum;
1332 void __iomem *epio = musb->endpoints[epnum].regs;
1333 void __iomem *mbase;
1334 unsigned long flags;
1337 mbase = musb->mregs;
1339 spin_lock_irqsave(&musb->lock, flags);
1340 musb_ep_select(mbase, (u8) epnum);
1342 /* disable interrupts */
1343 int_txe = musb_readw(mbase, MUSB_INTRTXE);
1344 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
1346 if (musb_ep->is_in) {
1347 csr = musb_readw(epio, MUSB_TXCSR);
1348 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1349 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS;
1350 musb_writew(epio, MUSB_TXCSR, csr);
1351 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1352 musb_writew(epio, MUSB_TXCSR, csr);
1355 csr = musb_readw(epio, MUSB_RXCSR);
1356 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS;
1357 musb_writew(epio, MUSB_RXCSR, csr);
1358 musb_writew(epio, MUSB_RXCSR, csr);
1361 /* re-enable interrupt */
1362 musb_writew(mbase, MUSB_INTRTXE, int_txe);
1363 spin_unlock_irqrestore(&musb->lock, flags);
1366 static const struct usb_ep_ops musb_ep_ops = {
1367 .enable = musb_gadget_enable,
1368 .disable = musb_gadget_disable,
1369 .alloc_request = musb_alloc_request,
1370 .free_request = musb_free_request,
1371 .queue = musb_gadget_queue,
1372 .dequeue = musb_gadget_dequeue,
1373 .set_halt = musb_gadget_set_halt,
1374 .fifo_status = musb_gadget_fifo_status,
1375 .fifo_flush = musb_gadget_fifo_flush
1378 /* ----------------------------------------------------------------------- */
1380 static int musb_gadget_get_frame(struct usb_gadget *gadget)
1382 struct musb *musb = gadget_to_musb(gadget);
1384 return (int)musb_readw(musb->mregs, MUSB_FRAME);
1387 static int musb_gadget_wakeup(struct usb_gadget *gadget)
1389 struct musb *musb = gadget_to_musb(gadget);
1390 void __iomem *mregs = musb->mregs;
1391 unsigned long flags;
1392 int status = -EINVAL;
1396 spin_lock_irqsave(&musb->lock, flags);
1398 switch (musb->xceiv.state) {
1399 case OTG_STATE_B_PERIPHERAL:
1400 /* NOTE: OTG state machine doesn't include B_SUSPENDED;
1401 * that's part of the standard usb 1.1 state machine, and
1402 * doesn't affect OTG transitions.
1404 if (musb->may_wakeup && musb->is_suspended)
1407 case OTG_STATE_B_IDLE:
1408 /* Start SRP ... OTG not required. */
1409 devctl = musb_readb(mregs, MUSB_DEVCTL);
1410 DBG(2, "Sending SRP: devctl: %02x\n", devctl);
1411 devctl |= MUSB_DEVCTL_SESSION;
1412 musb_writeb(mregs, MUSB_DEVCTL, devctl);
1413 devctl = musb_readb(mregs, MUSB_DEVCTL);
1415 while (!(devctl & MUSB_DEVCTL_SESSION)) {
1416 devctl = musb_readb(mregs, MUSB_DEVCTL);
1421 while (devctl & MUSB_DEVCTL_SESSION) {
1422 devctl = musb_readb(mregs, MUSB_DEVCTL);
1427 /* Block idling for at least 1s */
1428 musb_platform_try_idle(musb,
1429 jiffies + msecs_to_jiffies(1 * HZ));
1434 DBG(2, "Unhandled wake: %s\n", otg_state_string(musb));
1440 power = musb_readb(mregs, MUSB_POWER);
1441 power |= MUSB_POWER_RESUME;
1442 musb_writeb(mregs, MUSB_POWER, power);
1443 DBG(2, "issue wakeup\n");
1445 /* FIXME do this next chunk in a timer callback, no udelay */
1448 power = musb_readb(mregs, MUSB_POWER);
1449 power &= ~MUSB_POWER_RESUME;
1450 musb_writeb(mregs, MUSB_POWER, power);
1452 spin_unlock_irqrestore(&musb->lock, flags);
1457 musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered)
1459 struct musb *musb = gadget_to_musb(gadget);
1461 musb->is_self_powered = !!is_selfpowered;
1465 static void musb_pullup(struct musb *musb, int is_on)
1469 power = musb_readb(musb->mregs, MUSB_POWER);
1471 power |= MUSB_POWER_SOFTCONN;
1473 power &= ~MUSB_POWER_SOFTCONN;
1475 /* FIXME if on, HdrcStart; if off, HdrcStop */
1477 DBG(3, "gadget %s D+ pullup %s\n",
1478 musb->gadget_driver->function, is_on ? "on" : "off");
1479 musb_writeb(musb->mregs, MUSB_POWER, power);
1483 static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active)
1485 DBG(2, "<= %s =>\n", __FUNCTION__);
1488 * FIXME iff driver's softconnect flag is set (as it is during probe,
1489 * though that can clear it), just musb_pullup().
1496 static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1498 struct musb *musb = gadget_to_musb(gadget);
1500 if (!musb->xceiv.set_power)
1502 return otg_set_power(&musb->xceiv, mA);
1505 static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on)
1507 struct musb *musb = gadget_to_musb(gadget);
1508 unsigned long flags;
1512 /* NOTE: this assumes we are sensing vbus; we'd rather
1513 * not pullup unless the B-session is active.
1515 spin_lock_irqsave(&musb->lock, flags);
1516 if (is_on != musb->softconnect) {
1517 musb->softconnect = is_on;
1518 musb_pullup(musb, is_on);
1520 spin_unlock_irqrestore(&musb->lock, flags);
1524 static const struct usb_gadget_ops musb_gadget_operations = {
1525 .get_frame = musb_gadget_get_frame,
1526 .wakeup = musb_gadget_wakeup,
1527 .set_selfpowered = musb_gadget_set_self_powered,
1528 /* .vbus_session = musb_gadget_vbus_session, */
1529 .vbus_draw = musb_gadget_vbus_draw,
1530 .pullup = musb_gadget_pullup,
1533 /* ----------------------------------------------------------------------- */
1537 /* Only this registration code "knows" the rule (from USB standards)
1538 * about there being only one external upstream port. It assumes
1539 * all peripheral ports are external...
1541 static struct musb *the_gadget;
1543 static void musb_gadget_release(struct device *dev)
1545 /* kref_put(WHAT) */
1546 dev_dbg(dev, "%s\n", __FUNCTION__);
1551 init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in)
1553 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1555 memset(ep, 0, sizeof *ep);
1557 ep->current_epnum = epnum;
1562 INIT_LIST_HEAD(&ep->req_list);
1564 sprintf(ep->name, "ep%d%s", epnum,
1565 (!epnum || hw_ep->is_shared_fifo) ? "" : (
1566 is_in ? "in" : "out"));
1567 ep->end_point.name = ep->name;
1568 INIT_LIST_HEAD(&ep->end_point.ep_list);
1570 ep->end_point.maxpacket = 64;
1571 ep->end_point.ops = &musb_g_ep0_ops;
1572 musb->g.ep0 = &ep->end_point;
1575 ep->end_point.maxpacket = hw_ep->max_packet_sz_tx;
1577 ep->end_point.maxpacket = hw_ep->max_packet_sz_rx;
1578 ep->end_point.ops = &musb_ep_ops;
1579 list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list);
1584 * Initialize the endpoints exposed to peripheral drivers, with backlinks
1585 * to the rest of the driver state.
1587 static inline void __init musb_g_init_endpoints(struct musb *musb)
1590 struct musb_hw_ep *hw_ep;
1593 /* intialize endpoint list just once */
1594 INIT_LIST_HEAD(&(musb->g.ep_list));
1596 for (epnum = 0, hw_ep = musb->endpoints;
1597 epnum < musb->nr_endpoints;
1599 if (hw_ep->is_shared_fifo /* || !epnum */) {
1600 init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0);
1603 if (hw_ep->max_packet_sz_tx) {
1604 init_peripheral_ep(musb, &hw_ep->ep_in,
1608 if (hw_ep->max_packet_sz_rx) {
1609 init_peripheral_ep(musb, &hw_ep->ep_out,
1617 /* called once during driver setup to initialize and link into
1618 * the driver model; memory is zeroed.
1620 int __init musb_gadget_setup(struct musb *musb)
1624 /* REVISIT minor race: if (erroneously) setting up two
1625 * musb peripherals at the same time, only the bus lock
1632 musb->g.ops = &musb_gadget_operations;
1633 musb->g.is_dualspeed = 1;
1634 musb->g.speed = USB_SPEED_UNKNOWN;
1636 /* this "gadget" abstracts/virtualizes the controller */
1637 strcpy(musb->g.dev.bus_id, "gadget");
1638 musb->g.dev.parent = musb->controller;
1639 musb->g.dev.dma_mask = musb->controller->dma_mask;
1640 musb->g.dev.release = musb_gadget_release;
1641 musb->g.name = musb_driver_name;
1643 if (is_otg_enabled(musb))
1646 musb_g_init_endpoints(musb);
1648 musb->is_active = 0;
1649 musb_platform_try_idle(musb, 0);
1651 status = device_register(&musb->g.dev);
1657 void musb_gadget_cleanup(struct musb *musb)
1659 if (musb != the_gadget)
1662 device_unregister(&musb->g.dev);
1667 * Register the gadget driver. Used by gadget drivers when
1668 * registering themselves with the controller.
1670 * -EINVAL something went wrong (not driver)
1671 * -EBUSY another gadget is already using the controller
1672 * -ENOMEM no memeory to perform the operation
1674 * @param driver the gadget driver
1675 * @return <0 if error, 0 if everything is fine
1677 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1680 unsigned long flags;
1681 struct musb *musb = the_gadget;
1684 || driver->speed != USB_SPEED_HIGH
1689 /* driver must be initialized to support peripheral mode */
1690 if (!musb || !(musb->board_mode == MUSB_OTG
1691 || musb->board_mode != MUSB_OTG)) {
1692 DBG(1,"%s, no dev??\n", __FUNCTION__);
1696 DBG(3, "registering driver %s\n", driver->function);
1697 spin_lock_irqsave(&musb->lock, flags);
1699 if (musb->gadget_driver) {
1700 DBG(1, "%s is already bound to %s\n",
1702 musb->gadget_driver->driver.name);
1705 musb->gadget_driver = driver;
1706 musb->g.dev.driver = &driver->driver;
1707 driver->driver.bus = NULL;
1708 musb->softconnect = 1;
1712 spin_unlock_irqrestore(&musb->lock, flags);
1715 retval = driver->bind(&musb->g);
1717 DBG(3, "bind to driver %s failed --> %d\n",
1718 driver->driver.name, retval);
1719 musb->gadget_driver = NULL;
1720 musb->g.dev.driver = NULL;
1723 /* start peripheral and/or OTG engines */
1725 spin_lock_irqsave(&musb->lock, flags);
1727 /* REVISIT always use otg_set_peripheral(), handling
1728 * issues including the root hub one below ...
1730 musb->xceiv.gadget = &musb->g;
1731 musb->xceiv.state = OTG_STATE_B_IDLE;
1732 musb->is_active = 1;
1734 /* FIXME this ignores the softconnect flag. Drivers are
1735 * allowed hold the peripheral inactive until for example
1736 * userspace hooks up printer hardware or DSP codecs, so
1737 * hosts only see fully functional devices.
1740 if (!is_otg_enabled(musb))
1743 spin_unlock_irqrestore(&musb->lock, flags);
1745 if (is_otg_enabled(musb)) {
1746 DBG(3, "OTG startup...\n");
1748 /* REVISIT: funcall to other code, which also
1749 * handles power budgeting ... this way also
1750 * ensures HdrcStart is indirectly called.
1752 retval = usb_add_hcd(musb_to_hcd(musb), -1, 0);
1754 DBG(1, "add_hcd failed, %d\n", retval);
1755 spin_lock_irqsave(&musb->lock, flags);
1756 musb->xceiv.gadget = NULL;
1757 musb->xceiv.state = OTG_STATE_UNDEFINED;
1758 musb->gadget_driver = NULL;
1759 musb->g.dev.driver = NULL;
1760 spin_unlock_irqrestore(&musb->lock, flags);
1767 EXPORT_SYMBOL(usb_gadget_register_driver);
1769 static void stop_activity(struct musb *musb, struct usb_gadget_driver *driver)
1772 struct musb_hw_ep *hw_ep;
1774 /* don't disconnect if it's not connected */
1775 if (musb->g.speed == USB_SPEED_UNKNOWN)
1778 musb->g.speed = USB_SPEED_UNKNOWN;
1780 /* deactivate the hardware */
1781 if (musb->softconnect) {
1782 musb->softconnect = 0;
1783 musb_pullup(musb, 0);
1787 /* killing any outstanding requests will quiesce the driver;
1788 * then report disconnect
1791 for (i = 0, hw_ep = musb->endpoints;
1792 i < musb->nr_endpoints;
1794 musb_ep_select(musb->mregs, i);
1795 if (hw_ep->is_shared_fifo /* || !epnum */) {
1796 nuke(&hw_ep->ep_in, -ESHUTDOWN);
1798 if (hw_ep->max_packet_sz_tx)
1799 nuke(&hw_ep->ep_in, -ESHUTDOWN);
1800 if (hw_ep->max_packet_sz_rx)
1801 nuke(&hw_ep->ep_out, -ESHUTDOWN);
1805 spin_unlock(&musb->lock);
1806 driver->disconnect (&musb->g);
1807 spin_lock(&musb->lock);
1812 * Unregister the gadget driver. Used by gadget drivers when
1813 * unregistering themselves from the controller.
1815 * @param driver the gadget driver to unregister
1817 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1819 unsigned long flags;
1821 struct musb *musb = the_gadget;
1823 if (!driver || !driver->unbind || !musb)
1826 /* REVISIT always use otg_set_peripheral() here too;
1827 * this needs to shut down the OTG engine.
1830 spin_lock_irqsave(&musb->lock, flags);
1832 #ifdef CONFIG_USB_MUSB_OTG
1833 musb_hnp_stop(musb);
1836 if (musb->gadget_driver == driver) {
1838 (void) musb_gadget_vbus_draw(&musb->g, 0);
1840 musb->xceiv.state = OTG_STATE_UNDEFINED;
1841 stop_activity(musb, driver);
1843 DBG(3, "unregistering driver %s\n", driver->function);
1844 spin_unlock_irqrestore(&musb->lock, flags);
1845 driver->unbind(&musb->g);
1846 spin_lock_irqsave(&musb->lock, flags);
1848 musb->gadget_driver = NULL;
1849 musb->g.dev.driver = NULL;
1851 musb->is_active = 0;
1852 musb_platform_try_idle(musb, 0);
1855 spin_unlock_irqrestore(&musb->lock, flags);
1857 if (is_otg_enabled(musb) && retval == 0) {
1858 usb_remove_hcd(musb_to_hcd(musb));
1859 /* FIXME we need to be able to register another
1860 * gadget driver here and have everything work;
1861 * that currently misbehaves.
1867 EXPORT_SYMBOL(usb_gadget_unregister_driver);
1870 /* ----------------------------------------------------------------------- */
1872 /* lifecycle operations called through plat_uds.c */
1874 void musb_g_resume(struct musb *musb)
1876 musb->is_suspended = 0;
1877 switch (musb->xceiv.state) {
1878 case OTG_STATE_B_IDLE:
1880 case OTG_STATE_B_WAIT_ACON:
1881 case OTG_STATE_B_PERIPHERAL:
1882 musb->is_active = 1;
1883 if (musb->gadget_driver && musb->gadget_driver->resume) {
1884 spin_unlock(&musb->lock);
1885 musb->gadget_driver->resume(&musb->g);
1886 spin_lock(&musb->lock);
1890 WARN("unhandled RESUME transition (%s)\n",
1891 otg_state_string(musb));
1895 /* called when SOF packets stop for 3+ msec */
1896 void musb_g_suspend(struct musb *musb)
1900 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1901 DBG(3, "devctl %02x\n", devctl);
1903 switch (musb->xceiv.state) {
1904 case OTG_STATE_B_IDLE:
1905 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
1906 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
1908 case OTG_STATE_B_PERIPHERAL:
1909 musb->is_suspended = 1;
1910 if (musb->gadget_driver && musb->gadget_driver->suspend) {
1911 spin_unlock(&musb->lock);
1912 musb->gadget_driver->suspend(&musb->g);
1913 spin_lock(&musb->lock);
1917 /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ;
1918 * A_PERIPHERAL may need care too
1920 WARN("unhandled SUSPEND transition (%s)\n",
1921 otg_state_string(musb));
1925 /* Called during SRP */
1926 void musb_g_wakeup(struct musb *musb)
1928 musb_gadget_wakeup(&musb->g);
1931 /* called when VBUS drops below session threshold, and in other cases */
1932 void musb_g_disconnect(struct musb *musb)
1934 void __iomem *mregs = musb->mregs;
1935 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
1937 DBG(3, "devctl %02x\n", devctl);
1940 musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION);
1942 /* don't draw vbus until new b-default session */
1943 (void) musb_gadget_vbus_draw(&musb->g, 0);
1945 musb->g.speed = USB_SPEED_UNKNOWN;
1946 if (musb->gadget_driver && musb->gadget_driver->disconnect) {
1947 spin_unlock(&musb->lock);
1948 musb->gadget_driver->disconnect(&musb->g);
1949 spin_lock(&musb->lock);
1952 switch (musb->xceiv.state) {
1954 #ifdef CONFIG_USB_MUSB_OTG
1955 DBG(2, "Unhandled disconnect %s, setting a_idle\n",
1956 otg_state_string(musb));
1957 musb->xceiv.state = OTG_STATE_A_IDLE;
1959 case OTG_STATE_A_PERIPHERAL:
1960 musb->xceiv.state = OTG_STATE_A_WAIT_VFALL;
1962 case OTG_STATE_B_WAIT_ACON:
1963 case OTG_STATE_B_HOST:
1965 case OTG_STATE_B_PERIPHERAL:
1966 case OTG_STATE_B_IDLE:
1967 musb->xceiv.state = OTG_STATE_B_IDLE;
1969 case OTG_STATE_B_SRP_INIT:
1973 musb->is_active = 0;
1976 void musb_g_reset(struct musb *musb)
1977 __releases(musb->lock)
1978 __acquires(musb->lock)
1980 void __iomem *mbase = musb->mregs;
1981 u8 devctl = musb_readb(mbase, MUSB_DEVCTL);
1984 DBG(3, "<== %s addr=%x driver '%s'\n",
1985 (devctl & MUSB_DEVCTL_BDEVICE)
1986 ? "B-Device" : "A-Device",
1987 musb_readb(mbase, MUSB_FADDR),
1989 ? musb->gadget_driver->driver.name
1993 /* report disconnect, if we didn't already (flushing EP state) */
1994 if (musb->g.speed != USB_SPEED_UNKNOWN)
1995 musb_g_disconnect(musb);
1998 else if (devctl & MUSB_DEVCTL_HR)
1999 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
2002 /* what speed did we negotiate? */
2003 power = musb_readb(mbase, MUSB_POWER);
2004 musb->g.speed = (power & MUSB_POWER_HSMODE)
2005 ? USB_SPEED_HIGH : USB_SPEED_FULL;
2007 /* start in USB_STATE_DEFAULT */
2008 musb->is_active = 1;
2009 musb->is_suspended = 0;
2010 MUSB_DEV_MODE(musb);
2012 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
2014 musb->may_wakeup = 0;
2015 musb->g.b_hnp_enable = 0;
2016 musb->g.a_alt_hnp_support = 0;
2017 musb->g.a_hnp_support = 0;
2019 /* Normal reset, as B-Device;
2020 * or else after HNP, as A-Device
2022 if (devctl & MUSB_DEVCTL_BDEVICE) {
2023 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
2024 musb->g.is_a_peripheral = 0;
2025 } else if (is_otg_enabled(musb)) {
2026 musb->xceiv.state = OTG_STATE_A_PERIPHERAL;
2027 musb->g.is_a_peripheral = 1;
2031 /* start with default limits on VBUS power draw */
2032 (void) musb_gadget_vbus_draw(&musb->g,
2033 is_otg_enabled(musb) ? 8 : 100);