2 * MUSB OTG driver core code
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - <asm/arch/hdrc_cnf.h> for SOC or family details
86 * - platform_device for addressing, irq, and platform_data
87 * - platform_data is mostly for board-specific informarion
89 * Most of the conditional compilation will (someday) vanish.
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/platform_device.h>
104 #include <asm/arch/hardware.h>
105 #include <asm/arch/memory.h>
106 #include <asm/mach-types.h>
109 #include "musbdefs.h"
112 #ifdef CONFIG_ARCH_DAVINCI
119 unsigned debug = MUSB_DEBUG;
120 module_param(debug, uint, 0);
121 MODULE_PARM_DESC(debug, "initial debug message level");
123 #define MUSB_VERSION_SUFFIX "/dbg"
126 const char *otg_state_string(struct musb *musb)
130 snprintf(buf, sizeof buf, "otg-%d", musb->xceiv.state);
135 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
136 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
138 #define MUSB_VERSION_BASE "2.2a/db-0.5.2"
140 #ifndef MUSB_VERSION_SUFFIX
141 #define MUSB_VERSION_SUFFIX ""
143 #define MUSB_VERSION MUSB_VERSION_BASE MUSB_VERSION_SUFFIX
145 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
147 const char musb_driver_name[] = "musb_hdrc";
149 MODULE_DESCRIPTION(DRIVER_INFO);
150 MODULE_AUTHOR(DRIVER_AUTHOR);
151 MODULE_LICENSE("GPL");
154 /*-------------------------------------------------------------------------*/
156 static inline struct musb *dev_to_musb(struct device *dev)
158 #ifdef CONFIG_USB_MUSB_HDRC_HCD
159 /* usbcore insists dev->driver_data is a "struct hcd *" */
160 return hcd_to_musb(dev_get_drvdata(dev));
162 return dev_get_drvdata(dev);
166 /*-------------------------------------------------------------------------*/
168 #ifndef CONFIG_USB_TUSB6010
170 * Load an endpoint's FIFO
172 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
174 void __iomem *fifo = hw_ep->fifo;
178 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
179 'T', hw_ep->epnum, fifo, len, src);
181 /* we can't assume unaligned reads work */
182 if (likely((0x01 & (unsigned long) src) == 0)) {
185 /* best case is 32bit-aligned source address */
186 if ((0x02 & (unsigned long) src) == 0) {
188 writesl(fifo, src + index, len >> 2);
189 index += len & ~0x03;
192 musb_writew(fifo, 0, *(u16*)&src[index]);
197 writesw(fifo, src + index, len >> 1);
198 index += len & ~0x01;
202 musb_writeb(fifo, 0, src[index]);
205 writesb(fifo, src, len);
210 * Unload an endpoint's FIFO
212 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
214 void __iomem *fifo = hw_ep->fifo;
216 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
217 'R', hw_ep->epnum, fifo, len, dst);
219 /* we can't assume unaligned writes work */
220 if (likely((0x01 & (unsigned long) dst) == 0)) {
223 /* best case is 32bit-aligned destination address */
224 if ((0x02 & (unsigned long) dst) == 0) {
226 readsl(fifo, dst, len >> 2);
230 *(u16*)&dst[index] = musb_readw(fifo, 0);
235 readsw(fifo, dst, len >> 1);
240 dst[index] = musb_readb(fifo, 0);
243 readsb(fifo, dst, len);
247 #endif /* normal PIO */
250 /*-------------------------------------------------------------------------*/
252 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
253 static const u8 musb_test_packet[53] = {
254 /* implicit SYNC then DATA0 to start */
257 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
259 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
261 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
262 /* JJJJJJJKKKKKKK x8 */
263 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
265 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
266 /* JKKKKKKK x10, JK */
267 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
269 /* implicit CRC16 then EOP to end */
272 void musb_load_testpacket(struct musb *musb)
274 void __iomem *regs = musb->endpoints[0].regs;
276 musb_ep_select(musb->mregs, 0);
277 musb_write_fifo(musb->control_ep,
278 sizeof(musb_test_packet), musb_test_packet);
279 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
282 /*-------------------------------------------------------------------------*/
284 #ifdef CONFIG_USB_MUSB_OTG
287 * See also USB_OTG_1-3.pdf 6.6.5 Timers
288 * REVISIT: Are the other timers done in the hardware?
290 #define TB_ASE0_BRST 100 /* Min 3.125 ms */
293 * Handles OTG hnp timeouts, such as b_ase0_brst
295 void musb_otg_timer_func(unsigned long data)
297 struct musb *musb = (struct musb *)data;
300 spin_lock_irqsave(&musb->lock, flags);
301 if (musb->xceiv.state == OTG_STATE_B_WAIT_ACON) {
302 DBG(1, "HNP: B_WAIT_ACON timeout, going back to B_PERIPHERAL\n");
303 musb_g_disconnect(musb);
304 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
307 spin_unlock_irqrestore(&musb->lock, flags);
310 static DEFINE_TIMER(musb_otg_timer, musb_otg_timer_func, 0, 0);
313 * Stops the B-device HNP state. Caller must take care of locking.
315 void musb_hnp_stop(struct musb *musb)
317 struct usb_hcd *hcd = musb_to_hcd(musb);
318 void __iomem *mbase = musb->mregs;
321 switch (musb->xceiv.state) {
322 case OTG_STATE_A_PERIPHERAL:
323 case OTG_STATE_A_WAIT_VFALL:
324 DBG(1, "HNP: Switching back to A-host\n");
325 musb_g_disconnect(musb);
326 musb_root_disconnect(musb);
327 musb->xceiv.state = OTG_STATE_A_IDLE;
330 case OTG_STATE_B_HOST:
331 DBG(1, "HNP: Disabling HR\n");
332 hcd->self.is_b_host = 0;
333 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
334 reg = musb_readb(mbase, MUSB_POWER);
335 reg |= MUSB_POWER_SUSPENDM;
336 musb_writeb(mbase, MUSB_POWER, reg);
337 /* REVISIT: Start SESSION_REQUEST here? */
340 DBG(1, "HNP: Stopping in unknown state %s\n",
341 otg_state_string(musb));
348 * Interrupt Service Routine to record USB "global" interrupts.
349 * Since these do not happen often and signify things of
350 * paramount importance, it seems OK to check them individually;
351 * the order of the tests is specified in the manual
353 * @param musb instance pointer
354 * @param int_usb register contents
359 #define STAGE0_MASK (MUSB_INTR_RESUME | MUSB_INTR_SESSREQ \
360 | MUSB_INTR_VBUSERROR | MUSB_INTR_CONNECT \
363 static irqreturn_t musb_stage0_irq(struct musb * musb, u8 int_usb,
366 irqreturn_t handled = IRQ_NONE;
367 void __iomem *mbase = musb->mregs;
369 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
372 /* in host mode, the peripheral may issue remote wakeup.
373 * in peripheral mode, the host may resume the link.
374 * spurious RESUME irqs happen too, paired with SUSPEND.
376 if (int_usb & MUSB_INTR_RESUME) {
377 handled = IRQ_HANDLED;
378 DBG(3, "RESUME (%s)\n", otg_state_string(musb));
380 if (devctl & MUSB_DEVCTL_HM) {
381 #ifdef CONFIG_USB_MUSB_HDRC_HCD
382 switch (musb->xceiv.state) {
383 case OTG_STATE_A_SUSPEND:
384 /* remote wakeup? later, GetPortStatus
385 * will stop RESUME signaling
388 if (power & MUSB_POWER_SUSPENDM) {
390 musb->int_usb &= ~MUSB_INTR_SUSPEND;
391 DBG(2, "Spurious SUSPENDM\n");
395 power &= ~MUSB_POWER_SUSPENDM;
396 musb_writeb(mbase, MUSB_POWER,
397 power | MUSB_POWER_RESUME);
399 musb->port1_status |=
400 (USB_PORT_STAT_C_SUSPEND << 16)
401 | MUSB_PORT_STAT_RESUME;
402 musb->rh_timer = jiffies
403 + msecs_to_jiffies(20);
405 musb->xceiv.state = OTG_STATE_A_HOST;
407 usb_hcd_resume_root_hub(musb_to_hcd(musb));
409 case OTG_STATE_B_WAIT_ACON:
410 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
415 WARN("bogus %s RESUME (%s)\n",
417 otg_state_string(musb));
421 switch (musb->xceiv.state) {
422 #ifdef CONFIG_USB_MUSB_HDRC_HCD
423 case OTG_STATE_A_SUSPEND:
424 /* possibly DISCONNECT is upcoming */
425 musb->xceiv.state = OTG_STATE_A_HOST;
426 usb_hcd_resume_root_hub(musb_to_hcd(musb));
429 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
430 case OTG_STATE_B_WAIT_ACON:
431 case OTG_STATE_B_PERIPHERAL:
432 /* disconnect while suspended? we may
433 * not get a disconnect irq...
435 if ((devctl & MUSB_DEVCTL_VBUS)
436 != (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
437 musb->int_usb |= MUSB_INTR_DISCONNECT;
438 musb->int_usb &= ~MUSB_INTR_SUSPEND;
443 case OTG_STATE_B_IDLE:
444 musb->int_usb &= ~MUSB_INTR_SUSPEND;
448 WARN("bogus %s RESUME (%s)\n",
450 otg_state_string(musb));
455 #ifdef CONFIG_USB_MUSB_HDRC_HCD
456 /* see manual for the order of the tests */
457 if (int_usb & MUSB_INTR_SESSREQ) {
458 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb));
460 /* IRQ arrives from ID pin sense or (later, if VBUS power
461 * is removed) SRP. responses are time critical:
462 * - turn on VBUS (with silicon-specific mechanism)
463 * - go through A_WAIT_VRISE
464 * - ... to A_WAIT_BCON.
465 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
467 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
468 musb->ep0_stage = MUSB_EP0_START;
469 musb->xceiv.state = OTG_STATE_A_IDLE;
471 musb_set_vbus(musb, 1);
473 handled = IRQ_HANDLED;
476 if (int_usb & MUSB_INTR_VBUSERROR) {
479 /* During connection as an A-Device, we may see a short
480 * current spikes causing voltage drop, because of cable
481 * and peripheral capacitance combined with vbus draw.
482 * (So: less common with truly self-powered devices, where
483 * vbus doesn't act like a power supply.)
485 * Such spikes are short; usually less than ~500 usec, max
486 * of ~2 msec. That is, they're not sustained overcurrent
487 * errors, though they're reported using VBUSERROR irqs.
489 * Workarounds: (a) hardware: use self powered devices.
490 * (b) software: ignore non-repeated VBUS errors.
492 * REVISIT: do delays from lots of DEBUG_KERNEL checks
493 * make trouble here, keeping VBUS < 4.4V ?
495 switch (musb->xceiv.state) {
496 case OTG_STATE_A_HOST:
497 /* recovery is dicey once we've gotten past the
498 * initial stages of enumeration, but if VBUS
499 * stayed ok at the other end of the link, and
500 * another reset is due (at least for high speed,
501 * to redo the chirp etc), it might work OK...
503 case OTG_STATE_A_WAIT_BCON:
504 case OTG_STATE_A_WAIT_VRISE:
505 if (musb->vbuserr_retry) {
506 musb->vbuserr_retry--;
508 devctl |= MUSB_DEVCTL_SESSION;
509 musb_writeb(mbase, MUSB_DEVCTL, devctl);
511 musb->port1_status |=
512 (1 << USB_PORT_FEAT_OVER_CURRENT)
513 | (1 << USB_PORT_FEAT_C_OVER_CURRENT);
520 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
521 otg_state_string(musb),
524 switch (devctl & MUSB_DEVCTL_VBUS) {
525 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
526 s = "<SessEnd"; break;
527 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
528 s = "<AValid"; break;
529 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
530 s = "<VBusValid"; break;
531 //case 3 << MUSB_DEVCTL_VBUS_SHIFT:
535 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
538 /* go through A_WAIT_VFALL then start a new session */
540 musb_set_vbus(musb, 0);
541 handled = IRQ_HANDLED;
544 if (int_usb & MUSB_INTR_CONNECT) {
545 struct usb_hcd *hcd = musb_to_hcd(musb);
547 handled = IRQ_HANDLED;
549 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
551 musb->ep0_stage = MUSB_EP0_START;
553 #ifdef CONFIG_USB_MUSB_OTG
554 /* flush endpoints when transitioning from Device Mode */
555 if (is_peripheral_active(musb)) {
556 // REVISIT HNP; just force disconnect
558 musb_writew(mbase, MUSB_INTRTXE, musb->epmask);
559 musb_writew(mbase, MUSB_INTRRXE, musb->epmask & 0xfffe);
560 musb_writeb(mbase, MUSB_INTRUSBE, 0xf7);
562 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
563 |USB_PORT_STAT_HIGH_SPEED
564 |USB_PORT_STAT_ENABLE
566 musb->port1_status |= USB_PORT_STAT_CONNECTION
567 |(USB_PORT_STAT_C_CONNECTION << 16);
569 /* high vs full speed is just a guess until after reset */
570 if (devctl & MUSB_DEVCTL_LSDEV)
571 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
574 usb_hcd_poll_rh_status(hcd);
576 usb_hcd_resume_root_hub(hcd);
580 /* indicate new connection to OTG machine */
581 switch (musb->xceiv.state) {
582 case OTG_STATE_B_WAIT_ACON:
583 DBG(1, "HNP: Waiting to switch to b_host state\n");
584 musb->xceiv.state = OTG_STATE_B_HOST;
585 hcd->self.is_b_host = 1;
588 if ((devctl & MUSB_DEVCTL_VBUS)
589 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
590 musb->xceiv.state = OTG_STATE_A_HOST;
591 hcd->self.is_b_host = 0;
595 DBG(1, "CONNECT (%s) devctl %02x\n",
596 otg_state_string(musb), devctl);
598 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
600 /* mentor saves a bit: bus reset and babble share the same irq.
601 * only host sees babble; only peripheral sees bus reset.
603 if (int_usb & MUSB_INTR_RESET) {
604 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
606 * Looks like non-HS BABBLE can be ignored, but
607 * HS BABBLE is an error condition. For HS the solution
608 * is to avoid babble in the first place and fix whatever
609 * causes BABBLE. When HS BABBLE happens we can only stop
612 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
613 DBG(1, "BABBLE devctl: %02x\n", devctl);
615 ERR("Stopping host session because of babble\n");
616 musb_writeb(mbase, MUSB_DEVCTL, 0);
618 } else if (is_peripheral_capable()) {
619 DBG(1, "BUS RESET\n");
622 schedule_work(&musb->irq_work);
625 handled = IRQ_HANDLED;
632 * Interrupt Service Routine to record USB "global" interrupts.
633 * Since these do not happen often and signify things of
634 * paramount importance, it seems OK to check them individually;
635 * the order of the tests is specified in the manual
637 * @param musb instance pointer
638 * @param int_usb register contents
642 static irqreturn_t musb_stage2_irq(struct musb * musb, u8 int_usb,
645 irqreturn_t handled = IRQ_NONE;
648 /* REVISIT ... this would be for multiplexing periodic endpoints, or
649 * supporting transfer phasing to prevent exceeding ISO bandwidth
650 * limits of a given frame or microframe.
652 * It's not needed for peripheral side, which dedicates endpoints;
653 * though it _might_ use SOF irqs for other purposes.
655 * And it's not currently needed for host side, which also dedicates
656 * endpoints, relies on TX/RX interval registers, and isn't claimed
657 * to support ISO transfers yet.
659 if (int_usb & MUSB_INTR_SOF) {
660 void __iomem *mbase = musb->mregs;
661 struct musb_hw_ep *ep;
665 DBG(6, "START_OF_FRAME\n");
666 handled = IRQ_HANDLED;
668 /* start any periodic Tx transfers waiting for current frame */
669 frame = musb_readw(mbase, MUSB_FRAME);
670 ep = musb->endpoints;
671 for (epnum = 1; (epnum < musb->nr_endpoints)
672 && (musb->epmask >= (1 << epnum));
674 // FIXME handle framecounter wraps (12 bits)
675 // eliminate duplicated StartUrb logic
676 if (ep->dwWaitFrame >= frame) {
678 printk("SOF --> periodic TX%s on %d\n",
679 ep->tx_channel ? " DMA" : "",
682 musb_h_tx_start(musb, epnum);
684 cppi_hostdma_start(musb, epnum);
686 } /* end of for loop */
690 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
691 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
692 otg_state_string(musb),
693 MUSB_MODE(musb), devctl);
694 handled = IRQ_HANDLED;
696 switch (musb->xceiv.state) {
697 #ifdef CONFIG_USB_MUSB_HDRC_HCD
698 case OTG_STATE_A_HOST:
699 case OTG_STATE_A_SUSPEND:
700 musb_root_disconnect(musb);
701 if (musb->a_wait_bcon != 0)
702 musb_platform_try_idle(musb, jiffies
703 + msecs_to_jiffies(musb->a_wait_bcon));
706 #ifdef CONFIG_USB_MUSB_OTG
707 case OTG_STATE_B_HOST:
711 case OTG_STATE_A_PERIPHERAL:
712 musb_root_disconnect(musb);
714 case OTG_STATE_B_WAIT_ACON:
716 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
717 case OTG_STATE_B_PERIPHERAL:
718 case OTG_STATE_B_IDLE:
719 musb_g_disconnect(musb);
723 WARN("unhandled DISCONNECT transition (%s)\n",
724 otg_state_string(musb));
728 schedule_work(&musb->irq_work);
731 if (int_usb & MUSB_INTR_SUSPEND) {
732 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
733 otg_state_string(musb), devctl, power);
734 handled = IRQ_HANDLED;
736 switch (musb->xceiv.state) {
737 #ifdef CONFIG_USB_MUSB_OTG
738 case OTG_STATE_A_PERIPHERAL:
742 case OTG_STATE_B_PERIPHERAL:
743 musb_g_suspend(musb);
744 musb->is_active = is_otg_enabled(musb)
745 && musb->xceiv.gadget->b_hnp_enable;
746 if (musb->is_active) {
747 musb->xceiv.state = OTG_STATE_B_WAIT_ACON;
748 #ifdef CONFIG_USB_MUSB_OTG
749 DBG(1, "HNP: Setting timer for b_ase0_brst\n");
750 musb_otg_timer.data = (unsigned long)musb;
751 mod_timer(&musb_otg_timer, jiffies
752 + msecs_to_jiffies(TB_ASE0_BRST));
756 case OTG_STATE_A_WAIT_BCON:
757 if (musb->a_wait_bcon != 0)
758 musb_platform_try_idle(musb, jiffies
759 + msecs_to_jiffies(musb->a_wait_bcon));
761 case OTG_STATE_A_HOST:
762 musb->xceiv.state = OTG_STATE_A_SUSPEND;
763 musb->is_active = is_otg_enabled(musb)
764 && musb->xceiv.host->b_hnp_enable;
766 case OTG_STATE_B_HOST:
767 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
768 DBG(1, "REVISIT: SUSPEND as B_HOST\n");
771 /* "should not happen" */
781 /*-------------------------------------------------------------------------*/
784 * Program the HDRC to start (enable interrupts, dma, etc.).
786 void musb_start(struct musb *musb)
788 void __iomem *regs = musb->mregs;
789 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
791 DBG(2, "<== devctl %02x\n", devctl);
793 /* Set INT enable registers, enable interrupts */
794 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
795 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
796 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
798 musb_writeb(regs, MUSB_TESTMODE, 0);
800 /* put into basic highspeed mode and start session */
801 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
802 | MUSB_POWER_SOFTCONN
804 /* ENSUSPEND wedges tusb */
805 // | MUSB_POWER_ENSUSPEND
809 devctl = musb_readb(regs, MUSB_DEVCTL);
810 devctl &= ~MUSB_DEVCTL_SESSION;
812 if (is_otg_enabled(musb)) {
813 /* session started after:
814 * (a) ID-grounded irq, host mode;
815 * (b) vbus present/connect IRQ, peripheral mode;
816 * (c) peripheral initiates, using SRP
818 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
821 devctl |= MUSB_DEVCTL_SESSION;
823 } else if (is_host_enabled(musb)) {
824 /* assume ID pin is hard-wired to ground */
825 devctl |= MUSB_DEVCTL_SESSION;
827 } else /* peripheral is enabled */ {
828 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
831 musb_platform_enable(musb);
832 musb_writeb(regs, MUSB_DEVCTL, devctl);
836 static void musb_generic_disable(struct musb *musb)
838 void __iomem *mbase = musb->mregs;
841 /* disable interrupts */
842 musb_writeb(mbase, MUSB_INTRUSBE, 0);
843 musb_writew(mbase, MUSB_INTRTXE, 0);
844 musb_writew(mbase, MUSB_INTRRXE, 0);
847 musb_writeb(mbase, MUSB_DEVCTL, 0);
849 /* flush pending interrupts */
850 temp = musb_readb(mbase, MUSB_INTRUSB);
851 temp = musb_readw(mbase, MUSB_INTRTX);
852 temp = musb_readw(mbase, MUSB_INTRRX);
857 * Make the HDRC stop (disable interrupts, etc.);
858 * reversible by musb_start
859 * called on gadget driver unregister
860 * with controller locked, irqs blocked
861 * acts as a NOP unless some role activated the hardware
863 void musb_stop(struct musb *musb)
865 /* stop IRQs, timers, ... */
866 musb_platform_disable(musb);
867 musb_generic_disable(musb);
868 DBG(3, "HDRC disabled\n");
871 * - mark host and/or peripheral drivers unusable/inactive
872 * - disable DMA (and enable it in HdrcStart)
873 * - make sure we can musb_start() after musb_stop(); with
874 * OTG mode, gadget driver module rmmod/modprobe cycles that
877 musb_platform_try_idle(musb, 0);
880 static void musb_shutdown(struct platform_device *pdev)
882 struct musb *musb = dev_to_musb(&pdev->dev);
885 spin_lock_irqsave(&musb->lock, flags);
886 musb_platform_disable(musb);
887 musb_generic_disable(musb);
889 clk_put(musb->clock);
892 spin_unlock_irqrestore(&musb->lock, flags);
894 /* FIXME power down */
898 /*-------------------------------------------------------------------------*/
901 * The silicon either has hard-wired endpoint configurations, or else
902 * "dynamic fifo" sizing. The driver has support for both, though at this
903 * writing only the dynamic sizing is very well tested. We use normal
904 * idioms to so both modes are compile-tested, but dead code elimination
905 * leaves only the relevant one in the object file.
907 * We don't currently use dynamic fifo setup capability to do anything
908 * more than selecting one of a bunch of predefined configurations.
910 #ifdef MUSB_C_DYNFIFO_DEF
911 #define can_dynfifo() 1
913 #define can_dynfifo() 0
916 #ifdef CONFIG_USB_TUSB6010
917 static ushort __initdata fifo_mode = 4;
919 static ushort __initdata fifo_mode = 2;
922 /* "modprobe ... fifo_mode=1" etc */
923 module_param(fifo_mode, ushort, 0);
924 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
927 #define DYN_FIFO_SIZE (1<<(MUSB_C_RAM_BITS+2))
929 enum fifo_style { FIFO_RXTX, FIFO_TX, FIFO_RX } __attribute__ ((packed));
930 enum buf_mode { BUF_SINGLE, BUF_DOUBLE } __attribute__ ((packed));
934 enum fifo_style style;
940 * tables defining fifo_mode values. define more if you like.
941 * for host side, make sure both halves of ep1 are set up.
944 /* mode 0 - fits in 2KB */
945 static struct fifo_cfg __initdata mode_0_cfg[] = {
946 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
947 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
948 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
949 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
950 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
953 /* mode 1 - fits in 4KB */
954 static struct fifo_cfg __initdata mode_1_cfg[] = {
955 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
956 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
957 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
958 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
959 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
962 /* mode 2 - fits in 4KB */
963 static struct fifo_cfg __initdata mode_2_cfg[] = {
964 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
965 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
966 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
967 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
968 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
969 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
972 /* mode 3 - fits in 4KB */
973 static struct fifo_cfg __initdata mode_3_cfg[] = {
974 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
975 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
976 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
977 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
978 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
979 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
982 /* mode 4 - fits in 16KB */
983 static struct fifo_cfg __initdata mode_4_cfg[] = {
984 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
985 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
986 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
987 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
988 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
989 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
990 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
991 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
992 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
993 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
994 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
995 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
996 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
997 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
998 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
999 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1000 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1001 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1002 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 512, },
1003 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 512, },
1004 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 512, },
1005 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 512, },
1006 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 512, },
1007 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 512, },
1008 { .hw_ep_num = 13, .style = FIFO_TX, .maxpacket = 512, },
1009 { .hw_ep_num = 13, .style = FIFO_RX, .maxpacket = 512, },
1010 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1011 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1016 * configure a fifo; for non-shared endpoints, this may be called
1017 * once for a tx fifo and once for an rx fifo.
1019 * returns negative errno or offset for next fifo.
1022 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1023 const struct fifo_cfg *cfg, u16 offset)
1025 void __iomem *mbase = musb->mregs;
1027 u16 maxpacket = cfg->maxpacket;
1028 u16 c_off = offset >> 3;
1031 /* expect hw_ep has already been zero-initialized */
1033 size = ffs(max(maxpacket, (u16) 8)) - 1;
1034 maxpacket = 1 << size;
1037 if (cfg->mode == BUF_DOUBLE) {
1038 if ((offset + (maxpacket << 1)) > DYN_FIFO_SIZE)
1040 c_size |= MUSB_FIFOSZ_DPB;
1042 if ((offset + maxpacket) > DYN_FIFO_SIZE)
1046 /* configure the FIFO */
1047 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1049 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1050 /* EP0 reserved endpoint for control, bidirectional;
1051 * EP1 reserved for bulk, two unidirection halves.
1053 if (hw_ep->epnum == 1)
1054 musb->bulk_ep = hw_ep;
1055 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1057 switch (cfg->style) {
1059 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
1060 musb_writew(mbase, MUSB_TXFIFOADD, c_off);
1061 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1062 hw_ep->max_packet_sz_tx = maxpacket;
1065 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
1066 musb_writew(mbase, MUSB_RXFIFOADD, c_off);
1067 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1068 hw_ep->max_packet_sz_rx = maxpacket;
1071 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
1072 musb_writew(mbase, MUSB_TXFIFOADD, c_off);
1073 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1074 hw_ep->max_packet_sz_rx = maxpacket;
1076 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
1077 musb_writew(mbase, MUSB_RXFIFOADD, c_off);
1078 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1079 hw_ep->max_packet_sz_tx = maxpacket;
1081 hw_ep->is_shared_fifo = TRUE;
1085 /* NOTE rx and tx endpoint irqs aren't managed separately,
1086 * which happens to be ok
1088 musb->epmask |= (1 << hw_ep->epnum);
1090 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1093 static struct fifo_cfg __initdata ep0_cfg = {
1094 .style = FIFO_RXTX, .maxpacket = 64,
1097 static int __init ep_config_from_table(struct musb *musb)
1099 const struct fifo_cfg *cfg;
1102 struct musb_hw_ep *hw_ep = musb->endpoints;
1104 switch (fifo_mode) {
1110 n = ARRAY_SIZE(mode_0_cfg);
1114 n = ARRAY_SIZE(mode_1_cfg);
1118 n = ARRAY_SIZE(mode_2_cfg);
1122 n = ARRAY_SIZE(mode_3_cfg);
1126 n = ARRAY_SIZE(mode_4_cfg);
1130 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1131 musb_driver_name, fifo_mode);
1134 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1135 // assert(offset > 0)
1137 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1138 * be better than static MUSB_C_NUM_EPS and DYN_FIFO_SIZE...
1141 for (i = 0; i < n; i++) {
1142 u8 epn = cfg->hw_ep_num;
1144 if (epn >= MUSB_C_NUM_EPS) {
1145 pr_debug( "%s: invalid ep %d\n",
1146 musb_driver_name, epn);
1149 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1151 pr_debug( "%s: mem overrun, ep %d\n",
1152 musb_driver_name, epn);
1156 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1159 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1161 n + 1, MUSB_C_NUM_EPS * 2 - 1,
1162 offset, DYN_FIFO_SIZE);
1164 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1165 if (!musb->bulk_ep) {
1166 pr_debug( "%s: missing bulk\n", musb_driver_name);
1176 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1177 * @param musb the controller
1179 static int __init ep_config_from_hw(struct musb *musb)
1182 struct musb_hw_ep *hw_ep;
1183 void *mbase = musb->mregs;
1185 DBG(2, "<== static silicon ep config\n");
1187 /* FIXME pick up ep0 maxpacket size */
1189 for (epnum = 1; epnum < MUSB_C_NUM_EPS; epnum++) {
1190 musb_ep_select(mbase, epnum);
1191 hw_ep = musb->endpoints + epnum;
1193 /* read from core using indexed model */
1194 reg = musb_readb(hw_ep->regs, 0x10 + MUSB_FIFOSIZE);
1196 /* 0's returned when no more endpoints */
1199 musb->nr_endpoints++;
1200 musb->epmask |= (1 << epnum);
1202 hw_ep->max_packet_sz_tx = 1 << (reg & 0x0f);
1204 /* shared TX/RX FIFO? */
1205 if ((reg & 0xf0) == 0xf0) {
1206 hw_ep->max_packet_sz_rx = hw_ep->max_packet_sz_tx;
1207 hw_ep->is_shared_fifo = TRUE;
1210 hw_ep->max_packet_sz_rx = 1 << ((reg & 0xf0) >> 4);
1211 hw_ep->is_shared_fifo = FALSE;
1214 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1216 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1217 /* pick an RX/TX endpoint for bulk */
1218 if (hw_ep->max_packet_sz_tx < 512
1219 || hw_ep->max_packet_sz_rx < 512)
1222 /* REVISIT: this algorithm is lazy, we should at least
1223 * try to pick a double buffered endpoint.
1227 musb->bulk_ep = hw_ep;
1231 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1232 if (!musb->bulk_ep) {
1233 pr_debug( "%s: missing bulk\n", musb_driver_name);
1241 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1243 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1244 * configure endpoints, or take their config from silicon
1246 static int __init musb_core_init(u16 musb_type, struct musb *musb)
1253 u16 hwvers, rev_major, rev_minor;
1254 char aInfo[78], aRevision[32], aDate[12];
1255 void __iomem *mbase = musb->mregs;
1259 /* log core options (read using indexed model) */
1260 musb_ep_select(mbase, 0);
1261 reg = musb_readb(mbase, 0x10 + MUSB_CONFIGDATA);
1263 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1264 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1265 strcat(aInfo, ", dyn FIFOs");
1267 if (reg & MUSB_CONFIGDATA_MPRXE) {
1268 strcat(aInfo, ", bulk combine");
1270 musb->bulk_combine = TRUE;
1272 strcat(aInfo, " (X)"); /* no driver support */
1275 if (reg & MUSB_CONFIGDATA_MPTXE) {
1276 strcat(aInfo, ", bulk split");
1278 musb->bulk_split = TRUE;
1280 strcat(aInfo, " (X)"); /* no driver support */
1283 if (reg & MUSB_CONFIGDATA_HBRXE) {
1284 strcat(aInfo, ", HB-ISO Rx");
1285 strcat(aInfo, " (X)"); /* no driver support */
1287 if (reg & MUSB_CONFIGDATA_HBTXE) {
1288 strcat(aInfo, ", HB-ISO Tx");
1289 strcat(aInfo, " (X)"); /* no driver support */
1291 if (reg & MUSB_CONFIGDATA_SOFTCONE) {
1292 strcat(aInfo, ", SoftConn");
1295 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1296 musb_driver_name, reg, aInfo);
1299 data = musb_readl(mbase, 0x404);
1300 sprintf(aDate, "%04d-%02x-%02x", (data & 0xffff),
1301 (data >> 16) & 0xff, (data >> 24) & 0xff);
1302 /* FIXME ID2 and ID3 are unused */
1303 data = musb_readl(mbase, 0x408);
1304 printk("ID2=%lx\n", (long unsigned)data);
1305 data = musb_readl(mbase, 0x40c);
1306 printk("ID3=%lx\n", (long unsigned)data);
1307 reg = musb_readb(mbase, 0x400);
1308 musb_type = ('M' == reg) ? MUSB_CONTROLLER_MHDRC : MUSB_CONTROLLER_HDRC;
1312 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1313 musb->is_multipoint = 1;
1316 musb->is_multipoint = 0;
1318 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1319 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1321 "%s: kernel must blacklist external hubs\n",
1327 /* log release info */
1328 hwvers = musb_readw(mbase, MUSB_HWVERS);
1329 rev_major = (hwvers >> 10) & 0x1f;
1330 rev_minor = hwvers & 0x3ff;
1331 snprintf(aRevision, 32, "%d.%d%s", rev_major,
1332 rev_minor, (hwvers & 0x8000) ? "RC" : "");
1333 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1334 musb_driver_name, type, aRevision, aDate);
1337 musb->endpoints[0].max_packet_sz_tx = MUSB_EP0_FIFOSIZE;
1338 musb->endpoints[0].max_packet_sz_rx = MUSB_EP0_FIFOSIZE;
1340 /* discover endpoint configuration */
1341 musb->nr_endpoints = 1;
1344 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1346 status = ep_config_from_table(musb);
1348 ERR("reconfigure software for Dynamic FIFOs\n");
1353 status = ep_config_from_hw(musb);
1355 ERR("reconfigure software for static FIFOs\n");
1363 /* finish init, and print endpoint config */
1364 for (i = 0; i < musb->nr_endpoints; i++) {
1365 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1367 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1368 #ifdef CONFIG_USB_TUSB6010
1369 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1370 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1371 hw_ep->fifo_sync_va =
1372 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1375 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1377 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1380 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1381 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1382 hw_ep->target_regs = MUSB_BUSCTL_OFFSET(i, 0) + mbase;
1383 hw_ep->rx_reinit = 1;
1384 hw_ep->tx_reinit = 1;
1387 if (hw_ep->max_packet_sz_tx) {
1389 "%s: hw_ep %d%s, %smax %d\n",
1390 musb_driver_name, i,
1391 hw_ep->is_shared_fifo ? "shared" : "tx",
1392 hw_ep->tx_double_buffered
1393 ? "doublebuffer, " : "",
1394 hw_ep->max_packet_sz_tx);
1396 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1398 "%s: hw_ep %d%s, %smax %d\n",
1399 musb_driver_name, i,
1401 hw_ep->rx_double_buffered
1402 ? "doublebuffer, " : "",
1403 hw_ep->max_packet_sz_rx);
1405 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1406 DBG(1, "hw_ep %d not configured\n", i);
1412 /*-------------------------------------------------------------------------*/
1414 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
1416 static irqreturn_t generic_interrupt(int irq, void *__hci)
1418 unsigned long flags;
1419 irqreturn_t retval = IRQ_NONE;
1420 struct musb *musb = __hci;
1422 spin_lock_irqsave(&musb->lock, flags);
1424 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1425 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1426 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1428 if (musb->int_usb || musb->int_tx || musb->int_rx)
1429 retval = musb_interrupt(musb);
1431 spin_unlock_irqrestore(&musb->lock, flags);
1433 /* REVISIT we sometimes get spurious IRQs on g_ep0
1436 if (retval != IRQ_HANDLED)
1437 DBG(5, "spurious?\n");
1443 #define generic_interrupt NULL
1447 * handle all the irqs defined by the HDRC core. for now we expect: other
1448 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1449 * will be assigned, and the irq will already have been acked.
1451 * called in irq context with spinlock held, irqs blocked
1453 irqreturn_t musb_interrupt(struct musb *musb)
1455 irqreturn_t retval = IRQ_NONE;
1460 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1461 power = musb_readb(musb->mregs, MUSB_POWER);
1463 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
1464 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1465 musb->int_usb, musb->int_tx, musb->int_rx);
1467 /* the core can interrupt us for multiple reasons; docs have
1468 * a generic interrupt flowchart to follow
1470 if (musb->int_usb & STAGE0_MASK)
1471 retval |= musb_stage0_irq(musb, musb->int_usb,
1474 /* "stage 1" is handling endpoint irqs */
1476 /* handle endpoint 0 first */
1477 if (musb->int_tx & 1) {
1478 if (devctl & MUSB_DEVCTL_HM)
1479 retval |= musb_h_ep0_irq(musb);
1481 retval |= musb_g_ep0_irq(musb);
1484 /* RX on endpoints 1-15 */
1485 reg = musb->int_rx >> 1;
1489 // musb_ep_select(musb->mregs, ep_num);
1490 /* REVISIT just retval = ep->rx_irq(...) */
1491 retval = IRQ_HANDLED;
1492 if (devctl & MUSB_DEVCTL_HM) {
1493 if (is_host_capable())
1494 musb_host_rx(musb, ep_num);
1496 if (is_peripheral_capable())
1497 musb_g_rx(musb, ep_num);
1505 /* TX on endpoints 1-15 */
1506 reg = musb->int_tx >> 1;
1510 // musb_ep_select(musb->mregs, ep_num);
1511 /* REVISIT just retval |= ep->tx_irq(...) */
1512 retval = IRQ_HANDLED;
1513 if (devctl & MUSB_DEVCTL_HM) {
1514 if (is_host_capable())
1515 musb_host_tx(musb, ep_num);
1517 if (is_peripheral_capable())
1518 musb_g_tx(musb, ep_num);
1525 /* finish handling "global" interrupts after handling fifos */
1527 retval |= musb_stage2_irq(musb,
1528 musb->int_usb, devctl, power);
1534 #ifndef CONFIG_MUSB_PIO_ONLY
1535 static int __initdata use_dma = 1;
1537 /* "modprobe ... use_dma=0" etc */
1538 module_param(use_dma, bool, 0);
1539 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1541 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1543 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1545 /* called with controller lock already held */
1548 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1549 if (!is_cppi_enabled()) {
1551 if (devctl & MUSB_DEVCTL_HM)
1552 musb_h_ep0_irq(musb);
1554 musb_g_ep0_irq(musb);
1558 /* endpoints 1..15 */
1560 if (devctl & MUSB_DEVCTL_HM) {
1561 if (is_host_capable())
1562 musb_host_tx(musb, epnum);
1564 if (is_peripheral_capable())
1565 musb_g_tx(musb, epnum);
1569 if (devctl & MUSB_DEVCTL_HM) {
1570 if (is_host_capable())
1571 musb_host_rx(musb, epnum);
1573 if (is_peripheral_capable())
1574 musb_g_rx(musb, epnum);
1584 /*-------------------------------------------------------------------------*/
1589 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1591 struct musb *musb = dev_to_musb(dev);
1592 unsigned long flags;
1595 spin_lock_irqsave(&musb->lock, flags);
1596 ret = sprintf(buf, "%s\n", otg_state_string(musb));
1597 spin_unlock_irqrestore(&musb->lock, flags);
1603 musb_mode_store(struct device *dev, struct device_attribute *attr,
1604 const char *buf, size_t n)
1606 struct musb *musb = dev_to_musb(dev);
1607 unsigned long flags;
1609 spin_lock_irqsave(&musb->lock, flags);
1610 if (!strncmp(buf, "host", 4))
1611 musb_platform_set_mode(musb, MUSB_HOST);
1612 if (!strncmp(buf, "peripheral", 10))
1613 musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1614 if (!strncmp(buf, "otg", 3))
1615 musb_platform_set_mode(musb, MUSB_OTG);
1616 spin_unlock_irqrestore(&musb->lock, flags);
1620 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1623 musb_cable_show(struct device *dev, struct device_attribute *attr, char *buf)
1625 struct musb *musb = dev_to_musb(dev);
1626 char *v1= "", *v2 = "?";
1627 unsigned long flags;
1630 spin_lock_irqsave(&musb->lock, flags);
1631 #if defined(CONFIG_USB_TUSB6010) && !defined(CONFIG_USB_MUSB_OTG)
1632 /* REVISIT: connect-A != connect-B ... */
1633 vbus = musb_platform_get_vbus_status(musb);
1637 v2 = "disconnected";
1639 /* NOTE: board-specific issues, like too-big capacitors keeping
1640 * VBUS high for a long time after power has been removed, can
1641 * cause temporary false indications of a connection.
1643 vbus = musb_readb(musb->mregs, MUSB_DEVCTL);
1645 /* REVISIT retest on real OTG hardware */
1646 switch (musb->board_mode) {
1650 case MUSB_PERIPHERAL:
1655 v2 = (vbus & MUSB_DEVCTL_BDEVICE) ? "B" : "A";
1658 } else /* VBUS level below A-Valid */
1659 v2 = "disconnected";
1661 musb_platform_try_idle(musb, 0);
1662 spin_unlock_irqrestore(&musb->lock, flags);
1664 return sprintf(buf, "%s%s\n", v1, v2);
1666 static DEVICE_ATTR(cable, S_IRUGO, musb_cable_show, NULL);
1669 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1670 const char *buf, size_t n)
1672 struct musb *musb = dev_to_musb(dev);
1673 unsigned long flags;
1676 spin_lock_irqsave(&musb->lock, flags);
1677 if (sscanf(buf, "%lu", &val) < 1) {
1678 printk(KERN_ERR "Invalid VBUS timeout ms value\n");
1681 musb->a_wait_bcon = val;
1682 if (musb->xceiv.state == OTG_STATE_A_WAIT_BCON)
1683 musb->is_active = 0;
1684 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1685 spin_unlock_irqrestore(&musb->lock, flags);
1691 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1693 struct musb *musb = dev_to_musb(dev);
1694 unsigned long flags;
1697 spin_lock_irqsave(&musb->lock, flags);
1698 val = musb->a_wait_bcon;
1699 spin_unlock_irqrestore(&musb->lock, flags);
1701 return sprintf(buf, "%lu\n", val);
1703 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1705 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1707 /* Gadget drivers can't know that a host is connected so they might want
1708 * to start SRP, but users can. This allows userspace to trigger SRP.
1711 musb_srp_store(struct device *dev, struct device_attribute *attr,
1712 const char *buf, size_t n)
1714 struct musb *musb=dev_to_musb(dev);
1717 if (sscanf(buf, "%hu", &srp) != 1
1719 printk (KERN_ERR "SRP: Value must be 1\n");
1724 musb_g_wakeup(musb);
1728 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1730 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
1734 /* Only used to provide cable state change events */
1735 static void musb_irq_work(struct work_struct *data)
1737 struct musb *musb = container_of(data, struct musb, irq_work);
1739 sysfs_notify(&musb->controller->kobj, NULL, "cable");
1742 /* --------------------------------------------------------------------------
1746 static struct musb *__init
1747 allocate_instance(struct device *dev, void __iomem *mbase)
1750 struct musb_hw_ep *ep;
1752 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1753 struct usb_hcd *hcd;
1755 hcd = usb_create_hcd(&musb_hc_driver, dev, dev->bus_id);
1758 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1760 musb = hcd_to_musb(hcd);
1761 INIT_LIST_HEAD(&musb->control);
1762 INIT_LIST_HEAD(&musb->in_bulk);
1763 INIT_LIST_HEAD(&musb->out_bulk);
1765 hcd->uses_new_polling = 1;
1767 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1769 musb = kzalloc(sizeof *musb, GFP_KERNEL);
1772 dev_set_drvdata(dev, musb);
1776 musb->mregs = mbase;
1777 musb->ctrl_base = mbase;
1778 musb->nIrq = -ENODEV;
1779 for (epnum = 0, ep = musb->endpoints;
1780 epnum < MUSB_C_NUM_EPS;
1787 musb->controller = dev;
1791 static void musb_free(struct musb *musb)
1793 /* this has multiple entry modes. it handles fault cleanup after
1794 * probe(), where things may be partially set up, as well as rmmod
1795 * cleanup after everything's been de-activated.
1799 device_remove_file(musb->controller, &dev_attr_mode);
1800 device_remove_file(musb->controller, &dev_attr_cable);
1801 device_remove_file(musb->controller, &dev_attr_vbus);
1802 #ifdef CONFIG_USB_MUSB_OTG
1803 device_remove_file(musb->controller, &dev_attr_srp);
1807 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1808 musb_gadget_cleanup(musb);
1811 if (musb->nIrq >= 0) {
1812 disable_irq_wake(musb->nIrq);
1813 free_irq(musb->nIrq, musb);
1815 if (is_dma_capable() && musb->dma_controller) {
1816 struct dma_controller *c = musb->dma_controller;
1818 (void) c->stop(c->private_data);
1819 dma_controller_destroy(c);
1822 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1823 musb_platform_exit(musb);
1824 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1827 clk_disable(musb->clock);
1828 clk_put(musb->clock);
1831 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1832 usb_put_hcd(musb_to_hcd(musb));
1839 * Perform generic per-controller initialization.
1841 * @pDevice: the controller (already clocked, etc)
1843 * @mregs: virtual address of controller registers,
1844 * not yet corrected for platform-specific offsets
1847 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1851 struct musb_hdrc_platform_data *plat = dev->platform_data;
1853 /* The driver might handle more features than the board; OK.
1854 * Fail when the board needs a feature that's not enabled.
1857 dev_dbg(dev, "no platform_data?\n");
1860 switch (plat->mode) {
1862 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1867 case MUSB_PERIPHERAL:
1868 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1874 #ifdef CONFIG_USB_MUSB_OTG
1880 dev_err(dev, "incompatible Kconfig role setting\n");
1885 musb = allocate_instance(dev, ctrl);
1889 spin_lock_init(&musb->lock);
1890 musb->board_mode = plat->mode;
1891 musb->board_set_power = plat->set_power;
1892 musb->set_clock = plat->set_clock;
1893 musb->min_power = plat->min_power;
1895 /* Clock usage is chip-specific ... functional clock (DaVinci,
1896 * OMAP2430), or PHY ref (some TUSB6010 boards). All this core
1897 * code does is make sure a clock handle is available; platform
1898 * code manages it during start/stop and suspend/resume.
1901 musb->clock = clk_get(dev, plat->clock);
1902 if (IS_ERR(musb->clock)) {
1903 status = PTR_ERR(musb->clock);
1909 /* assume vbus is off */
1911 /* platform adjusts musb->mregs and musb->isr if needed,
1912 * and activates clocks
1914 musb->isr = generic_interrupt;
1915 status = musb_platform_init(musb);
1924 #ifndef CONFIG_MUSB_PIO_ONLY
1925 if (use_dma && dev->dma_mask) {
1926 struct dma_controller *c;
1928 c = dma_controller_create(musb, musb->mregs);
1929 musb->dma_controller = c;
1931 (void) c->start(c->private_data);
1934 /* ideally this would be abstracted in platform setup */
1935 if (!is_dma_capable() || !musb->dma_controller)
1936 dev->dma_mask = NULL;
1938 /* be sure interrupts are disabled before connecting ISR */
1939 musb_platform_disable(musb);
1940 musb_generic_disable(musb);
1942 /* setup musb parts of the core (especially endpoints) */
1943 status = musb_core_init(plat->multipoint
1944 ? MUSB_CONTROLLER_MHDRC
1945 : MUSB_CONTROLLER_HDRC, musb);
1949 /* attach to the IRQ */
1950 if (request_irq (nIrq, musb->isr, 0, dev->bus_id, musb)) {
1951 dev_err(dev, "request_irq %d failed!\n", nIrq);
1956 // FIXME this handles wakeup irqs wrong
1957 if (enable_irq_wake(nIrq) == 0)
1958 device_init_wakeup(dev, 1);
1960 pr_info("%s: USB %s mode controller at %p using %s, IRQ %d\n",
1963 switch (musb->board_mode) {
1964 case MUSB_HOST: s = "Host"; break;
1965 case MUSB_PERIPHERAL: s = "Peripheral"; break;
1966 default: s = "OTG"; break;
1969 (is_dma_capable() && musb->dma_controller)
1973 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1974 /* host side needs more setup, except for no-host modes */
1975 if (musb->board_mode != MUSB_PERIPHERAL) {
1976 struct usb_hcd *hcd = musb_to_hcd(musb);
1978 if (musb->board_mode == MUSB_OTG)
1979 hcd->self.otg_port = 1;
1980 musb->xceiv.host = &hcd->self;
1981 hcd->power_budget = 2 * (plat->power ? : 250);
1983 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
1985 /* For the host-only role, we can activate right away.
1986 * (We expect the ID pin to be forcibly grounded!!)
1987 * Otherwise, wait till the gadget driver hooks up.
1989 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
1990 MUSB_HST_MODE(musb);
1991 musb->xceiv.default_a = 1;
1992 musb->xceiv.state = OTG_STATE_A_IDLE;
1994 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
1996 DBG(1, "%s mode, status %d, devctl %02x %c\n",
1998 musb_readb(musb->mregs, MUSB_DEVCTL),
1999 (musb_readb(musb->mregs, MUSB_DEVCTL)
2000 & MUSB_DEVCTL_BDEVICE
2003 } else /* peripheral is enabled */ {
2004 MUSB_DEV_MODE(musb);
2005 musb->xceiv.default_a = 0;
2006 musb->xceiv.state = OTG_STATE_B_IDLE;
2008 status = musb_gadget_setup(musb);
2010 DBG(1, "%s mode, status %d, dev%02x\n",
2011 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2013 musb_readb(musb->mregs, MUSB_DEVCTL));
2018 musb_debug_create("driver/musb_hdrc", musb);
2022 clk_put(musb->clock);
2023 device_init_wakeup(dev, 0);
2028 INIT_WORK(&musb->irq_work, musb_irq_work);
2031 status = device_create_file(dev, &dev_attr_mode);
2032 status = device_create_file(dev, &dev_attr_cable);
2033 status = device_create_file(dev, &dev_attr_vbus);
2034 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2035 status = device_create_file(dev, &dev_attr_srp);
2036 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
2043 musb_platform_exit(musb);
2047 /*-------------------------------------------------------------------------*/
2049 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2050 * bridge to a platform device; this driver then suffices.
2053 #ifndef CONFIG_MUSB_PIO_ONLY
2054 static u64 *orig_dma_mask;
2057 static int __init musb_probe(struct platform_device *pdev)
2059 struct device *dev = &pdev->dev;
2060 int irq = platform_get_irq(pdev, 0);
2061 struct resource *iomem;
2064 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2065 if (!iomem || irq == 0)
2068 base = ioremap(iomem->start, iomem->end - iomem->start + 1);
2070 dev_err(dev, "ioremap failed\n");
2074 #ifndef CONFIG_MUSB_PIO_ONLY
2075 /* clobbered by use_dma=n */
2076 orig_dma_mask = dev->dma_mask;
2078 return musb_init_controller(dev, irq, base);
2081 static int __devexit musb_remove(struct platform_device *pdev)
2083 struct musb *musb = dev_to_musb(&pdev->dev);
2084 void __iomem *ctrl_base = musb->ctrl_base;
2086 /* this gets called on rmmod.
2087 * - Host mode: host may still be active
2088 * - Peripheral mode: peripheral is deactivated (or never-activated)
2089 * - OTG mode: both roles are deactivated (or never-activated)
2091 musb_shutdown(pdev);
2092 musb_debug_delete("driver/musb_hdrc", musb);
2093 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2094 if (musb->board_mode == MUSB_HOST)
2095 usb_remove_hcd(musb_to_hcd(musb));
2099 device_init_wakeup(&pdev->dev, 0);
2100 #ifndef CONFIG_MUSB_PIO_ONLY
2101 pdev->dev.dma_mask = orig_dma_mask;
2108 static int musb_suspend(struct platform_device *pdev, pm_message_t message)
2110 unsigned long flags;
2111 struct musb *musb = dev_to_musb(&pdev->dev);
2116 spin_lock_irqsave(&musb->lock, flags);
2118 if (is_peripheral_active(musb)) {
2119 /* FIXME force disconnect unless we know USB will wake
2120 * the system up quickly enough to respond ...
2122 } else if (is_host_active(musb)) {
2123 /* we know all the children are suspended; sometimes
2124 * they will even be wakeup-enabled.
2128 if (musb->set_clock)
2129 musb->set_clock(musb->clock, 0);
2131 clk_disable(musb->clock);
2132 spin_unlock_irqrestore(&musb->lock, flags);
2136 static int musb_resume(struct platform_device *pdev)
2138 unsigned long flags;
2139 struct musb *musb = dev_to_musb(&pdev->dev);
2144 spin_lock_irqsave(&musb->lock, flags);
2146 if (musb->set_clock)
2147 musb->set_clock(musb->clock, 1);
2149 clk_enable(musb->clock);
2151 /* for static cmos like DaVinci, register values were preserved
2152 * unless for some reason the whole soc powered down and we're
2153 * not treating that as a whole-system restart (e.g. swsusp)
2155 spin_unlock_irqrestore(&musb->lock, flags);
2160 #define musb_suspend NULL
2161 #define musb_resume NULL
2164 static struct platform_driver musb_driver = {
2166 .name = (char *)musb_driver_name,
2167 .bus = &platform_bus_type,
2168 .owner = THIS_MODULE,
2170 .remove = __devexit_p(musb_remove),
2171 .shutdown = musb_shutdown,
2172 .suspend = musb_suspend,
2173 .resume = musb_resume,
2176 /*-------------------------------------------------------------------------*/
2178 static int __init musb_init(void)
2180 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2185 pr_info("%s: version " MUSB_VERSION ", "
2186 #ifdef CONFIG_MUSB_PIO_ONLY
2188 #elif defined(CONFIG_USB_TI_CPPI_DMA)
2190 #elif defined(CONFIG_USB_INVENTRA_DMA)
2192 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
2198 #ifdef CONFIG_USB_MUSB_OTG
2199 "otg (peripheral+host)"
2200 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
2202 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2206 musb_driver_name, debug);
2207 return platform_driver_probe(&musb_driver, musb_probe);
2210 /* make us init after usbcore and before usb
2211 * gadget and host-side drivers start to register
2213 subsys_initcall(musb_init);
2215 static void __exit musb_cleanup(void)
2217 platform_driver_unregister(&musb_driver);
2219 module_exit(musb_cleanup);