2 * MUSB OTG driver core code
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - <asm/arch/hdrc_cnf.h> for SOC or family details
86 * - platform_device for addressing, irq, and platform_data
87 * - platform_data is mostly for board-specific informarion
89 * Most of the conditional compilation will (someday) vanish.
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/platform_device.h>
104 #include <asm/arch/hardware.h>
105 #include <asm/arch/memory.h>
106 #include <asm/mach-types.h>
109 #include "musb_core.h"
112 #ifdef CONFIG_ARCH_DAVINCI
119 unsigned debug = MUSB_DEBUG;
120 module_param(debug, uint, 0);
121 MODULE_PARM_DESC(debug, "initial debug message level");
123 #define MUSB_VERSION_SUFFIX "/dbg"
126 const char *otg_state_string(struct musb *musb)
130 snprintf(buf, sizeof buf, "otg-%d", musb->xceiv.state);
135 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
136 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
138 #define MUSB_VERSION_BASE "6.0"
140 #ifndef MUSB_VERSION_SUFFIX
141 #define MUSB_VERSION_SUFFIX ""
143 #define MUSB_VERSION MUSB_VERSION_BASE MUSB_VERSION_SUFFIX
145 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
147 const char musb_driver_name[] = "musb_hdrc";
149 MODULE_DESCRIPTION(DRIVER_INFO);
150 MODULE_AUTHOR(DRIVER_AUTHOR);
151 MODULE_LICENSE("GPL");
154 /*-------------------------------------------------------------------------*/
156 static inline struct musb *dev_to_musb(struct device *dev)
158 #ifdef CONFIG_USB_MUSB_HDRC_HCD
159 /* usbcore insists dev->driver_data is a "struct hcd *" */
160 return hcd_to_musb(dev_get_drvdata(dev));
162 return dev_get_drvdata(dev);
166 /*-------------------------------------------------------------------------*/
168 #ifndef CONFIG_USB_TUSB6010
170 * Load an endpoint's FIFO
172 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
174 void __iomem *fifo = hw_ep->fifo;
178 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
179 'T', hw_ep->epnum, fifo, len, src);
181 /* we can't assume unaligned reads work */
182 if (likely((0x01 & (unsigned long) src) == 0)) {
185 /* best case is 32bit-aligned source address */
186 if ((0x02 & (unsigned long) src) == 0) {
188 writesl(fifo, src + index, len >> 2);
189 index += len & ~0x03;
192 musb_writew(fifo, 0, *(u16*)&src[index]);
197 writesw(fifo, src + index, len >> 1);
198 index += len & ~0x01;
202 musb_writeb(fifo, 0, src[index]);
205 writesb(fifo, src, len);
210 * Unload an endpoint's FIFO
212 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
214 void __iomem *fifo = hw_ep->fifo;
216 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
217 'R', hw_ep->epnum, fifo, len, dst);
219 /* we can't assume unaligned writes work */
220 if (likely((0x01 & (unsigned long) dst) == 0)) {
223 /* best case is 32bit-aligned destination address */
224 if ((0x02 & (unsigned long) dst) == 0) {
226 readsl(fifo, dst, len >> 2);
230 *(u16*)&dst[index] = musb_readw(fifo, 0);
235 readsw(fifo, dst, len >> 1);
240 dst[index] = musb_readb(fifo, 0);
243 readsb(fifo, dst, len);
247 #endif /* normal PIO */
250 /*-------------------------------------------------------------------------*/
252 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
253 static const u8 musb_test_packet[53] = {
254 /* implicit SYNC then DATA0 to start */
257 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
259 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
261 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
262 /* JJJJJJJKKKKKKK x8 */
263 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
265 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
266 /* JKKKKKKK x10, JK */
267 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
269 /* implicit CRC16 then EOP to end */
272 void musb_load_testpacket(struct musb *musb)
274 void __iomem *regs = musb->endpoints[0].regs;
276 musb_ep_select(musb->mregs, 0);
277 musb_write_fifo(musb->control_ep,
278 sizeof(musb_test_packet), musb_test_packet);
279 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
282 /*-------------------------------------------------------------------------*/
284 #ifdef CONFIG_USB_MUSB_OTG
287 * See also USB_OTG_1-3.pdf 6.6.5 Timers
288 * REVISIT: Are the other timers done in the hardware?
290 #define TB_ASE0_BRST 100 /* Min 3.125 ms */
293 * Handles OTG hnp timeouts, such as b_ase0_brst
295 void musb_otg_timer_func(unsigned long data)
297 struct musb *musb = (struct musb *)data;
300 spin_lock_irqsave(&musb->lock, flags);
301 if (musb->xceiv.state == OTG_STATE_B_WAIT_ACON) {
302 DBG(1, "HNP: B_WAIT_ACON timeout; back to B_PERIPHERAL\n");
303 musb_g_disconnect(musb);
304 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
307 spin_unlock_irqrestore(&musb->lock, flags);
310 static DEFINE_TIMER(musb_otg_timer, musb_otg_timer_func, 0, 0);
313 * Stops the B-device HNP state. Caller must take care of locking.
315 void musb_hnp_stop(struct musb *musb)
317 struct usb_hcd *hcd = musb_to_hcd(musb);
318 void __iomem *mbase = musb->mregs;
321 switch (musb->xceiv.state) {
322 case OTG_STATE_A_PERIPHERAL:
323 case OTG_STATE_A_WAIT_VFALL:
324 DBG(1, "HNP: Switching back to A-host\n");
325 musb_g_disconnect(musb);
326 musb->xceiv.state = OTG_STATE_A_IDLE;
330 case OTG_STATE_B_HOST:
331 DBG(1, "HNP: Disabling HR\n");
332 hcd->self.is_b_host = 0;
333 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
335 reg = musb_readb(mbase, MUSB_POWER);
336 reg |= MUSB_POWER_SUSPENDM;
337 musb_writeb(mbase, MUSB_POWER, reg);
338 /* REVISIT: Start SESSION_REQUEST here? */
341 DBG(1, "HNP: Stopping in unknown state %s\n",
342 otg_state_string(musb));
346 * When returning to A state after HNP, avoid hub_port_rebounce(),
347 * which cause occasional OPT A "Did not receive reset after connect"
350 musb->port1_status &=
351 ~(1 << USB_PORT_FEAT_C_CONNECTION);
357 * Interrupt Service Routine to record USB "global" interrupts.
358 * Since these do not happen often and signify things of
359 * paramount importance, it seems OK to check them individually;
360 * the order of the tests is specified in the manual
362 * @param musb instance pointer
363 * @param int_usb register contents
368 #define STAGE0_MASK (MUSB_INTR_RESUME | MUSB_INTR_SESSREQ \
369 | MUSB_INTR_VBUSERROR | MUSB_INTR_CONNECT \
372 static irqreturn_t musb_stage0_irq(struct musb * musb, u8 int_usb,
375 irqreturn_t handled = IRQ_NONE;
376 void __iomem *mbase = musb->mregs;
378 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
381 /* in host mode, the peripheral may issue remote wakeup.
382 * in peripheral mode, the host may resume the link.
383 * spurious RESUME irqs happen too, paired with SUSPEND.
385 if (int_usb & MUSB_INTR_RESUME) {
386 handled = IRQ_HANDLED;
387 DBG(3, "RESUME (%s)\n", otg_state_string(musb));
389 if (devctl & MUSB_DEVCTL_HM) {
390 #ifdef CONFIG_USB_MUSB_HDRC_HCD
391 switch (musb->xceiv.state) {
392 case OTG_STATE_A_SUSPEND:
393 /* remote wakeup? later, GetPortStatus
394 * will stop RESUME signaling
397 if (power & MUSB_POWER_SUSPENDM) {
399 musb->int_usb &= ~MUSB_INTR_SUSPEND;
400 DBG(2, "Spurious SUSPENDM\n");
404 power &= ~MUSB_POWER_SUSPENDM;
405 musb_writeb(mbase, MUSB_POWER,
406 power | MUSB_POWER_RESUME);
408 musb->port1_status |=
409 (USB_PORT_STAT_C_SUSPEND << 16)
410 | MUSB_PORT_STAT_RESUME;
411 musb->rh_timer = jiffies
412 + msecs_to_jiffies(20);
414 musb->xceiv.state = OTG_STATE_A_HOST;
416 usb_hcd_resume_root_hub(musb_to_hcd(musb));
418 case OTG_STATE_B_WAIT_ACON:
419 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
424 WARN("bogus %s RESUME (%s)\n",
426 otg_state_string(musb));
430 switch (musb->xceiv.state) {
431 #ifdef CONFIG_USB_MUSB_HDRC_HCD
432 case OTG_STATE_A_SUSPEND:
433 /* possibly DISCONNECT is upcoming */
434 musb->xceiv.state = OTG_STATE_A_HOST;
435 usb_hcd_resume_root_hub(musb_to_hcd(musb));
438 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
439 case OTG_STATE_B_WAIT_ACON:
440 case OTG_STATE_B_PERIPHERAL:
441 /* disconnect while suspended? we may
442 * not get a disconnect irq...
444 if ((devctl & MUSB_DEVCTL_VBUS)
445 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
447 musb->int_usb |= MUSB_INTR_DISCONNECT;
448 musb->int_usb &= ~MUSB_INTR_SUSPEND;
453 case OTG_STATE_B_IDLE:
454 musb->int_usb &= ~MUSB_INTR_SUSPEND;
458 WARN("bogus %s RESUME (%s)\n",
460 otg_state_string(musb));
465 #ifdef CONFIG_USB_MUSB_HDRC_HCD
466 /* see manual for the order of the tests */
467 if (int_usb & MUSB_INTR_SESSREQ) {
468 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb));
470 /* IRQ arrives from ID pin sense or (later, if VBUS power
471 * is removed) SRP. responses are time critical:
472 * - turn on VBUS (with silicon-specific mechanism)
473 * - go through A_WAIT_VRISE
474 * - ... to A_WAIT_BCON.
475 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
477 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
478 musb->ep0_stage = MUSB_EP0_START;
479 musb->xceiv.state = OTG_STATE_A_IDLE;
481 musb_set_vbus(musb, 1);
483 handled = IRQ_HANDLED;
486 if (int_usb & MUSB_INTR_VBUSERROR) {
489 /* During connection as an A-Device, we may see a short
490 * current spikes causing voltage drop, because of cable
491 * and peripheral capacitance combined with vbus draw.
492 * (So: less common with truly self-powered devices, where
493 * vbus doesn't act like a power supply.)
495 * Such spikes are short; usually less than ~500 usec, max
496 * of ~2 msec. That is, they're not sustained overcurrent
497 * errors, though they're reported using VBUSERROR irqs.
499 * Workarounds: (a) hardware: use self powered devices.
500 * (b) software: ignore non-repeated VBUS errors.
502 * REVISIT: do delays from lots of DEBUG_KERNEL checks
503 * make trouble here, keeping VBUS < 4.4V ?
505 switch (musb->xceiv.state) {
506 case OTG_STATE_A_HOST:
507 /* recovery is dicey once we've gotten past the
508 * initial stages of enumeration, but if VBUS
509 * stayed ok at the other end of the link, and
510 * another reset is due (at least for high speed,
511 * to redo the chirp etc), it might work OK...
513 case OTG_STATE_A_WAIT_BCON:
514 case OTG_STATE_A_WAIT_VRISE:
515 if (musb->vbuserr_retry) {
516 musb->vbuserr_retry--;
518 devctl |= MUSB_DEVCTL_SESSION;
519 musb_writeb(mbase, MUSB_DEVCTL, devctl);
521 musb->port1_status |=
522 (1 << USB_PORT_FEAT_OVER_CURRENT)
523 | (1 << USB_PORT_FEAT_C_OVER_CURRENT);
530 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
531 otg_state_string(musb),
534 switch (devctl & MUSB_DEVCTL_VBUS) {
535 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
536 s = "<SessEnd"; break;
537 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
538 s = "<AValid"; break;
539 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
540 s = "<VBusValid"; break;
541 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
545 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
548 /* go through A_WAIT_VFALL then start a new session */
550 musb_set_vbus(musb, 0);
551 handled = IRQ_HANDLED;
554 if (int_usb & MUSB_INTR_CONNECT) {
555 struct usb_hcd *hcd = musb_to_hcd(musb);
557 handled = IRQ_HANDLED;
559 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
561 musb->ep0_stage = MUSB_EP0_START;
563 #ifdef CONFIG_USB_MUSB_OTG
564 /* flush endpoints when transitioning from Device Mode */
565 if (is_peripheral_active(musb)) {
566 /* REVISIT HNP; just force disconnect */
568 musb_writew(mbase, MUSB_INTRTXE, musb->epmask);
569 musb_writew(mbase, MUSB_INTRRXE, musb->epmask & 0xfffe);
570 musb_writeb(mbase, MUSB_INTRUSBE, 0xf7);
572 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
573 |USB_PORT_STAT_HIGH_SPEED
574 |USB_PORT_STAT_ENABLE
576 musb->port1_status |= USB_PORT_STAT_CONNECTION
577 |(USB_PORT_STAT_C_CONNECTION << 16);
579 /* high vs full speed is just a guess until after reset */
580 if (devctl & MUSB_DEVCTL_LSDEV)
581 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
584 usb_hcd_poll_rh_status(hcd);
586 usb_hcd_resume_root_hub(hcd);
590 /* indicate new connection to OTG machine */
591 switch (musb->xceiv.state) {
592 case OTG_STATE_B_PERIPHERAL:
593 if (int_usb & MUSB_INTR_SUSPEND) {
594 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n");
595 musb->xceiv.state = OTG_STATE_B_HOST;
596 hcd->self.is_b_host = 1;
597 int_usb &= ~MUSB_INTR_SUSPEND;
599 DBG(1, "CONNECT as b_peripheral???\n");
601 case OTG_STATE_B_WAIT_ACON:
602 DBG(1, "HNP: Waiting to switch to b_host state\n");
603 musb->xceiv.state = OTG_STATE_B_HOST;
604 hcd->self.is_b_host = 1;
607 if ((devctl & MUSB_DEVCTL_VBUS)
608 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
609 musb->xceiv.state = OTG_STATE_A_HOST;
610 hcd->self.is_b_host = 0;
614 DBG(1, "CONNECT (%s) devctl %02x\n",
615 otg_state_string(musb), devctl);
617 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
619 /* mentor saves a bit: bus reset and babble share the same irq.
620 * only host sees babble; only peripheral sees bus reset.
622 if (int_usb & MUSB_INTR_RESET) {
623 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
625 * Looks like non-HS BABBLE can be ignored, but
626 * HS BABBLE is an error condition. For HS the solution
627 * is to avoid babble in the first place and fix what
628 * caused BABBLE. When HS BABBLE happens we can only
631 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
632 DBG(1, "BABBLE devctl: %02x\n", devctl);
634 ERR("Stopping host session -- babble\n");
635 musb_writeb(mbase, MUSB_DEVCTL, 0);
637 } else if (is_peripheral_capable()) {
638 DBG(1, "BUS RESET\n");
641 schedule_work(&musb->irq_work);
644 handled = IRQ_HANDLED;
651 * Interrupt Service Routine to record USB "global" interrupts.
652 * Since these do not happen often and signify things of
653 * paramount importance, it seems OK to check them individually;
654 * the order of the tests is specified in the manual
656 * @param musb instance pointer
657 * @param int_usb register contents
661 static irqreturn_t musb_stage2_irq(struct musb * musb, u8 int_usb,
664 irqreturn_t handled = IRQ_NONE;
667 /* REVISIT ... this would be for multiplexing periodic endpoints, or
668 * supporting transfer phasing to prevent exceeding ISO bandwidth
669 * limits of a given frame or microframe.
671 * It's not needed for peripheral side, which dedicates endpoints;
672 * though it _might_ use SOF irqs for other purposes.
674 * And it's not currently needed for host side, which also dedicates
675 * endpoints, relies on TX/RX interval registers, and isn't claimed
676 * to support ISO transfers yet.
678 if (int_usb & MUSB_INTR_SOF) {
679 void __iomem *mbase = musb->mregs;
680 struct musb_hw_ep *ep;
684 DBG(6, "START_OF_FRAME\n");
685 handled = IRQ_HANDLED;
687 /* start any periodic Tx transfers waiting for current frame */
688 frame = musb_readw(mbase, MUSB_FRAME);
689 ep = musb->endpoints;
690 for (epnum = 1; (epnum < musb->nr_endpoints)
691 && (musb->epmask >= (1 << epnum));
694 * FIXME handle framecounter wraps (12 bits)
695 * eliminate duplicated StartUrb logic
697 if (ep->dwWaitFrame >= frame) {
699 printk("SOF --> periodic TX%s on %d\n",
700 ep->tx_channel ? " DMA" : "",
703 musb_h_tx_start(musb, epnum);
705 cppi_hostdma_start(musb, epnum);
707 } /* end of for loop */
711 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
712 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
713 otg_state_string(musb),
714 MUSB_MODE(musb), devctl);
715 handled = IRQ_HANDLED;
717 switch (musb->xceiv.state) {
718 #ifdef CONFIG_USB_MUSB_HDRC_HCD
719 case OTG_STATE_A_HOST:
720 case OTG_STATE_A_SUSPEND:
721 musb_root_disconnect(musb);
722 if (musb->a_wait_bcon != 0)
723 musb_platform_try_idle(musb, jiffies
724 + msecs_to_jiffies(musb->a_wait_bcon));
727 #ifdef CONFIG_USB_MUSB_OTG
728 case OTG_STATE_B_HOST:
731 case OTG_STATE_A_PERIPHERAL:
732 musb_root_disconnect(musb);
734 case OTG_STATE_B_WAIT_ACON:
737 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
738 case OTG_STATE_B_PERIPHERAL:
739 case OTG_STATE_B_IDLE:
740 musb_g_disconnect(musb);
744 WARN("unhandled DISCONNECT transition (%s)\n",
745 otg_state_string(musb));
749 schedule_work(&musb->irq_work);
752 if (int_usb & MUSB_INTR_SUSPEND) {
753 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
754 otg_state_string(musb), devctl, power);
755 handled = IRQ_HANDLED;
757 switch (musb->xceiv.state) {
758 #ifdef CONFIG_USB_MUSB_OTG
759 case OTG_STATE_A_PERIPHERAL:
763 case OTG_STATE_B_PERIPHERAL:
764 musb_g_suspend(musb);
765 musb->is_active = is_otg_enabled(musb)
766 && musb->xceiv.gadget->b_hnp_enable;
767 if (musb->is_active) {
768 musb->xceiv.state = OTG_STATE_B_WAIT_ACON;
769 #ifdef CONFIG_USB_MUSB_OTG
770 DBG(1, "HNP: Setting timer for b_ase0_brst\n");
771 musb_otg_timer.data = (unsigned long)musb;
772 mod_timer(&musb_otg_timer, jiffies
773 + msecs_to_jiffies(TB_ASE0_BRST));
777 case OTG_STATE_A_WAIT_BCON:
778 if (musb->a_wait_bcon != 0)
779 musb_platform_try_idle(musb, jiffies
780 + msecs_to_jiffies(musb->a_wait_bcon));
782 case OTG_STATE_A_HOST:
783 musb->xceiv.state = OTG_STATE_A_SUSPEND;
784 musb->is_active = is_otg_enabled(musb)
785 && musb->xceiv.host->b_hnp_enable;
787 case OTG_STATE_B_HOST:
788 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
789 DBG(1, "REVISIT: SUSPEND as B_HOST\n");
792 /* "should not happen" */
802 /*-------------------------------------------------------------------------*/
805 * Program the HDRC to start (enable interrupts, dma, etc.).
807 void musb_start(struct musb *musb)
809 void __iomem *regs = musb->mregs;
810 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
812 DBG(2, "<== devctl %02x\n", devctl);
814 /* Set INT enable registers, enable interrupts */
815 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
816 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
817 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
819 musb_writeb(regs, MUSB_TESTMODE, 0);
821 /* put into basic highspeed mode and start session */
822 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
823 | MUSB_POWER_SOFTCONN
825 /* ENSUSPEND wedges tusb */
826 /* | MUSB_POWER_ENSUSPEND */
830 devctl = musb_readb(regs, MUSB_DEVCTL);
831 devctl &= ~MUSB_DEVCTL_SESSION;
833 if (is_otg_enabled(musb)) {
834 /* session started after:
835 * (a) ID-grounded irq, host mode;
836 * (b) vbus present/connect IRQ, peripheral mode;
837 * (c) peripheral initiates, using SRP
839 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
842 devctl |= MUSB_DEVCTL_SESSION;
844 } else if (is_host_enabled(musb)) {
845 /* assume ID pin is hard-wired to ground */
846 devctl |= MUSB_DEVCTL_SESSION;
848 } else /* peripheral is enabled */ {
849 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
852 musb_platform_enable(musb);
853 musb_writeb(regs, MUSB_DEVCTL, devctl);
857 static void musb_generic_disable(struct musb *musb)
859 void __iomem *mbase = musb->mregs;
862 /* disable interrupts */
863 musb_writeb(mbase, MUSB_INTRUSBE, 0);
864 musb_writew(mbase, MUSB_INTRTXE, 0);
865 musb_writew(mbase, MUSB_INTRRXE, 0);
868 musb_writeb(mbase, MUSB_DEVCTL, 0);
870 /* flush pending interrupts */
871 temp = musb_readb(mbase, MUSB_INTRUSB);
872 temp = musb_readw(mbase, MUSB_INTRTX);
873 temp = musb_readw(mbase, MUSB_INTRRX);
878 * Make the HDRC stop (disable interrupts, etc.);
879 * reversible by musb_start
880 * called on gadget driver unregister
881 * with controller locked, irqs blocked
882 * acts as a NOP unless some role activated the hardware
884 void musb_stop(struct musb *musb)
886 /* stop IRQs, timers, ... */
887 musb_platform_disable(musb);
888 musb_generic_disable(musb);
889 DBG(3, "HDRC disabled\n");
892 * - mark host and/or peripheral drivers unusable/inactive
893 * - disable DMA (and enable it in HdrcStart)
894 * - make sure we can musb_start() after musb_stop(); with
895 * OTG mode, gadget driver module rmmod/modprobe cycles that
898 musb_platform_try_idle(musb, 0);
901 static void musb_shutdown(struct platform_device *pdev)
903 struct musb *musb = dev_to_musb(&pdev->dev);
906 spin_lock_irqsave(&musb->lock, flags);
907 musb_platform_disable(musb);
908 musb_generic_disable(musb);
910 clk_put(musb->clock);
913 spin_unlock_irqrestore(&musb->lock, flags);
915 /* FIXME power down */
919 /*-------------------------------------------------------------------------*/
922 * The silicon either has hard-wired endpoint configurations, or else
923 * "dynamic fifo" sizing. The driver has support for both, though at this
924 * writing only the dynamic sizing is very well tested. We use normal
925 * idioms to so both modes are compile-tested, but dead code elimination
926 * leaves only the relevant one in the object file.
928 * We don't currently use dynamic fifo setup capability to do anything
929 * more than selecting one of a bunch of predefined configurations.
931 #ifdef MUSB_C_DYNFIFO_DEF
932 #define can_dynfifo() 1
934 #define can_dynfifo() 0
937 #ifdef CONFIG_USB_TUSB6010
938 static ushort __initdata fifo_mode = 4;
940 static ushort __initdata fifo_mode = 2;
943 /* "modprobe ... fifo_mode=1" etc */
944 module_param(fifo_mode, ushort, 0);
945 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
948 #define DYN_FIFO_SIZE (1<<(MUSB_C_RAM_BITS+2))
950 enum fifo_style { FIFO_RXTX, FIFO_TX, FIFO_RX } __attribute__ ((packed));
951 enum buf_mode { BUF_SINGLE, BUF_DOUBLE } __attribute__ ((packed));
955 enum fifo_style style;
961 * tables defining fifo_mode values. define more if you like.
962 * for host side, make sure both halves of ep1 are set up.
965 /* mode 0 - fits in 2KB */
966 static struct fifo_cfg __initdata mode_0_cfg[] = {
967 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
968 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
969 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
970 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
971 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
974 /* mode 1 - fits in 4KB */
975 static struct fifo_cfg __initdata mode_1_cfg[] = {
976 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
977 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
978 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
979 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
980 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
983 /* mode 2 - fits in 4KB */
984 static struct fifo_cfg __initdata mode_2_cfg[] = {
985 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
986 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
987 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
988 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
989 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
990 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
993 /* mode 3 - fits in 4KB */
994 static struct fifo_cfg __initdata mode_3_cfg[] = {
995 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
996 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
997 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
998 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
999 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1000 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1003 /* mode 4 - fits in 16KB */
1004 static struct fifo_cfg __initdata mode_4_cfg[] = {
1005 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1006 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1007 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1008 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1009 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1010 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1011 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1012 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1013 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1014 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1015 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1016 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1017 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1018 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1019 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1020 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1021 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1022 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1023 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 512, },
1024 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 512, },
1025 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 512, },
1026 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 512, },
1027 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 512, },
1028 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 512, },
1029 { .hw_ep_num = 13, .style = FIFO_TX, .maxpacket = 512, },
1030 { .hw_ep_num = 13, .style = FIFO_RX, .maxpacket = 512, },
1031 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1032 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1037 * configure a fifo; for non-shared endpoints, this may be called
1038 * once for a tx fifo and once for an rx fifo.
1040 * returns negative errno or offset for next fifo.
1043 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1044 const struct fifo_cfg *cfg, u16 offset)
1046 void __iomem *mbase = musb->mregs;
1048 u16 maxpacket = cfg->maxpacket;
1049 u16 c_off = offset >> 3;
1052 /* expect hw_ep has already been zero-initialized */
1054 size = ffs(max(maxpacket, (u16) 8)) - 1;
1055 maxpacket = 1 << size;
1058 if (cfg->mode == BUF_DOUBLE) {
1059 if ((offset + (maxpacket << 1)) > DYN_FIFO_SIZE)
1061 c_size |= MUSB_FIFOSZ_DPB;
1063 if ((offset + maxpacket) > DYN_FIFO_SIZE)
1067 /* configure the FIFO */
1068 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1070 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1071 /* EP0 reserved endpoint for control, bidirectional;
1072 * EP1 reserved for bulk, two unidirection halves.
1074 if (hw_ep->epnum == 1)
1075 musb->bulk_ep = hw_ep;
1076 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1078 switch (cfg->style) {
1080 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
1081 musb_writew(mbase, MUSB_TXFIFOADD, c_off);
1082 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1083 hw_ep->max_packet_sz_tx = maxpacket;
1086 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
1087 musb_writew(mbase, MUSB_RXFIFOADD, c_off);
1088 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1089 hw_ep->max_packet_sz_rx = maxpacket;
1092 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
1093 musb_writew(mbase, MUSB_TXFIFOADD, c_off);
1094 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1095 hw_ep->max_packet_sz_rx = maxpacket;
1097 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
1098 musb_writew(mbase, MUSB_RXFIFOADD, c_off);
1099 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1100 hw_ep->max_packet_sz_tx = maxpacket;
1102 hw_ep->is_shared_fifo = true;
1106 /* NOTE rx and tx endpoint irqs aren't managed separately,
1107 * which happens to be ok
1109 musb->epmask |= (1 << hw_ep->epnum);
1111 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1114 static struct fifo_cfg __initdata ep0_cfg = {
1115 .style = FIFO_RXTX, .maxpacket = 64,
1118 static int __init ep_config_from_table(struct musb *musb)
1120 const struct fifo_cfg *cfg;
1123 struct musb_hw_ep *hw_ep = musb->endpoints;
1125 switch (fifo_mode) {
1131 n = ARRAY_SIZE(mode_0_cfg);
1135 n = ARRAY_SIZE(mode_1_cfg);
1139 n = ARRAY_SIZE(mode_2_cfg);
1143 n = ARRAY_SIZE(mode_3_cfg);
1147 n = ARRAY_SIZE(mode_4_cfg);
1151 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1152 musb_driver_name, fifo_mode);
1155 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1156 /* assert(offset > 0) */
1158 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1159 * be better than static MUSB_C_NUM_EPS and DYN_FIFO_SIZE...
1162 for (i = 0; i < n; i++) {
1163 u8 epn = cfg->hw_ep_num;
1165 if (epn >= MUSB_C_NUM_EPS) {
1166 pr_debug( "%s: invalid ep %d\n",
1167 musb_driver_name, epn);
1170 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1172 pr_debug( "%s: mem overrun, ep %d\n",
1173 musb_driver_name, epn);
1177 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1180 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1182 n + 1, MUSB_C_NUM_EPS * 2 - 1,
1183 offset, DYN_FIFO_SIZE);
1185 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1186 if (!musb->bulk_ep) {
1187 pr_debug( "%s: missing bulk\n", musb_driver_name);
1197 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1198 * @param musb the controller
1200 static int __init ep_config_from_hw(struct musb *musb)
1203 struct musb_hw_ep *hw_ep;
1204 void *mbase = musb->mregs;
1206 DBG(2, "<== static silicon ep config\n");
1208 /* FIXME pick up ep0 maxpacket size */
1210 for (epnum = 1; epnum < MUSB_C_NUM_EPS; epnum++) {
1211 musb_ep_select(mbase, epnum);
1212 hw_ep = musb->endpoints + epnum;
1214 /* read from core using indexed model */
1215 reg = musb_readb(hw_ep->regs, 0x10 + MUSB_FIFOSIZE);
1217 /* 0's returned when no more endpoints */
1220 musb->nr_endpoints++;
1221 musb->epmask |= (1 << epnum);
1223 hw_ep->max_packet_sz_tx = 1 << (reg & 0x0f);
1225 /* shared TX/RX FIFO? */
1226 if ((reg & 0xf0) == 0xf0) {
1227 hw_ep->max_packet_sz_rx = hw_ep->max_packet_sz_tx;
1228 hw_ep->is_shared_fifo = true;
1231 hw_ep->max_packet_sz_rx = 1 << ((reg & 0xf0) >> 4);
1232 hw_ep->is_shared_fifo = false;
1235 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1237 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1238 /* pick an RX/TX endpoint for bulk */
1239 if (hw_ep->max_packet_sz_tx < 512
1240 || hw_ep->max_packet_sz_rx < 512)
1243 /* REVISIT: this algorithm is lazy, we should at least
1244 * try to pick a double buffered endpoint.
1248 musb->bulk_ep = hw_ep;
1252 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1253 if (!musb->bulk_ep) {
1254 pr_debug( "%s: missing bulk\n", musb_driver_name);
1262 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1264 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1265 * configure endpoints, or take their config from silicon
1267 static int __init musb_core_init(u16 musb_type, struct musb *musb)
1274 u16 hwvers, rev_major, rev_minor;
1275 char aInfo[78], aRevision[32], aDate[12];
1276 void __iomem *mbase = musb->mregs;
1280 /* log core options (read using indexed model) */
1281 musb_ep_select(mbase, 0);
1282 reg = musb_readb(mbase, 0x10 + MUSB_CONFIGDATA);
1284 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1285 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1286 strcat(aInfo, ", dyn FIFOs");
1288 if (reg & MUSB_CONFIGDATA_MPRXE) {
1289 strcat(aInfo, ", bulk combine");
1291 musb->bulk_combine = true;
1293 strcat(aInfo, " (X)"); /* no driver support */
1296 if (reg & MUSB_CONFIGDATA_MPTXE) {
1297 strcat(aInfo, ", bulk split");
1299 musb->bulk_split = true;
1301 strcat(aInfo, " (X)"); /* no driver support */
1304 if (reg & MUSB_CONFIGDATA_HBRXE) {
1305 strcat(aInfo, ", HB-ISO Rx");
1306 strcat(aInfo, " (X)"); /* no driver support */
1308 if (reg & MUSB_CONFIGDATA_HBTXE) {
1309 strcat(aInfo, ", HB-ISO Tx");
1310 strcat(aInfo, " (X)"); /* no driver support */
1312 if (reg & MUSB_CONFIGDATA_SOFTCONE) {
1313 strcat(aInfo, ", SoftConn");
1316 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1317 musb_driver_name, reg, aInfo);
1320 data = musb_readl(mbase, 0x404);
1321 sprintf(aDate, "%04d-%02x-%02x", (data & 0xffff),
1322 (data >> 16) & 0xff, (data >> 24) & 0xff);
1323 /* FIXME ID2 and ID3 are unused */
1324 data = musb_readl(mbase, 0x408);
1325 printk("ID2=%lx\n", (long unsigned)data);
1326 data = musb_readl(mbase, 0x40c);
1327 printk("ID3=%lx\n", (long unsigned)data);
1328 reg = musb_readb(mbase, 0x400);
1329 musb_type = ('M' == reg) ? MUSB_CONTROLLER_MHDRC : MUSB_CONTROLLER_HDRC;
1333 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1334 musb->is_multipoint = 1;
1337 musb->is_multipoint = 0;
1339 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1340 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1342 "%s: kernel must blacklist external hubs\n",
1348 /* log release info */
1349 hwvers = musb_readw(mbase, MUSB_HWVERS);
1350 rev_major = (hwvers >> 10) & 0x1f;
1351 rev_minor = hwvers & 0x3ff;
1352 snprintf(aRevision, 32, "%d.%d%s", rev_major,
1353 rev_minor, (hwvers & 0x8000) ? "RC" : "");
1354 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1355 musb_driver_name, type, aRevision, aDate);
1358 musb->endpoints[0].max_packet_sz_tx = MUSB_EP0_FIFOSIZE;
1359 musb->endpoints[0].max_packet_sz_rx = MUSB_EP0_FIFOSIZE;
1361 /* discover endpoint configuration */
1362 musb->nr_endpoints = 1;
1365 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1367 status = ep_config_from_table(musb);
1369 ERR("reconfigure software for Dynamic FIFOs\n");
1374 status = ep_config_from_hw(musb);
1376 ERR("reconfigure software for static FIFOs\n");
1384 /* finish init, and print endpoint config */
1385 for (i = 0; i < musb->nr_endpoints; i++) {
1386 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1388 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1389 #ifdef CONFIG_USB_TUSB6010
1390 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1391 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1392 hw_ep->fifo_sync_va =
1393 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1396 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1398 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1401 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1402 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1403 hw_ep->target_regs = MUSB_BUSCTL_OFFSET(i, 0) + mbase;
1404 hw_ep->rx_reinit = 1;
1405 hw_ep->tx_reinit = 1;
1408 if (hw_ep->max_packet_sz_tx) {
1410 "%s: hw_ep %d%s, %smax %d\n",
1411 musb_driver_name, i,
1412 hw_ep->is_shared_fifo ? "shared" : "tx",
1413 hw_ep->tx_double_buffered
1414 ? "doublebuffer, " : "",
1415 hw_ep->max_packet_sz_tx);
1417 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1419 "%s: hw_ep %d%s, %smax %d\n",
1420 musb_driver_name, i,
1422 hw_ep->rx_double_buffered
1423 ? "doublebuffer, " : "",
1424 hw_ep->max_packet_sz_rx);
1426 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1427 DBG(1, "hw_ep %d not configured\n", i);
1433 /*-------------------------------------------------------------------------*/
1435 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
1437 static irqreturn_t generic_interrupt(int irq, void *__hci)
1439 unsigned long flags;
1440 irqreturn_t retval = IRQ_NONE;
1441 struct musb *musb = __hci;
1443 spin_lock_irqsave(&musb->lock, flags);
1445 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1446 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1447 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1449 if (musb->int_usb || musb->int_tx || musb->int_rx)
1450 retval = musb_interrupt(musb);
1452 spin_unlock_irqrestore(&musb->lock, flags);
1454 /* REVISIT we sometimes get spurious IRQs on g_ep0
1457 if (retval != IRQ_HANDLED)
1458 DBG(5, "spurious?\n");
1464 #define generic_interrupt NULL
1468 * handle all the irqs defined by the HDRC core. for now we expect: other
1469 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1470 * will be assigned, and the irq will already have been acked.
1472 * called in irq context with spinlock held, irqs blocked
1474 irqreturn_t musb_interrupt(struct musb *musb)
1476 irqreturn_t retval = IRQ_NONE;
1481 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1482 power = musb_readb(musb->mregs, MUSB_POWER);
1484 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
1485 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1486 musb->int_usb, musb->int_tx, musb->int_rx);
1488 /* the core can interrupt us for multiple reasons; docs have
1489 * a generic interrupt flowchart to follow
1491 if (musb->int_usb & STAGE0_MASK)
1492 retval |= musb_stage0_irq(musb, musb->int_usb,
1495 /* "stage 1" is handling endpoint irqs */
1497 /* handle endpoint 0 first */
1498 if (musb->int_tx & 1) {
1499 if (devctl & MUSB_DEVCTL_HM)
1500 retval |= musb_h_ep0_irq(musb);
1502 retval |= musb_g_ep0_irq(musb);
1505 /* RX on endpoints 1-15 */
1506 reg = musb->int_rx >> 1;
1510 /* musb_ep_select(musb->mregs, ep_num); */
1511 /* REVISIT just retval = ep->rx_irq(...) */
1512 retval = IRQ_HANDLED;
1513 if (devctl & MUSB_DEVCTL_HM) {
1514 if (is_host_capable())
1515 musb_host_rx(musb, ep_num);
1517 if (is_peripheral_capable())
1518 musb_g_rx(musb, ep_num);
1526 /* TX on endpoints 1-15 */
1527 reg = musb->int_tx >> 1;
1531 /* musb_ep_select(musb->mregs, ep_num); */
1532 /* REVISIT just retval |= ep->tx_irq(...) */
1533 retval = IRQ_HANDLED;
1534 if (devctl & MUSB_DEVCTL_HM) {
1535 if (is_host_capable())
1536 musb_host_tx(musb, ep_num);
1538 if (is_peripheral_capable())
1539 musb_g_tx(musb, ep_num);
1546 /* finish handling "global" interrupts after handling fifos */
1548 retval |= musb_stage2_irq(musb,
1549 musb->int_usb, devctl, power);
1555 #ifndef CONFIG_MUSB_PIO_ONLY
1556 static int __initdata use_dma = 1;
1558 /* "modprobe ... use_dma=0" etc */
1559 module_param(use_dma, bool, 0);
1560 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1562 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1564 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1566 /* called with controller lock already held */
1569 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1570 if (!is_cppi_enabled()) {
1572 if (devctl & MUSB_DEVCTL_HM)
1573 musb_h_ep0_irq(musb);
1575 musb_g_ep0_irq(musb);
1579 /* endpoints 1..15 */
1581 if (devctl & MUSB_DEVCTL_HM) {
1582 if (is_host_capable())
1583 musb_host_tx(musb, epnum);
1585 if (is_peripheral_capable())
1586 musb_g_tx(musb, epnum);
1590 if (devctl & MUSB_DEVCTL_HM) {
1591 if (is_host_capable())
1592 musb_host_rx(musb, epnum);
1594 if (is_peripheral_capable())
1595 musb_g_rx(musb, epnum);
1605 /*-------------------------------------------------------------------------*/
1610 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1612 struct musb *musb = dev_to_musb(dev);
1613 unsigned long flags;
1616 spin_lock_irqsave(&musb->lock, flags);
1617 ret = sprintf(buf, "%s\n", otg_state_string(musb));
1618 spin_unlock_irqrestore(&musb->lock, flags);
1624 musb_mode_store(struct device *dev, struct device_attribute *attr,
1625 const char *buf, size_t n)
1627 struct musb *musb = dev_to_musb(dev);
1628 unsigned long flags;
1630 spin_lock_irqsave(&musb->lock, flags);
1631 if (!strncmp(buf, "host", 4))
1632 musb_platform_set_mode(musb, MUSB_HOST);
1633 if (!strncmp(buf, "peripheral", 10))
1634 musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1635 if (!strncmp(buf, "otg", 3))
1636 musb_platform_set_mode(musb, MUSB_OTG);
1637 spin_unlock_irqrestore(&musb->lock, flags);
1641 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1644 musb_cable_show(struct device *dev, struct device_attribute *attr, char *buf)
1646 struct musb *musb = dev_to_musb(dev);
1647 char *v1= "", *v2 = "?";
1648 unsigned long flags;
1651 spin_lock_irqsave(&musb->lock, flags);
1652 #if defined(CONFIG_USB_TUSB6010) && !defined(CONFIG_USB_MUSB_OTG)
1653 /* REVISIT: connect-A != connect-B ... */
1654 vbus = musb_platform_get_vbus_status(musb);
1658 v2 = "disconnected";
1660 /* NOTE: board-specific issues, like too-big capacitors keeping
1661 * VBUS high for a long time after power has been removed, can
1662 * cause temporary false indications of a connection.
1664 vbus = musb_readb(musb->mregs, MUSB_DEVCTL);
1666 /* REVISIT retest on real OTG hardware */
1667 switch (musb->board_mode) {
1671 case MUSB_PERIPHERAL:
1676 v2 = (vbus & MUSB_DEVCTL_BDEVICE) ? "B" : "A";
1679 } else /* VBUS level below A-Valid */
1680 v2 = "disconnected";
1682 musb_platform_try_idle(musb, 0);
1683 spin_unlock_irqrestore(&musb->lock, flags);
1685 return sprintf(buf, "%s%s\n", v1, v2);
1687 static DEVICE_ATTR(cable, S_IRUGO, musb_cable_show, NULL);
1690 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1691 const char *buf, size_t n)
1693 struct musb *musb = dev_to_musb(dev);
1694 unsigned long flags;
1697 spin_lock_irqsave(&musb->lock, flags);
1698 if (sscanf(buf, "%lu", &val) < 1) {
1699 printk(KERN_ERR "Invalid VBUS timeout ms value\n");
1702 musb->a_wait_bcon = val;
1703 if (musb->xceiv.state == OTG_STATE_A_WAIT_BCON)
1704 musb->is_active = 0;
1705 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1706 spin_unlock_irqrestore(&musb->lock, flags);
1712 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1714 struct musb *musb = dev_to_musb(dev);
1715 unsigned long flags;
1718 spin_lock_irqsave(&musb->lock, flags);
1719 val = musb->a_wait_bcon;
1720 spin_unlock_irqrestore(&musb->lock, flags);
1722 return sprintf(buf, "%lu\n", val);
1724 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1726 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1728 /* Gadget drivers can't know that a host is connected so they might want
1729 * to start SRP, but users can. This allows userspace to trigger SRP.
1732 musb_srp_store(struct device *dev, struct device_attribute *attr,
1733 const char *buf, size_t n)
1735 struct musb *musb=dev_to_musb(dev);
1738 if (sscanf(buf, "%hu", &srp) != 1
1740 printk (KERN_ERR "SRP: Value must be 1\n");
1745 musb_g_wakeup(musb);
1749 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1751 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
1755 /* Only used to provide driver mode change events */
1756 static void musb_irq_work(struct work_struct *data)
1758 struct musb *musb = container_of(data, struct musb, irq_work);
1759 static int old_state;
1761 if (musb->xceiv.state != old_state) {
1762 old_state = musb->xceiv.state;
1763 sysfs_notify(&musb->controller->kobj, NULL, "cable");
1764 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1768 /* --------------------------------------------------------------------------
1772 static struct musb *__init
1773 allocate_instance(struct device *dev, void __iomem *mbase)
1776 struct musb_hw_ep *ep;
1778 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1779 struct usb_hcd *hcd;
1781 hcd = usb_create_hcd(&musb_hc_driver, dev, dev->bus_id);
1784 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1786 musb = hcd_to_musb(hcd);
1787 INIT_LIST_HEAD(&musb->control);
1788 INIT_LIST_HEAD(&musb->in_bulk);
1789 INIT_LIST_HEAD(&musb->out_bulk);
1791 hcd->uses_new_polling = 1;
1793 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1795 musb = kzalloc(sizeof *musb, GFP_KERNEL);
1798 dev_set_drvdata(dev, musb);
1802 musb->mregs = mbase;
1803 musb->ctrl_base = mbase;
1804 musb->nIrq = -ENODEV;
1805 for (epnum = 0, ep = musb->endpoints;
1806 epnum < MUSB_C_NUM_EPS;
1813 musb->controller = dev;
1817 static void musb_free(struct musb *musb)
1819 /* this has multiple entry modes. it handles fault cleanup after
1820 * probe(), where things may be partially set up, as well as rmmod
1821 * cleanup after everything's been de-activated.
1825 device_remove_file(musb->controller, &dev_attr_mode);
1826 device_remove_file(musb->controller, &dev_attr_cable);
1827 device_remove_file(musb->controller, &dev_attr_vbus);
1828 #ifdef CONFIG_USB_MUSB_OTG
1829 device_remove_file(musb->controller, &dev_attr_srp);
1833 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1834 musb_gadget_cleanup(musb);
1837 if (musb->nIrq >= 0) {
1838 disable_irq_wake(musb->nIrq);
1839 free_irq(musb->nIrq, musb);
1841 if (is_dma_capable() && musb->dma_controller) {
1842 struct dma_controller *c = musb->dma_controller;
1844 (void) c->stop(c->private_data);
1845 dma_controller_destroy(c);
1848 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1849 musb_platform_exit(musb);
1850 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1853 clk_disable(musb->clock);
1854 clk_put(musb->clock);
1857 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1858 usb_put_hcd(musb_to_hcd(musb));
1865 * Perform generic per-controller initialization.
1867 * @pDevice: the controller (already clocked, etc)
1869 * @mregs: virtual address of controller registers,
1870 * not yet corrected for platform-specific offsets
1873 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1877 struct musb_hdrc_platform_data *plat = dev->platform_data;
1879 /* The driver might handle more features than the board; OK.
1880 * Fail when the board needs a feature that's not enabled.
1883 dev_dbg(dev, "no platform_data?\n");
1886 switch (plat->mode) {
1888 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1893 case MUSB_PERIPHERAL:
1894 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1900 #ifdef CONFIG_USB_MUSB_OTG
1906 dev_err(dev, "incompatible Kconfig role setting\n");
1911 musb = allocate_instance(dev, ctrl);
1915 spin_lock_init(&musb->lock);
1916 musb->board_mode = plat->mode;
1917 musb->board_set_power = plat->set_power;
1918 musb->set_clock = plat->set_clock;
1919 musb->min_power = plat->min_power;
1921 /* Clock usage is chip-specific ... functional clock (DaVinci,
1922 * OMAP2430), or PHY ref (some TUSB6010 boards). All this core
1923 * code does is make sure a clock handle is available; platform
1924 * code manages it during start/stop and suspend/resume.
1927 musb->clock = clk_get(dev, plat->clock);
1928 if (IS_ERR(musb->clock)) {
1929 status = PTR_ERR(musb->clock);
1935 /* assume vbus is off */
1937 /* platform adjusts musb->mregs and musb->isr if needed,
1938 * and activates clocks
1940 musb->isr = generic_interrupt;
1941 status = musb_platform_init(musb);
1950 #ifndef CONFIG_MUSB_PIO_ONLY
1951 if (use_dma && dev->dma_mask) {
1952 struct dma_controller *c;
1954 c = dma_controller_create(musb, musb->mregs);
1955 musb->dma_controller = c;
1957 (void) c->start(c->private_data);
1960 /* ideally this would be abstracted in platform setup */
1961 if (!is_dma_capable() || !musb->dma_controller)
1962 dev->dma_mask = NULL;
1964 /* be sure interrupts are disabled before connecting ISR */
1965 musb_platform_disable(musb);
1966 musb_generic_disable(musb);
1968 /* setup musb parts of the core (especially endpoints) */
1969 status = musb_core_init(plat->multipoint
1970 ? MUSB_CONTROLLER_MHDRC
1971 : MUSB_CONTROLLER_HDRC, musb);
1975 /* attach to the IRQ */
1976 if (request_irq (nIrq, musb->isr, 0, dev->bus_id, musb)) {
1977 dev_err(dev, "request_irq %d failed!\n", nIrq);
1982 /* FIXME this handles wakeup irqs wrong */
1983 if (enable_irq_wake(nIrq) == 0)
1984 device_init_wakeup(dev, 1);
1986 pr_info("%s: USB %s mode controller at %p using %s, IRQ %d\n",
1989 switch (musb->board_mode) {
1990 case MUSB_HOST: s = "Host"; break;
1991 case MUSB_PERIPHERAL: s = "Peripheral"; break;
1992 default: s = "OTG"; break;
1995 (is_dma_capable() && musb->dma_controller)
1999 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2000 /* host side needs more setup, except for no-host modes */
2001 if (musb->board_mode != MUSB_PERIPHERAL) {
2002 struct usb_hcd *hcd = musb_to_hcd(musb);
2004 if (musb->board_mode == MUSB_OTG)
2005 hcd->self.otg_port = 1;
2006 musb->xceiv.host = &hcd->self;
2007 hcd->power_budget = 2 * (plat->power ? : 250);
2009 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
2011 /* For the host-only role, we can activate right away.
2012 * (We expect the ID pin to be forcibly grounded!!)
2013 * Otherwise, wait till the gadget driver hooks up.
2015 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2016 MUSB_HST_MODE(musb);
2017 musb->xceiv.default_a = 1;
2018 musb->xceiv.state = OTG_STATE_A_IDLE;
2020 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2022 DBG(1, "%s mode, status %d, devctl %02x %c\n",
2024 musb_readb(musb->mregs, MUSB_DEVCTL),
2025 (musb_readb(musb->mregs, MUSB_DEVCTL)
2026 & MUSB_DEVCTL_BDEVICE
2029 } else /* peripheral is enabled */ {
2030 MUSB_DEV_MODE(musb);
2031 musb->xceiv.default_a = 0;
2032 musb->xceiv.state = OTG_STATE_B_IDLE;
2034 status = musb_gadget_setup(musb);
2036 DBG(1, "%s mode, status %d, dev%02x\n",
2037 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2039 musb_readb(musb->mregs, MUSB_DEVCTL));
2044 musb_debug_create("driver/musb_hdrc", musb);
2048 clk_put(musb->clock);
2049 device_init_wakeup(dev, 0);
2054 INIT_WORK(&musb->irq_work, musb_irq_work);
2057 status = device_create_file(dev, &dev_attr_mode);
2058 status = device_create_file(dev, &dev_attr_cable);
2059 status = device_create_file(dev, &dev_attr_vbus);
2060 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2061 status = device_create_file(dev, &dev_attr_srp);
2062 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
2069 musb_platform_exit(musb);
2073 /*-------------------------------------------------------------------------*/
2075 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2076 * bridge to a platform device; this driver then suffices.
2079 #ifndef CONFIG_MUSB_PIO_ONLY
2080 static u64 *orig_dma_mask;
2083 static int __init musb_probe(struct platform_device *pdev)
2085 struct device *dev = &pdev->dev;
2086 int irq = platform_get_irq(pdev, 0);
2087 struct resource *iomem;
2090 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2091 if (!iomem || irq == 0)
2094 base = ioremap(iomem->start, iomem->end - iomem->start + 1);
2096 dev_err(dev, "ioremap failed\n");
2100 #ifndef CONFIG_MUSB_PIO_ONLY
2101 /* clobbered by use_dma=n */
2102 orig_dma_mask = dev->dma_mask;
2104 return musb_init_controller(dev, irq, base);
2107 static int __devexit musb_remove(struct platform_device *pdev)
2109 struct musb *musb = dev_to_musb(&pdev->dev);
2110 void __iomem *ctrl_base = musb->ctrl_base;
2112 /* this gets called on rmmod.
2113 * - Host mode: host may still be active
2114 * - Peripheral mode: peripheral is deactivated (or never-activated)
2115 * - OTG mode: both roles are deactivated (or never-activated)
2117 musb_shutdown(pdev);
2118 musb_debug_delete("driver/musb_hdrc", musb);
2119 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2120 if (musb->board_mode == MUSB_HOST)
2121 usb_remove_hcd(musb_to_hcd(musb));
2125 device_init_wakeup(&pdev->dev, 0);
2126 #ifndef CONFIG_MUSB_PIO_ONLY
2127 pdev->dev.dma_mask = orig_dma_mask;
2134 static int musb_suspend(struct platform_device *pdev, pm_message_t message)
2136 unsigned long flags;
2137 struct musb *musb = dev_to_musb(&pdev->dev);
2142 spin_lock_irqsave(&musb->lock, flags);
2144 if (is_peripheral_active(musb)) {
2145 /* FIXME force disconnect unless we know USB will wake
2146 * the system up quickly enough to respond ...
2148 } else if (is_host_active(musb)) {
2149 /* we know all the children are suspended; sometimes
2150 * they will even be wakeup-enabled.
2154 if (musb->set_clock)
2155 musb->set_clock(musb->clock, 0);
2157 clk_disable(musb->clock);
2158 spin_unlock_irqrestore(&musb->lock, flags);
2162 static int musb_resume(struct platform_device *pdev)
2164 unsigned long flags;
2165 struct musb *musb = dev_to_musb(&pdev->dev);
2170 spin_lock_irqsave(&musb->lock, flags);
2172 if (musb->set_clock)
2173 musb->set_clock(musb->clock, 1);
2175 clk_enable(musb->clock);
2177 /* for static cmos like DaVinci, register values were preserved
2178 * unless for some reason the whole soc powered down and we're
2179 * not treating that as a whole-system restart (e.g. swsusp)
2181 spin_unlock_irqrestore(&musb->lock, flags);
2186 #define musb_suspend NULL
2187 #define musb_resume NULL
2190 static struct platform_driver musb_driver = {
2192 .name = (char *)musb_driver_name,
2193 .bus = &platform_bus_type,
2194 .owner = THIS_MODULE,
2196 .remove = __devexit_p(musb_remove),
2197 .shutdown = musb_shutdown,
2198 .suspend = musb_suspend,
2199 .resume = musb_resume,
2202 /*-------------------------------------------------------------------------*/
2204 static int __init musb_init(void)
2206 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2211 pr_info("%s: version " MUSB_VERSION ", "
2212 #ifdef CONFIG_MUSB_PIO_ONLY
2214 #elif defined(CONFIG_USB_TI_CPPI_DMA)
2216 #elif defined(CONFIG_USB_INVENTRA_DMA)
2218 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
2224 #ifdef CONFIG_USB_MUSB_OTG
2225 "otg (peripheral+host)"
2226 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
2228 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2232 musb_driver_name, debug);
2233 return platform_driver_probe(&musb_driver, musb_probe);
2236 /* make us init after usbcore and before usb
2237 * gadget and host-side drivers start to register
2239 subsys_initcall(musb_init);
2241 static void __exit musb_cleanup(void)
2243 platform_driver_unregister(&musb_driver);
2245 module_exit(musb_cleanup);