2 * MUSB OTG driver core code
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - <asm/arch/hdrc_cnf.h> for SOC or family details
86 * - platform_device for addressing, irq, and platform_data
87 * - platform_data is mostly for board-specific informarion
89 * Most of the conditional compilation will (someday) vanish.
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/platform_device.h>
100 #include <linux/io.h>
103 #include <asm/arch/hardware.h>
104 #include <asm/arch/memory.h>
105 #include <asm/mach-types.h>
108 #include "musb_core.h"
111 #ifdef CONFIG_ARCH_DAVINCI
118 unsigned debug = MUSB_DEBUG;
119 module_param(debug, uint, 0);
120 MODULE_PARM_DESC(debug, "initial debug message level");
122 #define MUSB_VERSION_SUFFIX "/dbg"
125 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
126 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
128 #define MUSB_VERSION_BASE "6.0"
130 #ifndef MUSB_VERSION_SUFFIX
131 #define MUSB_VERSION_SUFFIX ""
133 #define MUSB_VERSION MUSB_VERSION_BASE MUSB_VERSION_SUFFIX
135 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
137 #define MUSB_DRIVER_NAME "musb_hdrc"
138 const char musb_driver_name[] = MUSB_DRIVER_NAME;
140 MODULE_DESCRIPTION(DRIVER_INFO);
141 MODULE_AUTHOR(DRIVER_AUTHOR);
142 MODULE_LICENSE("GPL");
143 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
146 /*-------------------------------------------------------------------------*/
148 static inline struct musb *dev_to_musb(struct device *dev)
150 #ifdef CONFIG_USB_MUSB_HDRC_HCD
151 /* usbcore insists dev->driver_data is a "struct hcd *" */
152 return hcd_to_musb(dev_get_drvdata(dev));
154 return dev_get_drvdata(dev);
158 /*-------------------------------------------------------------------------*/
160 #ifndef CONFIG_USB_TUSB6010
162 * Load an endpoint's FIFO
164 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
166 void __iomem *fifo = hw_ep->fifo;
170 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
171 'T', hw_ep->epnum, fifo, len, src);
173 /* we can't assume unaligned reads work */
174 if (likely((0x01 & (unsigned long) src) == 0)) {
177 /* best case is 32bit-aligned source address */
178 if ((0x02 & (unsigned long) src) == 0) {
180 writesl(fifo, src + index, len >> 2);
181 index += len & ~0x03;
184 musb_writew(fifo, 0, *(u16 *)&src[index]);
189 writesw(fifo, src + index, len >> 1);
190 index += len & ~0x01;
194 musb_writeb(fifo, 0, src[index]);
197 writesb(fifo, src, len);
202 * Unload an endpoint's FIFO
204 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
206 void __iomem *fifo = hw_ep->fifo;
208 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
209 'R', hw_ep->epnum, fifo, len, dst);
211 /* we can't assume unaligned writes work */
212 if (likely((0x01 & (unsigned long) dst) == 0)) {
215 /* best case is 32bit-aligned destination address */
216 if ((0x02 & (unsigned long) dst) == 0) {
218 readsl(fifo, dst, len >> 2);
222 *(u16 *)&dst[index] = musb_readw(fifo, 0);
227 readsw(fifo, dst, len >> 1);
232 dst[index] = musb_readb(fifo, 0);
235 readsb(fifo, dst, len);
239 #endif /* normal PIO */
242 /*-------------------------------------------------------------------------*/
244 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
245 static const u8 musb_test_packet[53] = {
246 /* implicit SYNC then DATA0 to start */
249 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
251 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
253 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
254 /* JJJJJJJKKKKKKK x8 */
255 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
257 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
258 /* JKKKKKKK x10, JK */
259 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
261 /* implicit CRC16 then EOP to end */
264 void musb_load_testpacket(struct musb *musb)
266 void __iomem *regs = musb->endpoints[0].regs;
268 musb_ep_select(musb->mregs, 0);
269 musb_write_fifo(musb->control_ep,
270 sizeof(musb_test_packet), musb_test_packet);
271 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
274 /*-------------------------------------------------------------------------*/
276 const char *otg_state_string(struct musb *musb)
278 switch (musb->xceiv.state) {
279 case OTG_STATE_A_IDLE: return "a_idle";
280 case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise";
281 case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon";
282 case OTG_STATE_A_HOST: return "a_host";
283 case OTG_STATE_A_SUSPEND: return "a_suspend";
284 case OTG_STATE_A_PERIPHERAL: return "a_peripheral";
285 case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall";
286 case OTG_STATE_A_VBUS_ERR: return "a_vbus_err";
287 case OTG_STATE_B_IDLE: return "b_idle";
288 case OTG_STATE_B_SRP_INIT: return "b_srp_init";
289 case OTG_STATE_B_PERIPHERAL: return "b_peripheral";
290 case OTG_STATE_B_WAIT_ACON: return "b_wait_acon";
291 case OTG_STATE_B_HOST: return "b_host";
292 default: return "UNDEFINED";
296 #ifdef CONFIG_USB_MUSB_OTG
299 * See also USB_OTG_1-3.pdf 6.6.5 Timers
300 * REVISIT: Are the other timers done in the hardware?
302 #define TB_ASE0_BRST 100 /* Min 3.125 ms */
305 * Handles OTG hnp timeouts, such as b_ase0_brst
307 void musb_otg_timer_func(unsigned long data)
309 struct musb *musb = (struct musb *)data;
312 spin_lock_irqsave(&musb->lock, flags);
313 switch (musb->xceiv.state) {
314 case OTG_STATE_B_WAIT_ACON:
315 DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n");
316 musb_g_disconnect(musb);
317 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
320 case OTG_STATE_A_WAIT_BCON:
321 DBG(1, "HNP: a_wait_bcon timeout; back to a_host\n");
325 DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb));
327 musb->ignore_disconnect = 0;
328 spin_unlock_irqrestore(&musb->lock, flags);
331 static DEFINE_TIMER(musb_otg_timer, musb_otg_timer_func, 0, 0);
334 * Stops the B-device HNP state. Caller must take care of locking.
336 void musb_hnp_stop(struct musb *musb)
338 struct usb_hcd *hcd = musb_to_hcd(musb);
339 void __iomem *mbase = musb->mregs;
342 switch (musb->xceiv.state) {
343 case OTG_STATE_A_PERIPHERAL:
344 case OTG_STATE_A_WAIT_VFALL:
345 case OTG_STATE_A_WAIT_BCON:
346 DBG(1, "HNP: Switching back to A-host\n");
347 musb_g_disconnect(musb);
348 musb->xceiv.state = OTG_STATE_A_IDLE;
352 case OTG_STATE_B_HOST:
353 DBG(1, "HNP: Disabling HR\n");
354 hcd->self.is_b_host = 0;
355 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
357 reg = musb_readb(mbase, MUSB_POWER);
358 reg |= MUSB_POWER_SUSPENDM;
359 musb_writeb(mbase, MUSB_POWER, reg);
360 /* REVISIT: Start SESSION_REQUEST here? */
363 DBG(1, "HNP: Stopping in unknown state %s\n",
364 otg_state_string(musb));
368 * When returning to A state after HNP, avoid hub_port_rebounce(),
369 * which cause occasional OPT A "Did not receive reset after connect"
372 musb->port1_status &=
373 ~(1 << USB_PORT_FEAT_C_CONNECTION);
379 * Interrupt Service Routine to record USB "global" interrupts.
380 * Since these do not happen often and signify things of
381 * paramount importance, it seems OK to check them individually;
382 * the order of the tests is specified in the manual
384 * @param musb instance pointer
385 * @param int_usb register contents
390 #define STAGE0_MASK (MUSB_INTR_RESUME | MUSB_INTR_SESSREQ \
391 | MUSB_INTR_VBUSERROR | MUSB_INTR_CONNECT \
394 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
397 irqreturn_t handled = IRQ_NONE;
398 void __iomem *mbase = musb->mregs;
400 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
403 /* in host mode, the peripheral may issue remote wakeup.
404 * in peripheral mode, the host may resume the link.
405 * spurious RESUME irqs happen too, paired with SUSPEND.
407 if (int_usb & MUSB_INTR_RESUME) {
408 handled = IRQ_HANDLED;
409 DBG(3, "RESUME (%s)\n", otg_state_string(musb));
411 if (devctl & MUSB_DEVCTL_HM) {
412 #ifdef CONFIG_USB_MUSB_HDRC_HCD
413 switch (musb->xceiv.state) {
414 case OTG_STATE_A_SUSPEND:
415 /* remote wakeup? later, GetPortStatus
416 * will stop RESUME signaling
419 if (power & MUSB_POWER_SUSPENDM) {
421 musb->int_usb &= ~MUSB_INTR_SUSPEND;
422 DBG(2, "Spurious SUSPENDM\n");
426 power &= ~MUSB_POWER_SUSPENDM;
427 musb_writeb(mbase, MUSB_POWER,
428 power | MUSB_POWER_RESUME);
430 musb->port1_status |=
431 (USB_PORT_STAT_C_SUSPEND << 16)
432 | MUSB_PORT_STAT_RESUME;
433 musb->rh_timer = jiffies
434 + msecs_to_jiffies(20);
436 musb->xceiv.state = OTG_STATE_A_HOST;
438 usb_hcd_resume_root_hub(musb_to_hcd(musb));
440 case OTG_STATE_B_WAIT_ACON:
441 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
446 WARN("bogus %s RESUME (%s)\n",
448 otg_state_string(musb));
452 switch (musb->xceiv.state) {
453 #ifdef CONFIG_USB_MUSB_HDRC_HCD
454 case OTG_STATE_A_SUSPEND:
455 /* possibly DISCONNECT is upcoming */
456 musb->xceiv.state = OTG_STATE_A_HOST;
457 usb_hcd_resume_root_hub(musb_to_hcd(musb));
460 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
461 case OTG_STATE_B_WAIT_ACON:
462 case OTG_STATE_B_PERIPHERAL:
463 /* disconnect while suspended? we may
464 * not get a disconnect irq...
466 if ((devctl & MUSB_DEVCTL_VBUS)
467 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
469 musb->int_usb |= MUSB_INTR_DISCONNECT;
470 musb->int_usb &= ~MUSB_INTR_SUSPEND;
475 case OTG_STATE_B_IDLE:
476 musb->int_usb &= ~MUSB_INTR_SUSPEND;
480 WARN("bogus %s RESUME (%s)\n",
482 otg_state_string(musb));
487 #ifdef CONFIG_USB_MUSB_HDRC_HCD
488 /* see manual for the order of the tests */
489 if (int_usb & MUSB_INTR_SESSREQ) {
490 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb));
492 /* IRQ arrives from ID pin sense or (later, if VBUS power
493 * is removed) SRP. responses are time critical:
494 * - turn on VBUS (with silicon-specific mechanism)
495 * - go through A_WAIT_VRISE
496 * - ... to A_WAIT_BCON.
497 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
499 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
500 musb->ep0_stage = MUSB_EP0_START;
501 musb->xceiv.state = OTG_STATE_A_IDLE;
503 musb_set_vbus(musb, 1);
505 handled = IRQ_HANDLED;
508 if (int_usb & MUSB_INTR_VBUSERROR) {
511 /* During connection as an A-Device, we may see a short
512 * current spikes causing voltage drop, because of cable
513 * and peripheral capacitance combined with vbus draw.
514 * (So: less common with truly self-powered devices, where
515 * vbus doesn't act like a power supply.)
517 * Such spikes are short; usually less than ~500 usec, max
518 * of ~2 msec. That is, they're not sustained overcurrent
519 * errors, though they're reported using VBUSERROR irqs.
521 * Workarounds: (a) hardware: use self powered devices.
522 * (b) software: ignore non-repeated VBUS errors.
524 * REVISIT: do delays from lots of DEBUG_KERNEL checks
525 * make trouble here, keeping VBUS < 4.4V ?
527 switch (musb->xceiv.state) {
528 case OTG_STATE_A_HOST:
529 /* recovery is dicey once we've gotten past the
530 * initial stages of enumeration, but if VBUS
531 * stayed ok at the other end of the link, and
532 * another reset is due (at least for high speed,
533 * to redo the chirp etc), it might work OK...
535 case OTG_STATE_A_WAIT_BCON:
536 case OTG_STATE_A_WAIT_VRISE:
537 if (musb->vbuserr_retry) {
538 musb->vbuserr_retry--;
540 devctl |= MUSB_DEVCTL_SESSION;
541 musb_writeb(mbase, MUSB_DEVCTL, devctl);
543 musb->port1_status |=
544 (1 << USB_PORT_FEAT_OVER_CURRENT)
545 | (1 << USB_PORT_FEAT_C_OVER_CURRENT);
552 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
553 otg_state_string(musb),
556 switch (devctl & MUSB_DEVCTL_VBUS) {
557 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
558 s = "<SessEnd"; break;
559 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
560 s = "<AValid"; break;
561 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
562 s = "<VBusValid"; break;
563 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
567 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
570 /* go through A_WAIT_VFALL then start a new session */
572 musb_set_vbus(musb, 0);
573 handled = IRQ_HANDLED;
576 if (int_usb & MUSB_INTR_CONNECT) {
577 struct usb_hcd *hcd = musb_to_hcd(musb);
579 handled = IRQ_HANDLED;
581 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
583 musb->ep0_stage = MUSB_EP0_START;
585 #ifdef CONFIG_USB_MUSB_OTG
586 /* flush endpoints when transitioning from Device Mode */
587 if (is_peripheral_active(musb)) {
588 /* REVISIT HNP; just force disconnect */
590 musb_writew(mbase, MUSB_INTRTXE, musb->epmask);
591 musb_writew(mbase, MUSB_INTRRXE, musb->epmask & 0xfffe);
592 musb_writeb(mbase, MUSB_INTRUSBE, 0xf7);
594 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
595 |USB_PORT_STAT_HIGH_SPEED
596 |USB_PORT_STAT_ENABLE
598 musb->port1_status |= USB_PORT_STAT_CONNECTION
599 |(USB_PORT_STAT_C_CONNECTION << 16);
601 /* high vs full speed is just a guess until after reset */
602 if (devctl & MUSB_DEVCTL_LSDEV)
603 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
606 usb_hcd_poll_rh_status(hcd);
608 usb_hcd_resume_root_hub(hcd);
612 /* indicate new connection to OTG machine */
613 switch (musb->xceiv.state) {
614 case OTG_STATE_B_PERIPHERAL:
615 if (int_usb & MUSB_INTR_SUSPEND) {
616 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n");
617 musb->xceiv.state = OTG_STATE_B_HOST;
618 hcd->self.is_b_host = 1;
619 int_usb &= ~MUSB_INTR_SUSPEND;
621 DBG(1, "CONNECT as b_peripheral???\n");
623 case OTG_STATE_B_WAIT_ACON:
624 DBG(1, "HNP: Waiting to switch to b_host state\n");
625 musb->xceiv.state = OTG_STATE_B_HOST;
626 hcd->self.is_b_host = 1;
629 if ((devctl & MUSB_DEVCTL_VBUS)
630 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
631 musb->xceiv.state = OTG_STATE_A_HOST;
632 hcd->self.is_b_host = 0;
636 DBG(1, "CONNECT (%s) devctl %02x\n",
637 otg_state_string(musb), devctl);
639 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
641 /* mentor saves a bit: bus reset and babble share the same irq.
642 * only host sees babble; only peripheral sees bus reset.
644 if (int_usb & MUSB_INTR_RESET) {
645 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
647 * Looks like non-HS BABBLE can be ignored, but
648 * HS BABBLE is an error condition. For HS the solution
649 * is to avoid babble in the first place and fix what
650 * caused BABBLE. When HS BABBLE happens we can only
653 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
654 DBG(1, "BABBLE devctl: %02x\n", devctl);
656 ERR("Stopping host session -- babble\n");
657 musb_writeb(mbase, MUSB_DEVCTL, 0);
659 } else if (is_peripheral_capable()) {
660 DBG(1, "BUS RESET as %s\n", otg_state_string(musb));
661 switch (musb->xceiv.state) {
662 #ifdef CONFIG_USB_OTG
663 case OTG_STATE_A_SUSPEND:
664 musb->ignore_disconnect = 0;
667 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
668 DBG(1, "HNP: Setting timer as %s\n",
669 otg_state_string(musb));
670 musb_otg_timer.data = (unsigned long)musb;
671 mod_timer(&musb_otg_timer, jiffies
672 + msecs_to_jiffies(100));
674 case OTG_STATE_A_PERIPHERAL:
677 case OTG_STATE_B_WAIT_ACON:
678 DBG(1, "HNP: RESET (%s), back to b_peripheral\n",
679 otg_state_string(musb));
680 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
684 case OTG_STATE_B_IDLE:
685 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
687 case OTG_STATE_B_PERIPHERAL:
691 DBG(1, "Unhandled BUS RESET as %s\n",
692 otg_state_string(musb));
696 handled = IRQ_HANDLED;
698 schedule_work(&musb->irq_work);
704 * Interrupt Service Routine to record USB "global" interrupts.
705 * Since these do not happen often and signify things of
706 * paramount importance, it seems OK to check them individually;
707 * the order of the tests is specified in the manual
709 * @param musb instance pointer
710 * @param int_usb register contents
714 static irqreturn_t musb_stage2_irq(struct musb *musb, u8 int_usb,
717 irqreturn_t handled = IRQ_NONE;
720 /* REVISIT ... this would be for multiplexing periodic endpoints, or
721 * supporting transfer phasing to prevent exceeding ISO bandwidth
722 * limits of a given frame or microframe.
724 * It's not needed for peripheral side, which dedicates endpoints;
725 * though it _might_ use SOF irqs for other purposes.
727 * And it's not currently needed for host side, which also dedicates
728 * endpoints, relies on TX/RX interval registers, and isn't claimed
729 * to support ISO transfers yet.
731 if (int_usb & MUSB_INTR_SOF) {
732 void __iomem *mbase = musb->mregs;
733 struct musb_hw_ep *ep;
737 DBG(6, "START_OF_FRAME\n");
738 handled = IRQ_HANDLED;
740 /* start any periodic Tx transfers waiting for current frame */
741 frame = musb_readw(mbase, MUSB_FRAME);
742 ep = musb->endpoints;
743 for (epnum = 1; (epnum < musb->nr_endpoints)
744 && (musb->epmask >= (1 << epnum));
747 * FIXME handle framecounter wraps (12 bits)
748 * eliminate duplicated StartUrb logic
750 if (ep->dwWaitFrame >= frame) {
752 printk("SOF --> periodic TX%s on %d\n",
753 ep->tx_channel ? " DMA" : "",
756 musb_h_tx_start(musb, epnum);
758 cppi_hostdma_start(musb, epnum);
760 } /* end of for loop */
764 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
765 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
766 otg_state_string(musb),
767 MUSB_MODE(musb), devctl);
768 handled = IRQ_HANDLED;
770 switch (musb->xceiv.state) {
771 #ifdef CONFIG_USB_MUSB_HDRC_HCD
772 case OTG_STATE_A_HOST:
773 case OTG_STATE_A_SUSPEND:
774 musb_root_disconnect(musb);
775 if (musb->a_wait_bcon != 0)
776 musb_platform_try_idle(musb, jiffies
777 + msecs_to_jiffies(musb->a_wait_bcon));
780 #ifdef CONFIG_USB_MUSB_OTG
781 case OTG_STATE_B_HOST:
784 case OTG_STATE_A_PERIPHERAL:
786 musb_root_disconnect(musb);
788 case OTG_STATE_B_WAIT_ACON:
791 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
792 case OTG_STATE_B_PERIPHERAL:
793 case OTG_STATE_B_IDLE:
794 musb_g_disconnect(musb);
798 WARN("unhandled DISCONNECT transition (%s)\n",
799 otg_state_string(musb));
803 schedule_work(&musb->irq_work);
806 if (int_usb & MUSB_INTR_SUSPEND) {
807 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
808 otg_state_string(musb), devctl, power);
809 handled = IRQ_HANDLED;
811 switch (musb->xceiv.state) {
812 #ifdef CONFIG_USB_MUSB_OTG
813 case OTG_STATE_A_PERIPHERAL:
815 * We cannot stop HNP here, devctl BDEVICE might be
820 case OTG_STATE_B_PERIPHERAL:
821 musb_g_suspend(musb);
822 musb->is_active = is_otg_enabled(musb)
823 && musb->xceiv.gadget->b_hnp_enable;
824 if (musb->is_active) {
825 #ifdef CONFIG_USB_MUSB_OTG
826 musb->xceiv.state = OTG_STATE_B_WAIT_ACON;
827 DBG(1, "HNP: Setting timer for b_ase0_brst\n");
828 musb_otg_timer.data = (unsigned long)musb;
829 mod_timer(&musb_otg_timer, jiffies
830 + msecs_to_jiffies(TB_ASE0_BRST));
834 case OTG_STATE_A_WAIT_BCON:
835 if (musb->a_wait_bcon != 0)
836 musb_platform_try_idle(musb, jiffies
837 + msecs_to_jiffies(musb->a_wait_bcon));
839 case OTG_STATE_A_HOST:
840 musb->xceiv.state = OTG_STATE_A_SUSPEND;
841 musb->is_active = is_otg_enabled(musb)
842 && musb->xceiv.host->b_hnp_enable;
844 case OTG_STATE_B_HOST:
845 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
846 DBG(1, "REVISIT: SUSPEND as B_HOST\n");
849 /* "should not happen" */
853 schedule_work(&musb->irq_work);
860 /*-------------------------------------------------------------------------*/
863 * Program the HDRC to start (enable interrupts, dma, etc.).
865 void musb_start(struct musb *musb)
867 void __iomem *regs = musb->mregs;
868 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
870 DBG(2, "<== devctl %02x\n", devctl);
872 /* Set INT enable registers, enable interrupts */
873 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
874 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
875 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
877 musb_writeb(regs, MUSB_TESTMODE, 0);
879 /* put into basic highspeed mode and start session */
880 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
881 | MUSB_POWER_SOFTCONN
883 /* ENSUSPEND wedges tusb */
884 /* | MUSB_POWER_ENSUSPEND */
888 devctl = musb_readb(regs, MUSB_DEVCTL);
889 devctl &= ~MUSB_DEVCTL_SESSION;
891 if (is_otg_enabled(musb)) {
892 /* session started after:
893 * (a) ID-grounded irq, host mode;
894 * (b) vbus present/connect IRQ, peripheral mode;
895 * (c) peripheral initiates, using SRP
897 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
900 devctl |= MUSB_DEVCTL_SESSION;
902 } else if (is_host_enabled(musb)) {
903 /* assume ID pin is hard-wired to ground */
904 devctl |= MUSB_DEVCTL_SESSION;
906 } else /* peripheral is enabled */ {
907 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
910 musb_platform_enable(musb);
911 musb_writeb(regs, MUSB_DEVCTL, devctl);
915 static void musb_generic_disable(struct musb *musb)
917 void __iomem *mbase = musb->mregs;
920 /* disable interrupts */
921 musb_writeb(mbase, MUSB_INTRUSBE, 0);
922 musb_writew(mbase, MUSB_INTRTXE, 0);
923 musb_writew(mbase, MUSB_INTRRXE, 0);
926 musb_writeb(mbase, MUSB_DEVCTL, 0);
928 /* flush pending interrupts */
929 temp = musb_readb(mbase, MUSB_INTRUSB);
930 temp = musb_readw(mbase, MUSB_INTRTX);
931 temp = musb_readw(mbase, MUSB_INTRRX);
936 * Make the HDRC stop (disable interrupts, etc.);
937 * reversible by musb_start
938 * called on gadget driver unregister
939 * with controller locked, irqs blocked
940 * acts as a NOP unless some role activated the hardware
942 void musb_stop(struct musb *musb)
944 /* stop IRQs, timers, ... */
945 musb_platform_disable(musb);
946 musb_generic_disable(musb);
947 DBG(3, "HDRC disabled\n");
950 * - mark host and/or peripheral drivers unusable/inactive
951 * - disable DMA (and enable it in HdrcStart)
952 * - make sure we can musb_start() after musb_stop(); with
953 * OTG mode, gadget driver module rmmod/modprobe cycles that
956 musb_platform_try_idle(musb, 0);
959 static void musb_shutdown(struct platform_device *pdev)
961 struct musb *musb = dev_to_musb(&pdev->dev);
964 spin_lock_irqsave(&musb->lock, flags);
965 musb_platform_disable(musb);
966 musb_generic_disable(musb);
968 clk_put(musb->clock);
971 spin_unlock_irqrestore(&musb->lock, flags);
973 /* FIXME power down */
977 /*-------------------------------------------------------------------------*/
980 * The silicon either has hard-wired endpoint configurations, or else
981 * "dynamic fifo" sizing. The driver has support for both, though at this
982 * writing only the dynamic sizing is very well tested. We use normal
983 * idioms to so both modes are compile-tested, but dead code elimination
984 * leaves only the relevant one in the object file.
986 * We don't currently use dynamic fifo setup capability to do anything
987 * more than selecting one of a bunch of predefined configurations.
989 #ifdef MUSB_C_DYNFIFO_DEF
990 #define can_dynfifo() 1
992 #define can_dynfifo() 0
995 #if defined(CONFIG_USB_TUSB6010) || \
996 defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
997 static ushort __initdata fifo_mode = 4;
999 static ushort __initdata fifo_mode = 2;
1002 /* "modprobe ... fifo_mode=1" etc */
1003 module_param(fifo_mode, ushort, 0);
1004 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1007 #define DYN_FIFO_SIZE (1<<(MUSB_C_RAM_BITS+2))
1009 enum fifo_style { FIFO_RXTX, FIFO_TX, FIFO_RX } __attribute__ ((packed));
1010 enum buf_mode { BUF_SINGLE, BUF_DOUBLE } __attribute__ ((packed));
1014 enum fifo_style style;
1020 * tables defining fifo_mode values. define more if you like.
1021 * for host side, make sure both halves of ep1 are set up.
1024 /* mode 0 - fits in 2KB */
1025 static struct fifo_cfg __initdata mode_0_cfg[] = {
1026 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1027 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1028 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1029 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1030 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1033 /* mode 1 - fits in 4KB */
1034 static struct fifo_cfg __initdata mode_1_cfg[] = {
1035 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1036 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1037 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1038 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1039 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1042 /* mode 2 - fits in 4KB */
1043 static struct fifo_cfg __initdata mode_2_cfg[] = {
1044 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1045 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1046 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1047 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1048 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1049 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1052 /* mode 3 - fits in 4KB */
1053 static struct fifo_cfg __initdata mode_3_cfg[] = {
1054 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1055 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1056 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1057 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1058 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1059 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1062 /* mode 4 - fits in 16KB */
1063 static struct fifo_cfg __initdata mode_4_cfg[] = {
1064 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1065 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1066 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1067 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1068 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1069 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1070 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1071 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1072 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1073 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1074 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1075 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1076 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1077 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1078 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1079 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1080 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1081 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1082 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 512, },
1083 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 512, },
1084 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 512, },
1085 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 512, },
1086 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 512, },
1087 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 512, },
1088 { .hw_ep_num = 13, .style = FIFO_TX, .maxpacket = 512, },
1089 { .hw_ep_num = 13, .style = FIFO_RX, .maxpacket = 512, },
1090 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1091 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1096 * configure a fifo; for non-shared endpoints, this may be called
1097 * once for a tx fifo and once for an rx fifo.
1099 * returns negative errno or offset for next fifo.
1102 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1103 const struct fifo_cfg *cfg, u16 offset)
1105 void __iomem *mbase = musb->mregs;
1107 u16 maxpacket = cfg->maxpacket;
1108 u16 c_off = offset >> 3;
1111 /* expect hw_ep has already been zero-initialized */
1113 size = ffs(max(maxpacket, (u16) 8)) - 1;
1114 maxpacket = 1 << size;
1117 if (cfg->mode == BUF_DOUBLE) {
1118 if ((offset + (maxpacket << 1)) > DYN_FIFO_SIZE)
1120 c_size |= MUSB_FIFOSZ_DPB;
1122 if ((offset + maxpacket) > DYN_FIFO_SIZE)
1126 /* configure the FIFO */
1127 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1129 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1130 /* EP0 reserved endpoint for control, bidirectional;
1131 * EP1 reserved for bulk, two unidirection halves.
1133 if (hw_ep->epnum == 1)
1134 musb->bulk_ep = hw_ep;
1135 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1137 switch (cfg->style) {
1139 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
1140 musb_writew(mbase, MUSB_TXFIFOADD, c_off);
1141 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1142 hw_ep->max_packet_sz_tx = maxpacket;
1145 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
1146 musb_writew(mbase, MUSB_RXFIFOADD, c_off);
1147 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1148 hw_ep->max_packet_sz_rx = maxpacket;
1151 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
1152 musb_writew(mbase, MUSB_TXFIFOADD, c_off);
1153 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1154 hw_ep->max_packet_sz_rx = maxpacket;
1156 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
1157 musb_writew(mbase, MUSB_RXFIFOADD, c_off);
1158 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1159 hw_ep->max_packet_sz_tx = maxpacket;
1161 hw_ep->is_shared_fifo = true;
1165 /* NOTE rx and tx endpoint irqs aren't managed separately,
1166 * which happens to be ok
1168 musb->epmask |= (1 << hw_ep->epnum);
1170 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1173 static struct fifo_cfg __initdata ep0_cfg = {
1174 .style = FIFO_RXTX, .maxpacket = 64,
1177 static int __init ep_config_from_table(struct musb *musb)
1179 const struct fifo_cfg *cfg;
1182 struct musb_hw_ep *hw_ep = musb->endpoints;
1184 switch (fifo_mode) {
1190 n = ARRAY_SIZE(mode_0_cfg);
1194 n = ARRAY_SIZE(mode_1_cfg);
1198 n = ARRAY_SIZE(mode_2_cfg);
1202 n = ARRAY_SIZE(mode_3_cfg);
1206 n = ARRAY_SIZE(mode_4_cfg);
1210 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1211 musb_driver_name, fifo_mode);
1214 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1215 /* assert(offset > 0) */
1217 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1218 * be better than static MUSB_C_NUM_EPS and DYN_FIFO_SIZE...
1221 for (i = 0; i < n; i++) {
1222 u8 epn = cfg->hw_ep_num;
1224 if (epn >= MUSB_C_NUM_EPS) {
1225 pr_debug("%s: invalid ep %d\n",
1226 musb_driver_name, epn);
1229 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1231 pr_debug("%s: mem overrun, ep %d\n",
1232 musb_driver_name, epn);
1236 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1239 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1241 n + 1, MUSB_C_NUM_EPS * 2 - 1,
1242 offset, DYN_FIFO_SIZE);
1244 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1245 if (!musb->bulk_ep) {
1246 pr_debug("%s: missing bulk\n", musb_driver_name);
1256 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1257 * @param musb the controller
1259 static int __init ep_config_from_hw(struct musb *musb)
1262 struct musb_hw_ep *hw_ep;
1263 void *mbase = musb->mregs;
1265 DBG(2, "<== static silicon ep config\n");
1267 /* FIXME pick up ep0 maxpacket size */
1269 for (epnum = 1; epnum < MUSB_C_NUM_EPS; epnum++) {
1270 musb_ep_select(mbase, epnum);
1271 hw_ep = musb->endpoints + epnum;
1273 /* read from core using indexed model */
1274 reg = musb_readb(hw_ep->regs, 0x10 + MUSB_FIFOSIZE);
1276 /* 0's returned when no more endpoints */
1279 musb->nr_endpoints++;
1280 musb->epmask |= (1 << epnum);
1282 hw_ep->max_packet_sz_tx = 1 << (reg & 0x0f);
1284 /* shared TX/RX FIFO? */
1285 if ((reg & 0xf0) == 0xf0) {
1286 hw_ep->max_packet_sz_rx = hw_ep->max_packet_sz_tx;
1287 hw_ep->is_shared_fifo = true;
1290 hw_ep->max_packet_sz_rx = 1 << ((reg & 0xf0) >> 4);
1291 hw_ep->is_shared_fifo = false;
1294 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1296 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1297 /* pick an RX/TX endpoint for bulk */
1298 if (hw_ep->max_packet_sz_tx < 512
1299 || hw_ep->max_packet_sz_rx < 512)
1302 /* REVISIT: this algorithm is lazy, we should at least
1303 * try to pick a double buffered endpoint.
1307 musb->bulk_ep = hw_ep;
1311 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1312 if (!musb->bulk_ep) {
1313 pr_debug("%s: missing bulk\n", musb_driver_name);
1321 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1323 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1324 * configure endpoints, or take their config from silicon
1326 static int __init musb_core_init(u16 musb_type, struct musb *musb)
1333 u16 hwvers, rev_major, rev_minor;
1334 char aInfo[78], aRevision[32], aDate[12];
1335 void __iomem *mbase = musb->mregs;
1339 /* log core options (read using indexed model) */
1340 musb_ep_select(mbase, 0);
1341 reg = musb_readb(mbase, 0x10 + MUSB_CONFIGDATA);
1343 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1344 if (reg & MUSB_CONFIGDATA_DYNFIFO)
1345 strcat(aInfo, ", dyn FIFOs");
1346 if (reg & MUSB_CONFIGDATA_MPRXE) {
1347 strcat(aInfo, ", bulk combine");
1349 musb->bulk_combine = true;
1351 strcat(aInfo, " (X)"); /* no driver support */
1354 if (reg & MUSB_CONFIGDATA_MPTXE) {
1355 strcat(aInfo, ", bulk split");
1357 musb->bulk_split = true;
1359 strcat(aInfo, " (X)"); /* no driver support */
1362 if (reg & MUSB_CONFIGDATA_HBRXE) {
1363 strcat(aInfo, ", HB-ISO Rx");
1364 strcat(aInfo, " (X)"); /* no driver support */
1366 if (reg & MUSB_CONFIGDATA_HBTXE) {
1367 strcat(aInfo, ", HB-ISO Tx");
1368 strcat(aInfo, " (X)"); /* no driver support */
1370 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1371 strcat(aInfo, ", SoftConn");
1373 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1374 musb_driver_name, reg, aInfo);
1377 data = musb_readl(mbase, 0x404);
1378 sprintf(aDate, "%04d-%02x-%02x", (data & 0xffff),
1379 (data >> 16) & 0xff, (data >> 24) & 0xff);
1380 /* FIXME ID2 and ID3 are unused */
1381 data = musb_readl(mbase, 0x408);
1382 printk("ID2=%lx\n", (long unsigned)data);
1383 data = musb_readl(mbase, 0x40c);
1384 printk("ID3=%lx\n", (long unsigned)data);
1385 reg = musb_readb(mbase, 0x400);
1386 musb_type = ('M' == reg) ? MUSB_CONTROLLER_MHDRC : MUSB_CONTROLLER_HDRC;
1390 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1391 musb->is_multipoint = 1;
1394 musb->is_multipoint = 0;
1396 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1397 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1399 "%s: kernel must blacklist external hubs\n",
1405 /* log release info */
1406 hwvers = musb_readw(mbase, MUSB_HWVERS);
1407 rev_major = (hwvers >> 10) & 0x1f;
1408 rev_minor = hwvers & 0x3ff;
1409 snprintf(aRevision, 32, "%d.%d%s", rev_major,
1410 rev_minor, (hwvers & 0x8000) ? "RC" : "");
1411 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1412 musb_driver_name, type, aRevision, aDate);
1415 musb->endpoints[0].max_packet_sz_tx = MUSB_EP0_FIFOSIZE;
1416 musb->endpoints[0].max_packet_sz_rx = MUSB_EP0_FIFOSIZE;
1418 /* discover endpoint configuration */
1419 musb->nr_endpoints = 1;
1422 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1424 status = ep_config_from_table(musb);
1426 ERR("reconfigure software for Dynamic FIFOs\n");
1431 status = ep_config_from_hw(musb);
1433 ERR("reconfigure software for static FIFOs\n");
1441 /* finish init, and print endpoint config */
1442 for (i = 0; i < musb->nr_endpoints; i++) {
1443 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1445 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1446 #ifdef CONFIG_USB_TUSB6010
1447 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1448 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1449 hw_ep->fifo_sync_va =
1450 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1453 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1455 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1458 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1459 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1460 hw_ep->target_regs = MUSB_BUSCTL_OFFSET(i, 0) + mbase;
1461 hw_ep->rx_reinit = 1;
1462 hw_ep->tx_reinit = 1;
1465 if (hw_ep->max_packet_sz_tx) {
1467 "%s: hw_ep %d%s, %smax %d\n",
1468 musb_driver_name, i,
1469 hw_ep->is_shared_fifo ? "shared" : "tx",
1470 hw_ep->tx_double_buffered
1471 ? "doublebuffer, " : "",
1472 hw_ep->max_packet_sz_tx);
1474 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1476 "%s: hw_ep %d%s, %smax %d\n",
1477 musb_driver_name, i,
1479 hw_ep->rx_double_buffered
1480 ? "doublebuffer, " : "",
1481 hw_ep->max_packet_sz_rx);
1483 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1484 DBG(1, "hw_ep %d not configured\n", i);
1490 /*-------------------------------------------------------------------------*/
1492 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
1494 static irqreturn_t generic_interrupt(int irq, void *__hci)
1496 unsigned long flags;
1497 irqreturn_t retval = IRQ_NONE;
1498 struct musb *musb = __hci;
1500 spin_lock_irqsave(&musb->lock, flags);
1502 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1503 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1504 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1506 if (musb->int_usb || musb->int_tx || musb->int_rx)
1507 retval = musb_interrupt(musb);
1509 spin_unlock_irqrestore(&musb->lock, flags);
1511 /* REVISIT we sometimes get spurious IRQs on g_ep0
1514 if (retval != IRQ_HANDLED)
1515 DBG(5, "spurious?\n");
1521 #define generic_interrupt NULL
1525 * handle all the irqs defined by the HDRC core. for now we expect: other
1526 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1527 * will be assigned, and the irq will already have been acked.
1529 * called in irq context with spinlock held, irqs blocked
1531 irqreturn_t musb_interrupt(struct musb *musb)
1533 irqreturn_t retval = IRQ_NONE;
1538 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1539 power = musb_readb(musb->mregs, MUSB_POWER);
1541 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
1542 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1543 musb->int_usb, musb->int_tx, musb->int_rx);
1545 /* the core can interrupt us for multiple reasons; docs have
1546 * a generic interrupt flowchart to follow
1548 if (musb->int_usb & STAGE0_MASK)
1549 retval |= musb_stage0_irq(musb, musb->int_usb,
1552 /* "stage 1" is handling endpoint irqs */
1554 /* handle endpoint 0 first */
1555 if (musb->int_tx & 1) {
1556 if (devctl & MUSB_DEVCTL_HM)
1557 retval |= musb_h_ep0_irq(musb);
1559 retval |= musb_g_ep0_irq(musb);
1562 /* RX on endpoints 1-15 */
1563 reg = musb->int_rx >> 1;
1567 /* musb_ep_select(musb->mregs, ep_num); */
1568 /* REVISIT just retval = ep->rx_irq(...) */
1569 retval = IRQ_HANDLED;
1570 if (devctl & MUSB_DEVCTL_HM) {
1571 if (is_host_capable())
1572 musb_host_rx(musb, ep_num);
1574 if (is_peripheral_capable())
1575 musb_g_rx(musb, ep_num);
1583 /* TX on endpoints 1-15 */
1584 reg = musb->int_tx >> 1;
1588 /* musb_ep_select(musb->mregs, ep_num); */
1589 /* REVISIT just retval |= ep->tx_irq(...) */
1590 retval = IRQ_HANDLED;
1591 if (devctl & MUSB_DEVCTL_HM) {
1592 if (is_host_capable())
1593 musb_host_tx(musb, ep_num);
1595 if (is_peripheral_capable())
1596 musb_g_tx(musb, ep_num);
1603 /* finish handling "global" interrupts after handling fifos */
1605 retval |= musb_stage2_irq(musb,
1606 musb->int_usb, devctl, power);
1612 #ifndef CONFIG_MUSB_PIO_ONLY
1613 static int __initdata use_dma = 1;
1615 /* "modprobe ... use_dma=0" etc */
1616 module_param(use_dma, bool, 0);
1617 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1619 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1621 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1623 /* called with controller lock already held */
1626 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1627 if (!is_cppi_enabled()) {
1629 if (devctl & MUSB_DEVCTL_HM)
1630 musb_h_ep0_irq(musb);
1632 musb_g_ep0_irq(musb);
1636 /* endpoints 1..15 */
1638 if (devctl & MUSB_DEVCTL_HM) {
1639 if (is_host_capable())
1640 musb_host_tx(musb, epnum);
1642 if (is_peripheral_capable())
1643 musb_g_tx(musb, epnum);
1647 if (devctl & MUSB_DEVCTL_HM) {
1648 if (is_host_capable())
1649 musb_host_rx(musb, epnum);
1651 if (is_peripheral_capable())
1652 musb_g_rx(musb, epnum);
1662 /*-------------------------------------------------------------------------*/
1667 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1669 struct musb *musb = dev_to_musb(dev);
1670 unsigned long flags;
1673 spin_lock_irqsave(&musb->lock, flags);
1674 ret = sprintf(buf, "%s\n", otg_state_string(musb));
1675 spin_unlock_irqrestore(&musb->lock, flags);
1681 musb_mode_store(struct device *dev, struct device_attribute *attr,
1682 const char *buf, size_t n)
1684 struct musb *musb = dev_to_musb(dev);
1685 unsigned long flags;
1687 spin_lock_irqsave(&musb->lock, flags);
1688 if (!strncmp(buf, "host", 4))
1689 musb_platform_set_mode(musb, MUSB_HOST);
1690 if (!strncmp(buf, "peripheral", 10))
1691 musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1692 if (!strncmp(buf, "otg", 3))
1693 musb_platform_set_mode(musb, MUSB_OTG);
1694 spin_unlock_irqrestore(&musb->lock, flags);
1698 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1701 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1702 const char *buf, size_t n)
1704 struct musb *musb = dev_to_musb(dev);
1705 unsigned long flags;
1708 if (sscanf(buf, "%lu", &val) < 1) {
1709 printk(KERN_ERR "Invalid VBUS timeout ms value\n");
1713 spin_lock_irqsave(&musb->lock, flags);
1714 musb->a_wait_bcon = val;
1715 if (musb->xceiv.state == OTG_STATE_A_WAIT_BCON)
1716 musb->is_active = 0;
1717 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1718 spin_unlock_irqrestore(&musb->lock, flags);
1724 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1726 struct musb *musb = dev_to_musb(dev);
1727 unsigned long flags;
1731 spin_lock_irqsave(&musb->lock, flags);
1732 val = musb->a_wait_bcon;
1733 vbus = musb_platform_get_vbus_status(musb);
1734 spin_unlock_irqrestore(&musb->lock, flags);
1736 return sprintf(buf, "Vbus %s, timeout %lu\n",
1737 vbus ? "on" : "off", val);
1739 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1741 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1743 /* Gadget drivers can't know that a host is connected so they might want
1744 * to start SRP, but users can. This allows userspace to trigger SRP.
1747 musb_srp_store(struct device *dev, struct device_attribute *attr,
1748 const char *buf, size_t n)
1750 struct musb *musb = dev_to_musb(dev);
1753 if (sscanf(buf, "%hu", &srp) != 1
1755 printk(KERN_ERR "SRP: Value must be 1\n");
1760 musb_g_wakeup(musb);
1764 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1766 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
1770 /* Only used to provide driver mode change events */
1771 static void musb_irq_work(struct work_struct *data)
1773 struct musb *musb = container_of(data, struct musb, irq_work);
1774 static int old_state;
1776 if (musb->xceiv.state != old_state) {
1777 old_state = musb->xceiv.state;
1778 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1782 /* --------------------------------------------------------------------------
1786 static struct musb *__init
1787 allocate_instance(struct device *dev, void __iomem *mbase)
1790 struct musb_hw_ep *ep;
1792 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1793 struct usb_hcd *hcd;
1795 hcd = usb_create_hcd(&musb_hc_driver, dev, dev->bus_id);
1798 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1800 musb = hcd_to_musb(hcd);
1801 INIT_LIST_HEAD(&musb->control);
1802 INIT_LIST_HEAD(&musb->in_bulk);
1803 INIT_LIST_HEAD(&musb->out_bulk);
1805 hcd->uses_new_polling = 1;
1807 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1809 musb = kzalloc(sizeof *musb, GFP_KERNEL);
1812 dev_set_drvdata(dev, musb);
1816 musb->mregs = mbase;
1817 musb->ctrl_base = mbase;
1818 musb->nIrq = -ENODEV;
1819 for (epnum = 0, ep = musb->endpoints;
1820 epnum < MUSB_C_NUM_EPS;
1827 #ifdef CONFIG_USB_MUSB_OTG
1828 otg_set_transceiver(&musb->xceiv);
1830 musb->controller = dev;
1834 static void musb_free(struct musb *musb)
1836 /* this has multiple entry modes. it handles fault cleanup after
1837 * probe(), where things may be partially set up, as well as rmmod
1838 * cleanup after everything's been de-activated.
1842 device_remove_file(musb->controller, &dev_attr_mode);
1843 device_remove_file(musb->controller, &dev_attr_vbus);
1844 #ifdef CONFIG_USB_MUSB_OTG
1845 device_remove_file(musb->controller, &dev_attr_srp);
1849 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1850 musb_gadget_cleanup(musb);
1853 if (musb->nIrq >= 0) {
1854 disable_irq_wake(musb->nIrq);
1855 free_irq(musb->nIrq, musb);
1857 if (is_dma_capable() && musb->dma_controller) {
1858 struct dma_controller *c = musb->dma_controller;
1861 dma_controller_destroy(c);
1864 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1865 musb_platform_exit(musb);
1866 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1869 clk_disable(musb->clock);
1870 clk_put(musb->clock);
1873 #ifdef CONFIG_USB_MUSB_OTG
1874 put_device(musb->xceiv.dev);
1877 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1878 usb_put_hcd(musb_to_hcd(musb));
1885 * Perform generic per-controller initialization.
1887 * @pDevice: the controller (already clocked, etc)
1889 * @mregs: virtual address of controller registers,
1890 * not yet corrected for platform-specific offsets
1893 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1897 struct musb_hdrc_platform_data *plat = dev->platform_data;
1899 /* The driver might handle more features than the board; OK.
1900 * Fail when the board needs a feature that's not enabled.
1903 dev_dbg(dev, "no platform_data?\n");
1906 switch (plat->mode) {
1908 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1913 case MUSB_PERIPHERAL:
1914 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1920 #ifdef CONFIG_USB_MUSB_OTG
1926 dev_err(dev, "incompatible Kconfig role setting\n");
1931 musb = allocate_instance(dev, ctrl);
1935 spin_lock_init(&musb->lock);
1936 musb->board_mode = plat->mode;
1937 musb->board_set_power = plat->set_power;
1938 musb->set_clock = plat->set_clock;
1939 musb->min_power = plat->min_power;
1941 /* Clock usage is chip-specific ... functional clock (DaVinci,
1942 * OMAP2430), or PHY ref (some TUSB6010 boards). All this core
1943 * code does is make sure a clock handle is available; platform
1944 * code manages it during start/stop and suspend/resume.
1947 musb->clock = clk_get(dev, plat->clock);
1948 if (IS_ERR(musb->clock)) {
1949 status = PTR_ERR(musb->clock);
1955 /* assume vbus is off */
1957 /* platform adjusts musb->mregs and musb->isr if needed,
1958 * and activates clocks
1960 musb->isr = generic_interrupt;
1961 status = musb_platform_init(musb);
1970 #ifndef CONFIG_MUSB_PIO_ONLY
1971 if (use_dma && dev->dma_mask) {
1972 struct dma_controller *c;
1974 c = dma_controller_create(musb, musb->mregs);
1975 musb->dma_controller = c;
1980 /* ideally this would be abstracted in platform setup */
1981 if (!is_dma_capable() || !musb->dma_controller)
1982 dev->dma_mask = NULL;
1984 /* be sure interrupts are disabled before connecting ISR */
1985 musb_platform_disable(musb);
1986 musb_generic_disable(musb);
1988 /* setup musb parts of the core (especially endpoints) */
1989 status = musb_core_init(plat->multipoint
1990 ? MUSB_CONTROLLER_MHDRC
1991 : MUSB_CONTROLLER_HDRC, musb);
1995 /* Init IRQ workqueue before request_irq */
1996 INIT_WORK(&musb->irq_work, musb_irq_work);
1998 /* attach to the IRQ */
1999 if (request_irq(nIrq, musb->isr, 0, dev->bus_id, musb)) {
2000 dev_err(dev, "request_irq %d failed!\n", nIrq);
2005 /* FIXME this handles wakeup irqs wrong */
2006 if (enable_irq_wake(nIrq) == 0)
2007 device_init_wakeup(dev, 1);
2009 pr_info("%s: USB %s mode controller at %p using %s, IRQ %d\n",
2012 switch (musb->board_mode) {
2013 case MUSB_HOST: s = "Host"; break;
2014 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2015 default: s = "OTG"; break;
2018 (is_dma_capable() && musb->dma_controller)
2022 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2023 /* host side needs more setup, except for no-host modes */
2024 if (musb->board_mode != MUSB_PERIPHERAL) {
2025 struct usb_hcd *hcd = musb_to_hcd(musb);
2027 if (musb->board_mode == MUSB_OTG)
2028 hcd->self.otg_port = 1;
2029 musb->xceiv.host = &hcd->self;
2030 hcd->power_budget = 2 * (plat->power ? : 250);
2032 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
2034 /* For the host-only role, we can activate right away.
2035 * (We expect the ID pin to be forcibly grounded!!)
2036 * Otherwise, wait till the gadget driver hooks up.
2038 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2039 MUSB_HST_MODE(musb);
2040 musb->xceiv.default_a = 1;
2041 musb->xceiv.state = OTG_STATE_A_IDLE;
2043 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2045 DBG(1, "%s mode, status %d, devctl %02x %c\n",
2047 musb_readb(musb->mregs, MUSB_DEVCTL),
2048 (musb_readb(musb->mregs, MUSB_DEVCTL)
2049 & MUSB_DEVCTL_BDEVICE
2052 } else /* peripheral is enabled */ {
2053 MUSB_DEV_MODE(musb);
2054 musb->xceiv.default_a = 0;
2055 musb->xceiv.state = OTG_STATE_B_IDLE;
2057 status = musb_gadget_setup(musb);
2059 DBG(1, "%s mode, status %d, dev%02x\n",
2060 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2062 musb_readb(musb->mregs, MUSB_DEVCTL));
2067 musb_debug_create("driver/musb_hdrc", musb);
2071 clk_put(musb->clock);
2072 device_init_wakeup(dev, 0);
2078 status = device_create_file(dev, &dev_attr_mode);
2079 status = device_create_file(dev, &dev_attr_vbus);
2080 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2081 status = device_create_file(dev, &dev_attr_srp);
2082 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
2089 musb_platform_exit(musb);
2093 /*-------------------------------------------------------------------------*/
2095 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2096 * bridge to a platform device; this driver then suffices.
2099 #ifndef CONFIG_MUSB_PIO_ONLY
2100 static u64 *orig_dma_mask;
2103 static int __init musb_probe(struct platform_device *pdev)
2105 struct device *dev = &pdev->dev;
2106 int irq = platform_get_irq(pdev, 0);
2107 struct resource *iomem;
2110 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2111 if (!iomem || irq == 0)
2114 base = ioremap(iomem->start, iomem->end - iomem->start + 1);
2116 dev_err(dev, "ioremap failed\n");
2120 #ifndef CONFIG_MUSB_PIO_ONLY
2121 /* clobbered by use_dma=n */
2122 orig_dma_mask = dev->dma_mask;
2124 return musb_init_controller(dev, irq, base);
2127 static int __devexit musb_remove(struct platform_device *pdev)
2129 struct musb *musb = dev_to_musb(&pdev->dev);
2130 void __iomem *ctrl_base = musb->ctrl_base;
2132 /* this gets called on rmmod.
2133 * - Host mode: host may still be active
2134 * - Peripheral mode: peripheral is deactivated (or never-activated)
2135 * - OTG mode: both roles are deactivated (or never-activated)
2137 musb_shutdown(pdev);
2138 musb_debug_delete("driver/musb_hdrc", musb);
2139 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2140 if (musb->board_mode == MUSB_HOST)
2141 usb_remove_hcd(musb_to_hcd(musb));
2145 device_init_wakeup(&pdev->dev, 0);
2146 #ifndef CONFIG_MUSB_PIO_ONLY
2147 pdev->dev.dma_mask = orig_dma_mask;
2154 static int musb_suspend(struct platform_device *pdev, pm_message_t message)
2156 unsigned long flags;
2157 struct musb *musb = dev_to_musb(&pdev->dev);
2162 spin_lock_irqsave(&musb->lock, flags);
2164 if (is_peripheral_active(musb)) {
2165 /* FIXME force disconnect unless we know USB will wake
2166 * the system up quickly enough to respond ...
2168 } else if (is_host_active(musb)) {
2169 /* we know all the children are suspended; sometimes
2170 * they will even be wakeup-enabled.
2174 if (musb->set_clock)
2175 musb->set_clock(musb->clock, 0);
2177 clk_disable(musb->clock);
2178 spin_unlock_irqrestore(&musb->lock, flags);
2182 static int musb_resume(struct platform_device *pdev)
2184 unsigned long flags;
2185 struct musb *musb = dev_to_musb(&pdev->dev);
2190 spin_lock_irqsave(&musb->lock, flags);
2192 if (musb->set_clock)
2193 musb->set_clock(musb->clock, 1);
2195 clk_enable(musb->clock);
2197 /* for static cmos like DaVinci, register values were preserved
2198 * unless for some reason the whole soc powered down and we're
2199 * not treating that as a whole-system restart (e.g. swsusp)
2201 spin_unlock_irqrestore(&musb->lock, flags);
2206 #define musb_suspend NULL
2207 #define musb_resume NULL
2210 static struct platform_driver musb_driver = {
2212 .name = (char *)musb_driver_name,
2213 .bus = &platform_bus_type,
2214 .owner = THIS_MODULE,
2216 .remove = __devexit_p(musb_remove),
2217 .shutdown = musb_shutdown,
2218 .suspend = musb_suspend,
2219 .resume = musb_resume,
2222 /*-------------------------------------------------------------------------*/
2224 static int __init musb_init(void)
2226 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2231 pr_info("%s: version " MUSB_VERSION ", "
2232 #ifdef CONFIG_MUSB_PIO_ONLY
2234 #elif defined(CONFIG_USB_TI_CPPI_DMA)
2236 #elif defined(CONFIG_USB_INVENTRA_DMA)
2238 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
2244 #ifdef CONFIG_USB_MUSB_OTG
2245 "otg (peripheral+host)"
2246 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
2248 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2252 musb_driver_name, debug);
2253 return platform_driver_probe(&musb_driver, musb_probe);
2256 /* make us init after usbcore and before usb
2257 * gadget and host-side drivers start to register
2259 subsys_initcall(musb_init);
2261 static void __exit musb_cleanup(void)
2263 platform_driver_unregister(&musb_driver);
2265 module_exit(musb_cleanup);