2 * MUSB OTG driver core code
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - <asm/arch/hdrc_cnf.h> for SOC or family details
86 * - platform_device for addressing, irq, and platform_data
87 * - platform_data is mostly for board-specific informarion
89 * Most of the conditional compilation will (someday) vanish.
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/platform_device.h>
104 #include <asm/arch/hardware.h>
105 #include <asm/arch/memory.h>
106 #include <asm/mach-types.h>
109 #include "musb_core.h"
112 #ifdef CONFIG_ARCH_DAVINCI
119 unsigned debug = MUSB_DEBUG;
120 module_param(debug, uint, 0);
121 MODULE_PARM_DESC(debug, "initial debug message level");
123 #define MUSB_VERSION_SUFFIX "/dbg"
126 const char *otg_state_string(struct musb *musb)
130 snprintf(buf, sizeof buf, "otg-%d", musb->xceiv.state);
135 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
136 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
138 #define MUSB_VERSION_BASE "2.2a/db-0.5.2"
140 #ifndef MUSB_VERSION_SUFFIX
141 #define MUSB_VERSION_SUFFIX ""
143 #define MUSB_VERSION MUSB_VERSION_BASE MUSB_VERSION_SUFFIX
145 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
147 const char musb_driver_name[] = "musb_hdrc";
149 MODULE_DESCRIPTION(DRIVER_INFO);
150 MODULE_AUTHOR(DRIVER_AUTHOR);
151 MODULE_LICENSE("GPL");
154 /*-------------------------------------------------------------------------*/
156 static inline struct musb *dev_to_musb(struct device *dev)
158 #ifdef CONFIG_USB_MUSB_HDRC_HCD
159 /* usbcore insists dev->driver_data is a "struct hcd *" */
160 return hcd_to_musb(dev_get_drvdata(dev));
162 return dev_get_drvdata(dev);
166 /*-------------------------------------------------------------------------*/
168 #ifndef CONFIG_USB_TUSB6010
170 * Load an endpoint's FIFO
172 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
174 void __iomem *fifo = hw_ep->fifo;
178 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
179 'T', hw_ep->epnum, fifo, len, src);
181 /* we can't assume unaligned reads work */
182 if (likely((0x01 & (unsigned long) src) == 0)) {
185 /* best case is 32bit-aligned source address */
186 if ((0x02 & (unsigned long) src) == 0) {
188 writesl(fifo, src + index, len >> 2);
189 index += len & ~0x03;
192 musb_writew(fifo, 0, *(u16*)&src[index]);
197 writesw(fifo, src + index, len >> 1);
198 index += len & ~0x01;
202 musb_writeb(fifo, 0, src[index]);
205 writesb(fifo, src, len);
210 * Unload an endpoint's FIFO
212 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
214 void __iomem *fifo = hw_ep->fifo;
216 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
217 'R', hw_ep->epnum, fifo, len, dst);
219 /* we can't assume unaligned writes work */
220 if (likely((0x01 & (unsigned long) dst) == 0)) {
223 /* best case is 32bit-aligned destination address */
224 if ((0x02 & (unsigned long) dst) == 0) {
226 readsl(fifo, dst, len >> 2);
230 *(u16*)&dst[index] = musb_readw(fifo, 0);
235 readsw(fifo, dst, len >> 1);
240 dst[index] = musb_readb(fifo, 0);
243 readsb(fifo, dst, len);
247 #endif /* normal PIO */
250 /*-------------------------------------------------------------------------*/
252 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
253 static const u8 musb_test_packet[53] = {
254 /* implicit SYNC then DATA0 to start */
257 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
259 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
261 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
262 /* JJJJJJJKKKKKKK x8 */
263 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
265 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
266 /* JKKKKKKK x10, JK */
267 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
269 /* implicit CRC16 then EOP to end */
272 void musb_load_testpacket(struct musb *musb)
274 void __iomem *regs = musb->endpoints[0].regs;
276 musb_ep_select(musb->mregs, 0);
277 musb_write_fifo(musb->control_ep,
278 sizeof(musb_test_packet), musb_test_packet);
279 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
282 /*-------------------------------------------------------------------------*/
284 #ifdef CONFIG_USB_MUSB_OTG
287 * See also USB_OTG_1-3.pdf 6.6.5 Timers
288 * REVISIT: Are the other timers done in the hardware?
290 #define TB_ASE0_BRST 100 /* Min 3.125 ms */
293 * Handles OTG hnp timeouts, such as b_ase0_brst
295 void musb_otg_timer_func(unsigned long data)
297 struct musb *musb = (struct musb *)data;
300 spin_lock_irqsave(&musb->lock, flags);
301 if (musb->xceiv.state == OTG_STATE_B_WAIT_ACON) {
302 DBG(1, "HNP: B_WAIT_ACON timeout; back to B_PERIPHERAL\n");
303 musb_g_disconnect(musb);
304 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
307 spin_unlock_irqrestore(&musb->lock, flags);
310 static DEFINE_TIMER(musb_otg_timer, musb_otg_timer_func, 0, 0);
313 * Stops the B-device HNP state. Caller must take care of locking.
315 void musb_hnp_stop(struct musb *musb)
317 struct usb_hcd *hcd = musb_to_hcd(musb);
318 void __iomem *mbase = musb->mregs;
321 switch (musb->xceiv.state) {
322 case OTG_STATE_A_PERIPHERAL:
323 case OTG_STATE_A_WAIT_VFALL:
324 DBG(1, "HNP: Switching back to A-host\n");
325 musb_g_disconnect(musb);
326 musb->xceiv.state = OTG_STATE_A_IDLE;
330 case OTG_STATE_B_HOST:
331 DBG(1, "HNP: Disabling HR\n");
332 hcd->self.is_b_host = 0;
333 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
335 reg = musb_readb(mbase, MUSB_POWER);
336 reg |= MUSB_POWER_SUSPENDM;
337 musb_writeb(mbase, MUSB_POWER, reg);
338 /* REVISIT: Start SESSION_REQUEST here? */
341 DBG(1, "HNP: Stopping in unknown state %s\n",
342 otg_state_string(musb));
349 * Interrupt Service Routine to record USB "global" interrupts.
350 * Since these do not happen often and signify things of
351 * paramount importance, it seems OK to check them individually;
352 * the order of the tests is specified in the manual
354 * @param musb instance pointer
355 * @param int_usb register contents
360 #define STAGE0_MASK (MUSB_INTR_RESUME | MUSB_INTR_SESSREQ \
361 | MUSB_INTR_VBUSERROR | MUSB_INTR_CONNECT \
364 static irqreturn_t musb_stage0_irq(struct musb * musb, u8 int_usb,
367 irqreturn_t handled = IRQ_NONE;
368 void __iomem *mbase = musb->mregs;
370 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
373 /* in host mode, the peripheral may issue remote wakeup.
374 * in peripheral mode, the host may resume the link.
375 * spurious RESUME irqs happen too, paired with SUSPEND.
377 if (int_usb & MUSB_INTR_RESUME) {
378 handled = IRQ_HANDLED;
379 DBG(3, "RESUME (%s)\n", otg_state_string(musb));
381 if (devctl & MUSB_DEVCTL_HM) {
382 #ifdef CONFIG_USB_MUSB_HDRC_HCD
383 switch (musb->xceiv.state) {
384 case OTG_STATE_A_SUSPEND:
385 /* remote wakeup? later, GetPortStatus
386 * will stop RESUME signaling
389 if (power & MUSB_POWER_SUSPENDM) {
391 musb->int_usb &= ~MUSB_INTR_SUSPEND;
392 DBG(2, "Spurious SUSPENDM\n");
396 power &= ~MUSB_POWER_SUSPENDM;
397 musb_writeb(mbase, MUSB_POWER,
398 power | MUSB_POWER_RESUME);
400 musb->port1_status |=
401 (USB_PORT_STAT_C_SUSPEND << 16)
402 | MUSB_PORT_STAT_RESUME;
403 musb->rh_timer = jiffies
404 + msecs_to_jiffies(20);
406 musb->xceiv.state = OTG_STATE_A_HOST;
408 usb_hcd_resume_root_hub(musb_to_hcd(musb));
410 case OTG_STATE_B_WAIT_ACON:
411 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
416 WARN("bogus %s RESUME (%s)\n",
418 otg_state_string(musb));
422 switch (musb->xceiv.state) {
423 #ifdef CONFIG_USB_MUSB_HDRC_HCD
424 case OTG_STATE_A_SUSPEND:
425 /* possibly DISCONNECT is upcoming */
426 musb->xceiv.state = OTG_STATE_A_HOST;
427 usb_hcd_resume_root_hub(musb_to_hcd(musb));
430 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
431 case OTG_STATE_B_WAIT_ACON:
432 case OTG_STATE_B_PERIPHERAL:
433 /* disconnect while suspended? we may
434 * not get a disconnect irq...
436 if ((devctl & MUSB_DEVCTL_VBUS)
437 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
439 musb->int_usb |= MUSB_INTR_DISCONNECT;
440 musb->int_usb &= ~MUSB_INTR_SUSPEND;
445 case OTG_STATE_B_IDLE:
446 musb->int_usb &= ~MUSB_INTR_SUSPEND;
450 WARN("bogus %s RESUME (%s)\n",
452 otg_state_string(musb));
457 #ifdef CONFIG_USB_MUSB_HDRC_HCD
458 /* see manual for the order of the tests */
459 if (int_usb & MUSB_INTR_SESSREQ) {
460 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb));
462 /* IRQ arrives from ID pin sense or (later, if VBUS power
463 * is removed) SRP. responses are time critical:
464 * - turn on VBUS (with silicon-specific mechanism)
465 * - go through A_WAIT_VRISE
466 * - ... to A_WAIT_BCON.
467 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
469 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
470 musb->ep0_stage = MUSB_EP0_START;
471 musb->xceiv.state = OTG_STATE_A_IDLE;
473 musb_set_vbus(musb, 1);
475 handled = IRQ_HANDLED;
478 if (int_usb & MUSB_INTR_VBUSERROR) {
481 /* During connection as an A-Device, we may see a short
482 * current spikes causing voltage drop, because of cable
483 * and peripheral capacitance combined with vbus draw.
484 * (So: less common with truly self-powered devices, where
485 * vbus doesn't act like a power supply.)
487 * Such spikes are short; usually less than ~500 usec, max
488 * of ~2 msec. That is, they're not sustained overcurrent
489 * errors, though they're reported using VBUSERROR irqs.
491 * Workarounds: (a) hardware: use self powered devices.
492 * (b) software: ignore non-repeated VBUS errors.
494 * REVISIT: do delays from lots of DEBUG_KERNEL checks
495 * make trouble here, keeping VBUS < 4.4V ?
497 switch (musb->xceiv.state) {
498 case OTG_STATE_A_HOST:
499 /* recovery is dicey once we've gotten past the
500 * initial stages of enumeration, but if VBUS
501 * stayed ok at the other end of the link, and
502 * another reset is due (at least for high speed,
503 * to redo the chirp etc), it might work OK...
505 case OTG_STATE_A_WAIT_BCON:
506 case OTG_STATE_A_WAIT_VRISE:
507 if (musb->vbuserr_retry) {
508 musb->vbuserr_retry--;
510 devctl |= MUSB_DEVCTL_SESSION;
511 musb_writeb(mbase, MUSB_DEVCTL, devctl);
513 musb->port1_status |=
514 (1 << USB_PORT_FEAT_OVER_CURRENT)
515 | (1 << USB_PORT_FEAT_C_OVER_CURRENT);
522 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
523 otg_state_string(musb),
526 switch (devctl & MUSB_DEVCTL_VBUS) {
527 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
528 s = "<SessEnd"; break;
529 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
530 s = "<AValid"; break;
531 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
532 s = "<VBusValid"; break;
533 //case 3 << MUSB_DEVCTL_VBUS_SHIFT:
537 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
540 /* go through A_WAIT_VFALL then start a new session */
542 musb_set_vbus(musb, 0);
543 handled = IRQ_HANDLED;
546 if (int_usb & MUSB_INTR_CONNECT) {
547 struct usb_hcd *hcd = musb_to_hcd(musb);
549 handled = IRQ_HANDLED;
551 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
553 musb->ep0_stage = MUSB_EP0_START;
555 #ifdef CONFIG_USB_MUSB_OTG
556 /* flush endpoints when transitioning from Device Mode */
557 if (is_peripheral_active(musb)) {
558 // REVISIT HNP; just force disconnect
560 musb_writew(mbase, MUSB_INTRTXE, musb->epmask);
561 musb_writew(mbase, MUSB_INTRRXE, musb->epmask & 0xfffe);
562 musb_writeb(mbase, MUSB_INTRUSBE, 0xf7);
564 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
565 |USB_PORT_STAT_HIGH_SPEED
566 |USB_PORT_STAT_ENABLE
568 musb->port1_status |= USB_PORT_STAT_CONNECTION
569 |(USB_PORT_STAT_C_CONNECTION << 16);
571 /* high vs full speed is just a guess until after reset */
572 if (devctl & MUSB_DEVCTL_LSDEV)
573 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
576 usb_hcd_poll_rh_status(hcd);
578 usb_hcd_resume_root_hub(hcd);
582 /* indicate new connection to OTG machine */
583 switch (musb->xceiv.state) {
584 case OTG_STATE_B_PERIPHERAL:
585 if (int_usb & MUSB_INTR_SUSPEND) {
586 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n");
587 musb->xceiv.state = OTG_STATE_B_HOST;
588 hcd->self.is_b_host = 1;
589 int_usb &= ~MUSB_INTR_SUSPEND;
591 DBG(1, "CONNECT as b_peripheral???\n");
593 case OTG_STATE_B_WAIT_ACON:
594 DBG(1, "HNP: Waiting to switch to b_host state\n");
595 musb->xceiv.state = OTG_STATE_B_HOST;
596 hcd->self.is_b_host = 1;
599 if ((devctl & MUSB_DEVCTL_VBUS)
600 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
601 musb->xceiv.state = OTG_STATE_A_HOST;
602 hcd->self.is_b_host = 0;
606 DBG(1, "CONNECT (%s) devctl %02x\n",
607 otg_state_string(musb), devctl);
609 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
611 /* mentor saves a bit: bus reset and babble share the same irq.
612 * only host sees babble; only peripheral sees bus reset.
614 if (int_usb & MUSB_INTR_RESET) {
615 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
617 * Looks like non-HS BABBLE can be ignored, but
618 * HS BABBLE is an error condition. For HS the solution
619 * is to avoid babble in the first place and fix what
620 * caused BABBLE. When HS BABBLE happens we can only
623 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
624 DBG(1, "BABBLE devctl: %02x\n", devctl);
626 ERR("Stopping host session -- babble\n");
627 musb_writeb(mbase, MUSB_DEVCTL, 0);
629 } else if (is_peripheral_capable()) {
630 DBG(1, "BUS RESET\n");
633 schedule_work(&musb->irq_work);
636 handled = IRQ_HANDLED;
643 * Interrupt Service Routine to record USB "global" interrupts.
644 * Since these do not happen often and signify things of
645 * paramount importance, it seems OK to check them individually;
646 * the order of the tests is specified in the manual
648 * @param musb instance pointer
649 * @param int_usb register contents
653 static irqreturn_t musb_stage2_irq(struct musb * musb, u8 int_usb,
656 irqreturn_t handled = IRQ_NONE;
659 /* REVISIT ... this would be for multiplexing periodic endpoints, or
660 * supporting transfer phasing to prevent exceeding ISO bandwidth
661 * limits of a given frame or microframe.
663 * It's not needed for peripheral side, which dedicates endpoints;
664 * though it _might_ use SOF irqs for other purposes.
666 * And it's not currently needed for host side, which also dedicates
667 * endpoints, relies on TX/RX interval registers, and isn't claimed
668 * to support ISO transfers yet.
670 if (int_usb & MUSB_INTR_SOF) {
671 void __iomem *mbase = musb->mregs;
672 struct musb_hw_ep *ep;
676 DBG(6, "START_OF_FRAME\n");
677 handled = IRQ_HANDLED;
679 /* start any periodic Tx transfers waiting for current frame */
680 frame = musb_readw(mbase, MUSB_FRAME);
681 ep = musb->endpoints;
682 for (epnum = 1; (epnum < musb->nr_endpoints)
683 && (musb->epmask >= (1 << epnum));
685 // FIXME handle framecounter wraps (12 bits)
686 // eliminate duplicated StartUrb logic
687 if (ep->dwWaitFrame >= frame) {
689 printk("SOF --> periodic TX%s on %d\n",
690 ep->tx_channel ? " DMA" : "",
693 musb_h_tx_start(musb, epnum);
695 cppi_hostdma_start(musb, epnum);
697 } /* end of for loop */
701 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
702 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
703 otg_state_string(musb),
704 MUSB_MODE(musb), devctl);
705 handled = IRQ_HANDLED;
707 switch (musb->xceiv.state) {
708 #ifdef CONFIG_USB_MUSB_HDRC_HCD
709 case OTG_STATE_A_HOST:
710 case OTG_STATE_A_SUSPEND:
711 musb_root_disconnect(musb);
712 if (musb->a_wait_bcon != 0)
713 musb_platform_try_idle(musb, jiffies
714 + msecs_to_jiffies(musb->a_wait_bcon));
717 #ifdef CONFIG_USB_MUSB_OTG
718 case OTG_STATE_B_HOST:
721 case OTG_STATE_A_PERIPHERAL:
722 musb_root_disconnect(musb);
724 case OTG_STATE_B_WAIT_ACON:
727 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
728 case OTG_STATE_B_PERIPHERAL:
729 case OTG_STATE_B_IDLE:
730 musb_g_disconnect(musb);
734 WARN("unhandled DISCONNECT transition (%s)\n",
735 otg_state_string(musb));
739 schedule_work(&musb->irq_work);
742 if (int_usb & MUSB_INTR_SUSPEND) {
743 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
744 otg_state_string(musb), devctl, power);
745 handled = IRQ_HANDLED;
747 switch (musb->xceiv.state) {
748 #ifdef CONFIG_USB_MUSB_OTG
749 case OTG_STATE_A_PERIPHERAL:
753 case OTG_STATE_B_PERIPHERAL:
754 musb_g_suspend(musb);
755 musb->is_active = is_otg_enabled(musb)
756 && musb->xceiv.gadget->b_hnp_enable;
757 if (musb->is_active) {
758 musb->xceiv.state = OTG_STATE_B_WAIT_ACON;
759 #ifdef CONFIG_USB_MUSB_OTG
760 DBG(1, "HNP: Setting timer for b_ase0_brst\n");
761 musb_otg_timer.data = (unsigned long)musb;
762 mod_timer(&musb_otg_timer, jiffies
763 + msecs_to_jiffies(TB_ASE0_BRST));
767 case OTG_STATE_A_WAIT_BCON:
768 if (musb->a_wait_bcon != 0)
769 musb_platform_try_idle(musb, jiffies
770 + msecs_to_jiffies(musb->a_wait_bcon));
772 case OTG_STATE_A_HOST:
773 musb->xceiv.state = OTG_STATE_A_SUSPEND;
774 musb->is_active = is_otg_enabled(musb)
775 && musb->xceiv.host->b_hnp_enable;
777 case OTG_STATE_B_HOST:
778 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
779 DBG(1, "REVISIT: SUSPEND as B_HOST\n");
782 /* "should not happen" */
792 /*-------------------------------------------------------------------------*/
795 * Program the HDRC to start (enable interrupts, dma, etc.).
797 void musb_start(struct musb *musb)
799 void __iomem *regs = musb->mregs;
800 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
802 DBG(2, "<== devctl %02x\n", devctl);
804 /* Set INT enable registers, enable interrupts */
805 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
806 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
807 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
809 musb_writeb(regs, MUSB_TESTMODE, 0);
811 /* put into basic highspeed mode and start session */
812 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
813 | MUSB_POWER_SOFTCONN
815 /* ENSUSPEND wedges tusb */
816 // | MUSB_POWER_ENSUSPEND
820 devctl = musb_readb(regs, MUSB_DEVCTL);
821 devctl &= ~MUSB_DEVCTL_SESSION;
823 if (is_otg_enabled(musb)) {
824 /* session started after:
825 * (a) ID-grounded irq, host mode;
826 * (b) vbus present/connect IRQ, peripheral mode;
827 * (c) peripheral initiates, using SRP
829 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
832 devctl |= MUSB_DEVCTL_SESSION;
834 } else if (is_host_enabled(musb)) {
835 /* assume ID pin is hard-wired to ground */
836 devctl |= MUSB_DEVCTL_SESSION;
838 } else /* peripheral is enabled */ {
839 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
842 musb_platform_enable(musb);
843 musb_writeb(regs, MUSB_DEVCTL, devctl);
847 static void musb_generic_disable(struct musb *musb)
849 void __iomem *mbase = musb->mregs;
852 /* disable interrupts */
853 musb_writeb(mbase, MUSB_INTRUSBE, 0);
854 musb_writew(mbase, MUSB_INTRTXE, 0);
855 musb_writew(mbase, MUSB_INTRRXE, 0);
858 musb_writeb(mbase, MUSB_DEVCTL, 0);
860 /* flush pending interrupts */
861 temp = musb_readb(mbase, MUSB_INTRUSB);
862 temp = musb_readw(mbase, MUSB_INTRTX);
863 temp = musb_readw(mbase, MUSB_INTRRX);
868 * Make the HDRC stop (disable interrupts, etc.);
869 * reversible by musb_start
870 * called on gadget driver unregister
871 * with controller locked, irqs blocked
872 * acts as a NOP unless some role activated the hardware
874 void musb_stop(struct musb *musb)
876 /* stop IRQs, timers, ... */
877 musb_platform_disable(musb);
878 musb_generic_disable(musb);
879 DBG(3, "HDRC disabled\n");
882 * - mark host and/or peripheral drivers unusable/inactive
883 * - disable DMA (and enable it in HdrcStart)
884 * - make sure we can musb_start() after musb_stop(); with
885 * OTG mode, gadget driver module rmmod/modprobe cycles that
888 musb_platform_try_idle(musb, 0);
891 static void musb_shutdown(struct platform_device *pdev)
893 struct musb *musb = dev_to_musb(&pdev->dev);
896 spin_lock_irqsave(&musb->lock, flags);
897 musb_platform_disable(musb);
898 musb_generic_disable(musb);
900 clk_put(musb->clock);
903 spin_unlock_irqrestore(&musb->lock, flags);
905 /* FIXME power down */
909 /*-------------------------------------------------------------------------*/
912 * The silicon either has hard-wired endpoint configurations, or else
913 * "dynamic fifo" sizing. The driver has support for both, though at this
914 * writing only the dynamic sizing is very well tested. We use normal
915 * idioms to so both modes are compile-tested, but dead code elimination
916 * leaves only the relevant one in the object file.
918 * We don't currently use dynamic fifo setup capability to do anything
919 * more than selecting one of a bunch of predefined configurations.
921 #ifdef MUSB_C_DYNFIFO_DEF
922 #define can_dynfifo() 1
924 #define can_dynfifo() 0
927 #ifdef CONFIG_USB_TUSB6010
928 static ushort __initdata fifo_mode = 4;
930 static ushort __initdata fifo_mode = 2;
933 /* "modprobe ... fifo_mode=1" etc */
934 module_param(fifo_mode, ushort, 0);
935 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
938 #define DYN_FIFO_SIZE (1<<(MUSB_C_RAM_BITS+2))
940 enum fifo_style { FIFO_RXTX, FIFO_TX, FIFO_RX } __attribute__ ((packed));
941 enum buf_mode { BUF_SINGLE, BUF_DOUBLE } __attribute__ ((packed));
945 enum fifo_style style;
951 * tables defining fifo_mode values. define more if you like.
952 * for host side, make sure both halves of ep1 are set up.
955 /* mode 0 - fits in 2KB */
956 static struct fifo_cfg __initdata mode_0_cfg[] = {
957 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
958 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
959 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
960 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
961 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
964 /* mode 1 - fits in 4KB */
965 static struct fifo_cfg __initdata mode_1_cfg[] = {
966 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
967 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
968 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
969 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
970 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
973 /* mode 2 - fits in 4KB */
974 static struct fifo_cfg __initdata mode_2_cfg[] = {
975 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
976 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
977 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
978 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
979 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
980 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
983 /* mode 3 - fits in 4KB */
984 static struct fifo_cfg __initdata mode_3_cfg[] = {
985 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
986 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
987 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
988 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
989 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
990 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
993 /* mode 4 - fits in 16KB */
994 static struct fifo_cfg __initdata mode_4_cfg[] = {
995 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
996 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
997 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
998 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
999 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1000 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1001 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1002 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1003 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1004 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1005 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1006 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1007 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1008 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1009 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1010 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1011 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1012 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1013 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 512, },
1014 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 512, },
1015 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 512, },
1016 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 512, },
1017 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 512, },
1018 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 512, },
1019 { .hw_ep_num = 13, .style = FIFO_TX, .maxpacket = 512, },
1020 { .hw_ep_num = 13, .style = FIFO_RX, .maxpacket = 512, },
1021 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1022 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1027 * configure a fifo; for non-shared endpoints, this may be called
1028 * once for a tx fifo and once for an rx fifo.
1030 * returns negative errno or offset for next fifo.
1033 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1034 const struct fifo_cfg *cfg, u16 offset)
1036 void __iomem *mbase = musb->mregs;
1038 u16 maxpacket = cfg->maxpacket;
1039 u16 c_off = offset >> 3;
1042 /* expect hw_ep has already been zero-initialized */
1044 size = ffs(max(maxpacket, (u16) 8)) - 1;
1045 maxpacket = 1 << size;
1048 if (cfg->mode == BUF_DOUBLE) {
1049 if ((offset + (maxpacket << 1)) > DYN_FIFO_SIZE)
1051 c_size |= MUSB_FIFOSZ_DPB;
1053 if ((offset + maxpacket) > DYN_FIFO_SIZE)
1057 /* configure the FIFO */
1058 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1060 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1061 /* EP0 reserved endpoint for control, bidirectional;
1062 * EP1 reserved for bulk, two unidirection halves.
1064 if (hw_ep->epnum == 1)
1065 musb->bulk_ep = hw_ep;
1066 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1068 switch (cfg->style) {
1070 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
1071 musb_writew(mbase, MUSB_TXFIFOADD, c_off);
1072 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1073 hw_ep->max_packet_sz_tx = maxpacket;
1076 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
1077 musb_writew(mbase, MUSB_RXFIFOADD, c_off);
1078 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1079 hw_ep->max_packet_sz_rx = maxpacket;
1082 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
1083 musb_writew(mbase, MUSB_TXFIFOADD, c_off);
1084 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1085 hw_ep->max_packet_sz_rx = maxpacket;
1087 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
1088 musb_writew(mbase, MUSB_RXFIFOADD, c_off);
1089 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1090 hw_ep->max_packet_sz_tx = maxpacket;
1092 hw_ep->is_shared_fifo = true;
1096 /* NOTE rx and tx endpoint irqs aren't managed separately,
1097 * which happens to be ok
1099 musb->epmask |= (1 << hw_ep->epnum);
1101 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1104 static struct fifo_cfg __initdata ep0_cfg = {
1105 .style = FIFO_RXTX, .maxpacket = 64,
1108 static int __init ep_config_from_table(struct musb *musb)
1110 const struct fifo_cfg *cfg;
1113 struct musb_hw_ep *hw_ep = musb->endpoints;
1115 switch (fifo_mode) {
1121 n = ARRAY_SIZE(mode_0_cfg);
1125 n = ARRAY_SIZE(mode_1_cfg);
1129 n = ARRAY_SIZE(mode_2_cfg);
1133 n = ARRAY_SIZE(mode_3_cfg);
1137 n = ARRAY_SIZE(mode_4_cfg);
1141 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1142 musb_driver_name, fifo_mode);
1145 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1146 // assert(offset > 0)
1148 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1149 * be better than static MUSB_C_NUM_EPS and DYN_FIFO_SIZE...
1152 for (i = 0; i < n; i++) {
1153 u8 epn = cfg->hw_ep_num;
1155 if (epn >= MUSB_C_NUM_EPS) {
1156 pr_debug( "%s: invalid ep %d\n",
1157 musb_driver_name, epn);
1160 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1162 pr_debug( "%s: mem overrun, ep %d\n",
1163 musb_driver_name, epn);
1167 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1170 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1172 n + 1, MUSB_C_NUM_EPS * 2 - 1,
1173 offset, DYN_FIFO_SIZE);
1175 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1176 if (!musb->bulk_ep) {
1177 pr_debug( "%s: missing bulk\n", musb_driver_name);
1187 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1188 * @param musb the controller
1190 static int __init ep_config_from_hw(struct musb *musb)
1193 struct musb_hw_ep *hw_ep;
1194 void *mbase = musb->mregs;
1196 DBG(2, "<== static silicon ep config\n");
1198 /* FIXME pick up ep0 maxpacket size */
1200 for (epnum = 1; epnum < MUSB_C_NUM_EPS; epnum++) {
1201 musb_ep_select(mbase, epnum);
1202 hw_ep = musb->endpoints + epnum;
1204 /* read from core using indexed model */
1205 reg = musb_readb(hw_ep->regs, 0x10 + MUSB_FIFOSIZE);
1207 /* 0's returned when no more endpoints */
1210 musb->nr_endpoints++;
1211 musb->epmask |= (1 << epnum);
1213 hw_ep->max_packet_sz_tx = 1 << (reg & 0x0f);
1215 /* shared TX/RX FIFO? */
1216 if ((reg & 0xf0) == 0xf0) {
1217 hw_ep->max_packet_sz_rx = hw_ep->max_packet_sz_tx;
1218 hw_ep->is_shared_fifo = true;
1221 hw_ep->max_packet_sz_rx = 1 << ((reg & 0xf0) >> 4);
1222 hw_ep->is_shared_fifo = false;
1225 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1227 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1228 /* pick an RX/TX endpoint for bulk */
1229 if (hw_ep->max_packet_sz_tx < 512
1230 || hw_ep->max_packet_sz_rx < 512)
1233 /* REVISIT: this algorithm is lazy, we should at least
1234 * try to pick a double buffered endpoint.
1238 musb->bulk_ep = hw_ep;
1242 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1243 if (!musb->bulk_ep) {
1244 pr_debug( "%s: missing bulk\n", musb_driver_name);
1252 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1254 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1255 * configure endpoints, or take their config from silicon
1257 static int __init musb_core_init(u16 musb_type, struct musb *musb)
1264 u16 hwvers, rev_major, rev_minor;
1265 char aInfo[78], aRevision[32], aDate[12];
1266 void __iomem *mbase = musb->mregs;
1270 /* log core options (read using indexed model) */
1271 musb_ep_select(mbase, 0);
1272 reg = musb_readb(mbase, 0x10 + MUSB_CONFIGDATA);
1274 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1275 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1276 strcat(aInfo, ", dyn FIFOs");
1278 if (reg & MUSB_CONFIGDATA_MPRXE) {
1279 strcat(aInfo, ", bulk combine");
1281 musb->bulk_combine = true;
1283 strcat(aInfo, " (X)"); /* no driver support */
1286 if (reg & MUSB_CONFIGDATA_MPTXE) {
1287 strcat(aInfo, ", bulk split");
1289 musb->bulk_split = true;
1291 strcat(aInfo, " (X)"); /* no driver support */
1294 if (reg & MUSB_CONFIGDATA_HBRXE) {
1295 strcat(aInfo, ", HB-ISO Rx");
1296 strcat(aInfo, " (X)"); /* no driver support */
1298 if (reg & MUSB_CONFIGDATA_HBTXE) {
1299 strcat(aInfo, ", HB-ISO Tx");
1300 strcat(aInfo, " (X)"); /* no driver support */
1302 if (reg & MUSB_CONFIGDATA_SOFTCONE) {
1303 strcat(aInfo, ", SoftConn");
1306 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1307 musb_driver_name, reg, aInfo);
1310 data = musb_readl(mbase, 0x404);
1311 sprintf(aDate, "%04d-%02x-%02x", (data & 0xffff),
1312 (data >> 16) & 0xff, (data >> 24) & 0xff);
1313 /* FIXME ID2 and ID3 are unused */
1314 data = musb_readl(mbase, 0x408);
1315 printk("ID2=%lx\n", (long unsigned)data);
1316 data = musb_readl(mbase, 0x40c);
1317 printk("ID3=%lx\n", (long unsigned)data);
1318 reg = musb_readb(mbase, 0x400);
1319 musb_type = ('M' == reg) ? MUSB_CONTROLLER_MHDRC : MUSB_CONTROLLER_HDRC;
1323 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1324 musb->is_multipoint = 1;
1327 musb->is_multipoint = 0;
1329 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1330 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1332 "%s: kernel must blacklist external hubs\n",
1338 /* log release info */
1339 hwvers = musb_readw(mbase, MUSB_HWVERS);
1340 rev_major = (hwvers >> 10) & 0x1f;
1341 rev_minor = hwvers & 0x3ff;
1342 snprintf(aRevision, 32, "%d.%d%s", rev_major,
1343 rev_minor, (hwvers & 0x8000) ? "RC" : "");
1344 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1345 musb_driver_name, type, aRevision, aDate);
1348 musb->endpoints[0].max_packet_sz_tx = MUSB_EP0_FIFOSIZE;
1349 musb->endpoints[0].max_packet_sz_rx = MUSB_EP0_FIFOSIZE;
1351 /* discover endpoint configuration */
1352 musb->nr_endpoints = 1;
1355 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1357 status = ep_config_from_table(musb);
1359 ERR("reconfigure software for Dynamic FIFOs\n");
1364 status = ep_config_from_hw(musb);
1366 ERR("reconfigure software for static FIFOs\n");
1374 /* finish init, and print endpoint config */
1375 for (i = 0; i < musb->nr_endpoints; i++) {
1376 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1378 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1379 #ifdef CONFIG_USB_TUSB6010
1380 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1381 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1382 hw_ep->fifo_sync_va =
1383 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1386 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1388 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1391 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1392 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1393 hw_ep->target_regs = MUSB_BUSCTL_OFFSET(i, 0) + mbase;
1394 hw_ep->rx_reinit = 1;
1395 hw_ep->tx_reinit = 1;
1398 if (hw_ep->max_packet_sz_tx) {
1400 "%s: hw_ep %d%s, %smax %d\n",
1401 musb_driver_name, i,
1402 hw_ep->is_shared_fifo ? "shared" : "tx",
1403 hw_ep->tx_double_buffered
1404 ? "doublebuffer, " : "",
1405 hw_ep->max_packet_sz_tx);
1407 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1409 "%s: hw_ep %d%s, %smax %d\n",
1410 musb_driver_name, i,
1412 hw_ep->rx_double_buffered
1413 ? "doublebuffer, " : "",
1414 hw_ep->max_packet_sz_rx);
1416 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1417 DBG(1, "hw_ep %d not configured\n", i);
1423 /*-------------------------------------------------------------------------*/
1425 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
1427 static irqreturn_t generic_interrupt(int irq, void *__hci)
1429 unsigned long flags;
1430 irqreturn_t retval = IRQ_NONE;
1431 struct musb *musb = __hci;
1433 spin_lock_irqsave(&musb->lock, flags);
1435 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1436 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1437 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1439 if (musb->int_usb || musb->int_tx || musb->int_rx)
1440 retval = musb_interrupt(musb);
1442 spin_unlock_irqrestore(&musb->lock, flags);
1444 /* REVISIT we sometimes get spurious IRQs on g_ep0
1447 if (retval != IRQ_HANDLED)
1448 DBG(5, "spurious?\n");
1454 #define generic_interrupt NULL
1458 * handle all the irqs defined by the HDRC core. for now we expect: other
1459 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1460 * will be assigned, and the irq will already have been acked.
1462 * called in irq context with spinlock held, irqs blocked
1464 irqreturn_t musb_interrupt(struct musb *musb)
1466 irqreturn_t retval = IRQ_NONE;
1471 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1472 power = musb_readb(musb->mregs, MUSB_POWER);
1474 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
1475 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1476 musb->int_usb, musb->int_tx, musb->int_rx);
1478 /* the core can interrupt us for multiple reasons; docs have
1479 * a generic interrupt flowchart to follow
1481 if (musb->int_usb & STAGE0_MASK)
1482 retval |= musb_stage0_irq(musb, musb->int_usb,
1485 /* "stage 1" is handling endpoint irqs */
1487 /* handle endpoint 0 first */
1488 if (musb->int_tx & 1) {
1489 if (devctl & MUSB_DEVCTL_HM)
1490 retval |= musb_h_ep0_irq(musb);
1492 retval |= musb_g_ep0_irq(musb);
1495 /* RX on endpoints 1-15 */
1496 reg = musb->int_rx >> 1;
1500 // musb_ep_select(musb->mregs, ep_num);
1501 /* REVISIT just retval = ep->rx_irq(...) */
1502 retval = IRQ_HANDLED;
1503 if (devctl & MUSB_DEVCTL_HM) {
1504 if (is_host_capable())
1505 musb_host_rx(musb, ep_num);
1507 if (is_peripheral_capable())
1508 musb_g_rx(musb, ep_num);
1516 /* TX on endpoints 1-15 */
1517 reg = musb->int_tx >> 1;
1521 // musb_ep_select(musb->mregs, ep_num);
1522 /* REVISIT just retval |= ep->tx_irq(...) */
1523 retval = IRQ_HANDLED;
1524 if (devctl & MUSB_DEVCTL_HM) {
1525 if (is_host_capable())
1526 musb_host_tx(musb, ep_num);
1528 if (is_peripheral_capable())
1529 musb_g_tx(musb, ep_num);
1536 /* finish handling "global" interrupts after handling fifos */
1538 retval |= musb_stage2_irq(musb,
1539 musb->int_usb, devctl, power);
1545 #ifndef CONFIG_MUSB_PIO_ONLY
1546 static int __initdata use_dma = 1;
1548 /* "modprobe ... use_dma=0" etc */
1549 module_param(use_dma, bool, 0);
1550 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1552 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1554 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1556 /* called with controller lock already held */
1559 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1560 if (!is_cppi_enabled()) {
1562 if (devctl & MUSB_DEVCTL_HM)
1563 musb_h_ep0_irq(musb);
1565 musb_g_ep0_irq(musb);
1569 /* endpoints 1..15 */
1571 if (devctl & MUSB_DEVCTL_HM) {
1572 if (is_host_capable())
1573 musb_host_tx(musb, epnum);
1575 if (is_peripheral_capable())
1576 musb_g_tx(musb, epnum);
1580 if (devctl & MUSB_DEVCTL_HM) {
1581 if (is_host_capable())
1582 musb_host_rx(musb, epnum);
1584 if (is_peripheral_capable())
1585 musb_g_rx(musb, epnum);
1595 /*-------------------------------------------------------------------------*/
1600 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1602 struct musb *musb = dev_to_musb(dev);
1603 unsigned long flags;
1606 spin_lock_irqsave(&musb->lock, flags);
1607 ret = sprintf(buf, "%s\n", otg_state_string(musb));
1608 spin_unlock_irqrestore(&musb->lock, flags);
1614 musb_mode_store(struct device *dev, struct device_attribute *attr,
1615 const char *buf, size_t n)
1617 struct musb *musb = dev_to_musb(dev);
1618 unsigned long flags;
1620 spin_lock_irqsave(&musb->lock, flags);
1621 if (!strncmp(buf, "host", 4))
1622 musb_platform_set_mode(musb, MUSB_HOST);
1623 if (!strncmp(buf, "peripheral", 10))
1624 musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1625 if (!strncmp(buf, "otg", 3))
1626 musb_platform_set_mode(musb, MUSB_OTG);
1627 spin_unlock_irqrestore(&musb->lock, flags);
1631 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1634 musb_cable_show(struct device *dev, struct device_attribute *attr, char *buf)
1636 struct musb *musb = dev_to_musb(dev);
1637 char *v1= "", *v2 = "?";
1638 unsigned long flags;
1641 spin_lock_irqsave(&musb->lock, flags);
1642 #if defined(CONFIG_USB_TUSB6010) && !defined(CONFIG_USB_MUSB_OTG)
1643 /* REVISIT: connect-A != connect-B ... */
1644 vbus = musb_platform_get_vbus_status(musb);
1648 v2 = "disconnected";
1650 /* NOTE: board-specific issues, like too-big capacitors keeping
1651 * VBUS high for a long time after power has been removed, can
1652 * cause temporary false indications of a connection.
1654 vbus = musb_readb(musb->mregs, MUSB_DEVCTL);
1656 /* REVISIT retest on real OTG hardware */
1657 switch (musb->board_mode) {
1661 case MUSB_PERIPHERAL:
1666 v2 = (vbus & MUSB_DEVCTL_BDEVICE) ? "B" : "A";
1669 } else /* VBUS level below A-Valid */
1670 v2 = "disconnected";
1672 musb_platform_try_idle(musb, 0);
1673 spin_unlock_irqrestore(&musb->lock, flags);
1675 return sprintf(buf, "%s%s\n", v1, v2);
1677 static DEVICE_ATTR(cable, S_IRUGO, musb_cable_show, NULL);
1680 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1681 const char *buf, size_t n)
1683 struct musb *musb = dev_to_musb(dev);
1684 unsigned long flags;
1687 spin_lock_irqsave(&musb->lock, flags);
1688 if (sscanf(buf, "%lu", &val) < 1) {
1689 printk(KERN_ERR "Invalid VBUS timeout ms value\n");
1692 musb->a_wait_bcon = val;
1693 if (musb->xceiv.state == OTG_STATE_A_WAIT_BCON)
1694 musb->is_active = 0;
1695 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1696 spin_unlock_irqrestore(&musb->lock, flags);
1702 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1704 struct musb *musb = dev_to_musb(dev);
1705 unsigned long flags;
1708 spin_lock_irqsave(&musb->lock, flags);
1709 val = musb->a_wait_bcon;
1710 spin_unlock_irqrestore(&musb->lock, flags);
1712 return sprintf(buf, "%lu\n", val);
1714 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1716 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1718 /* Gadget drivers can't know that a host is connected so they might want
1719 * to start SRP, but users can. This allows userspace to trigger SRP.
1722 musb_srp_store(struct device *dev, struct device_attribute *attr,
1723 const char *buf, size_t n)
1725 struct musb *musb=dev_to_musb(dev);
1728 if (sscanf(buf, "%hu", &srp) != 1
1730 printk (KERN_ERR "SRP: Value must be 1\n");
1735 musb_g_wakeup(musb);
1739 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1741 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
1745 /* Only used to provide cable state change events */
1746 static void musb_irq_work(struct work_struct *data)
1748 struct musb *musb = container_of(data, struct musb, irq_work);
1750 sysfs_notify(&musb->controller->kobj, NULL, "cable");
1753 /* --------------------------------------------------------------------------
1757 static struct musb *__init
1758 allocate_instance(struct device *dev, void __iomem *mbase)
1761 struct musb_hw_ep *ep;
1763 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1764 struct usb_hcd *hcd;
1766 hcd = usb_create_hcd(&musb_hc_driver, dev, dev->bus_id);
1769 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1771 musb = hcd_to_musb(hcd);
1772 INIT_LIST_HEAD(&musb->control);
1773 INIT_LIST_HEAD(&musb->in_bulk);
1774 INIT_LIST_HEAD(&musb->out_bulk);
1776 hcd->uses_new_polling = 1;
1778 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1780 musb = kzalloc(sizeof *musb, GFP_KERNEL);
1783 dev_set_drvdata(dev, musb);
1787 musb->mregs = mbase;
1788 musb->ctrl_base = mbase;
1789 musb->nIrq = -ENODEV;
1790 for (epnum = 0, ep = musb->endpoints;
1791 epnum < MUSB_C_NUM_EPS;
1798 musb->controller = dev;
1802 static void musb_free(struct musb *musb)
1804 /* this has multiple entry modes. it handles fault cleanup after
1805 * probe(), where things may be partially set up, as well as rmmod
1806 * cleanup after everything's been de-activated.
1810 device_remove_file(musb->controller, &dev_attr_mode);
1811 device_remove_file(musb->controller, &dev_attr_cable);
1812 device_remove_file(musb->controller, &dev_attr_vbus);
1813 #ifdef CONFIG_USB_MUSB_OTG
1814 device_remove_file(musb->controller, &dev_attr_srp);
1818 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1819 musb_gadget_cleanup(musb);
1822 if (musb->nIrq >= 0) {
1823 disable_irq_wake(musb->nIrq);
1824 free_irq(musb->nIrq, musb);
1826 if (is_dma_capable() && musb->dma_controller) {
1827 struct dma_controller *c = musb->dma_controller;
1829 (void) c->stop(c->private_data);
1830 dma_controller_destroy(c);
1833 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1834 musb_platform_exit(musb);
1835 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1838 clk_disable(musb->clock);
1839 clk_put(musb->clock);
1842 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1843 usb_put_hcd(musb_to_hcd(musb));
1850 * Perform generic per-controller initialization.
1852 * @pDevice: the controller (already clocked, etc)
1854 * @mregs: virtual address of controller registers,
1855 * not yet corrected for platform-specific offsets
1858 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1862 struct musb_hdrc_platform_data *plat = dev->platform_data;
1864 /* The driver might handle more features than the board; OK.
1865 * Fail when the board needs a feature that's not enabled.
1868 dev_dbg(dev, "no platform_data?\n");
1871 switch (plat->mode) {
1873 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1878 case MUSB_PERIPHERAL:
1879 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1885 #ifdef CONFIG_USB_MUSB_OTG
1891 dev_err(dev, "incompatible Kconfig role setting\n");
1896 musb = allocate_instance(dev, ctrl);
1900 spin_lock_init(&musb->lock);
1901 musb->board_mode = plat->mode;
1902 musb->board_set_power = plat->set_power;
1903 musb->set_clock = plat->set_clock;
1904 musb->min_power = plat->min_power;
1906 /* Clock usage is chip-specific ... functional clock (DaVinci,
1907 * OMAP2430), or PHY ref (some TUSB6010 boards). All this core
1908 * code does is make sure a clock handle is available; platform
1909 * code manages it during start/stop and suspend/resume.
1912 musb->clock = clk_get(dev, plat->clock);
1913 if (IS_ERR(musb->clock)) {
1914 status = PTR_ERR(musb->clock);
1920 /* assume vbus is off */
1922 /* platform adjusts musb->mregs and musb->isr if needed,
1923 * and activates clocks
1925 musb->isr = generic_interrupt;
1926 status = musb_platform_init(musb);
1935 #ifndef CONFIG_MUSB_PIO_ONLY
1936 if (use_dma && dev->dma_mask) {
1937 struct dma_controller *c;
1939 c = dma_controller_create(musb, musb->mregs);
1940 musb->dma_controller = c;
1942 (void) c->start(c->private_data);
1945 /* ideally this would be abstracted in platform setup */
1946 if (!is_dma_capable() || !musb->dma_controller)
1947 dev->dma_mask = NULL;
1949 /* be sure interrupts are disabled before connecting ISR */
1950 musb_platform_disable(musb);
1951 musb_generic_disable(musb);
1953 /* setup musb parts of the core (especially endpoints) */
1954 status = musb_core_init(plat->multipoint
1955 ? MUSB_CONTROLLER_MHDRC
1956 : MUSB_CONTROLLER_HDRC, musb);
1960 /* attach to the IRQ */
1961 if (request_irq (nIrq, musb->isr, 0, dev->bus_id, musb)) {
1962 dev_err(dev, "request_irq %d failed!\n", nIrq);
1967 // FIXME this handles wakeup irqs wrong
1968 if (enable_irq_wake(nIrq) == 0)
1969 device_init_wakeup(dev, 1);
1971 pr_info("%s: USB %s mode controller at %p using %s, IRQ %d\n",
1974 switch (musb->board_mode) {
1975 case MUSB_HOST: s = "Host"; break;
1976 case MUSB_PERIPHERAL: s = "Peripheral"; break;
1977 default: s = "OTG"; break;
1980 (is_dma_capable() && musb->dma_controller)
1984 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1985 /* host side needs more setup, except for no-host modes */
1986 if (musb->board_mode != MUSB_PERIPHERAL) {
1987 struct usb_hcd *hcd = musb_to_hcd(musb);
1989 if (musb->board_mode == MUSB_OTG)
1990 hcd->self.otg_port = 1;
1991 musb->xceiv.host = &hcd->self;
1992 hcd->power_budget = 2 * (plat->power ? : 250);
1994 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
1996 /* For the host-only role, we can activate right away.
1997 * (We expect the ID pin to be forcibly grounded!!)
1998 * Otherwise, wait till the gadget driver hooks up.
2000 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2001 MUSB_HST_MODE(musb);
2002 musb->xceiv.default_a = 1;
2003 musb->xceiv.state = OTG_STATE_A_IDLE;
2005 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2007 DBG(1, "%s mode, status %d, devctl %02x %c\n",
2009 musb_readb(musb->mregs, MUSB_DEVCTL),
2010 (musb_readb(musb->mregs, MUSB_DEVCTL)
2011 & MUSB_DEVCTL_BDEVICE
2014 } else /* peripheral is enabled */ {
2015 MUSB_DEV_MODE(musb);
2016 musb->xceiv.default_a = 0;
2017 musb->xceiv.state = OTG_STATE_B_IDLE;
2019 status = musb_gadget_setup(musb);
2021 DBG(1, "%s mode, status %d, dev%02x\n",
2022 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2024 musb_readb(musb->mregs, MUSB_DEVCTL));
2029 musb_debug_create("driver/musb_hdrc", musb);
2033 clk_put(musb->clock);
2034 device_init_wakeup(dev, 0);
2039 INIT_WORK(&musb->irq_work, musb_irq_work);
2042 status = device_create_file(dev, &dev_attr_mode);
2043 status = device_create_file(dev, &dev_attr_cable);
2044 status = device_create_file(dev, &dev_attr_vbus);
2045 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2046 status = device_create_file(dev, &dev_attr_srp);
2047 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
2054 musb_platform_exit(musb);
2058 /*-------------------------------------------------------------------------*/
2060 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2061 * bridge to a platform device; this driver then suffices.
2064 #ifndef CONFIG_MUSB_PIO_ONLY
2065 static u64 *orig_dma_mask;
2068 static int __init musb_probe(struct platform_device *pdev)
2070 struct device *dev = &pdev->dev;
2071 int irq = platform_get_irq(pdev, 0);
2072 struct resource *iomem;
2075 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2076 if (!iomem || irq == 0)
2079 base = ioremap(iomem->start, iomem->end - iomem->start + 1);
2081 dev_err(dev, "ioremap failed\n");
2085 #ifndef CONFIG_MUSB_PIO_ONLY
2086 /* clobbered by use_dma=n */
2087 orig_dma_mask = dev->dma_mask;
2089 return musb_init_controller(dev, irq, base);
2092 static int __devexit musb_remove(struct platform_device *pdev)
2094 struct musb *musb = dev_to_musb(&pdev->dev);
2095 void __iomem *ctrl_base = musb->ctrl_base;
2097 /* this gets called on rmmod.
2098 * - Host mode: host may still be active
2099 * - Peripheral mode: peripheral is deactivated (or never-activated)
2100 * - OTG mode: both roles are deactivated (or never-activated)
2102 musb_shutdown(pdev);
2103 musb_debug_delete("driver/musb_hdrc", musb);
2104 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2105 if (musb->board_mode == MUSB_HOST)
2106 usb_remove_hcd(musb_to_hcd(musb));
2110 device_init_wakeup(&pdev->dev, 0);
2111 #ifndef CONFIG_MUSB_PIO_ONLY
2112 pdev->dev.dma_mask = orig_dma_mask;
2119 static int musb_suspend(struct platform_device *pdev, pm_message_t message)
2121 unsigned long flags;
2122 struct musb *musb = dev_to_musb(&pdev->dev);
2127 spin_lock_irqsave(&musb->lock, flags);
2129 if (is_peripheral_active(musb)) {
2130 /* FIXME force disconnect unless we know USB will wake
2131 * the system up quickly enough to respond ...
2133 } else if (is_host_active(musb)) {
2134 /* we know all the children are suspended; sometimes
2135 * they will even be wakeup-enabled.
2139 if (musb->set_clock)
2140 musb->set_clock(musb->clock, 0);
2142 clk_disable(musb->clock);
2143 spin_unlock_irqrestore(&musb->lock, flags);
2147 static int musb_resume(struct platform_device *pdev)
2149 unsigned long flags;
2150 struct musb *musb = dev_to_musb(&pdev->dev);
2155 spin_lock_irqsave(&musb->lock, flags);
2157 if (musb->set_clock)
2158 musb->set_clock(musb->clock, 1);
2160 clk_enable(musb->clock);
2162 /* for static cmos like DaVinci, register values were preserved
2163 * unless for some reason the whole soc powered down and we're
2164 * not treating that as a whole-system restart (e.g. swsusp)
2166 spin_unlock_irqrestore(&musb->lock, flags);
2171 #define musb_suspend NULL
2172 #define musb_resume NULL
2175 static struct platform_driver musb_driver = {
2177 .name = (char *)musb_driver_name,
2178 .bus = &platform_bus_type,
2179 .owner = THIS_MODULE,
2181 .remove = __devexit_p(musb_remove),
2182 .shutdown = musb_shutdown,
2183 .suspend = musb_suspend,
2184 .resume = musb_resume,
2187 /*-------------------------------------------------------------------------*/
2189 static int __init musb_init(void)
2191 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2196 pr_info("%s: version " MUSB_VERSION ", "
2197 #ifdef CONFIG_MUSB_PIO_ONLY
2199 #elif defined(CONFIG_USB_TI_CPPI_DMA)
2201 #elif defined(CONFIG_USB_INVENTRA_DMA)
2203 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
2209 #ifdef CONFIG_USB_MUSB_OTG
2210 "otg (peripheral+host)"
2211 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
2213 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2217 musb_driver_name, debug);
2218 return platform_driver_probe(&musb_driver, musb_probe);
2221 /* make us init after usbcore and before usb
2222 * gadget and host-side drivers start to register
2224 subsys_initcall(musb_init);
2226 static void __exit musb_cleanup(void)
2228 platform_driver_unregister(&musb_driver);
2230 module_exit(musb_cleanup);