2 * MUSB OTG driver core code
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - <asm/arch/hdrc_cnf.h> for SOC or family details
86 * - platform_device for addressing, irq, and platform_data
87 * - platform_data is mostly for board-specific informarion
89 * Most of the conditional compilation will (someday) vanish.
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/platform_device.h>
100 #include <linux/io.h>
103 #include <asm/arch/hardware.h>
104 #include <asm/arch/memory.h>
105 #include <asm/mach-types.h>
108 #include "musb_core.h"
111 #ifdef CONFIG_ARCH_DAVINCI
118 unsigned debug = MUSB_DEBUG;
119 module_param(debug, uint, 0);
120 MODULE_PARM_DESC(debug, "initial debug message level");
122 #define MUSB_VERSION_SUFFIX "/dbg"
125 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
126 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
128 #define MUSB_VERSION_BASE "6.0"
130 #ifndef MUSB_VERSION_SUFFIX
131 #define MUSB_VERSION_SUFFIX ""
133 #define MUSB_VERSION MUSB_VERSION_BASE MUSB_VERSION_SUFFIX
135 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
137 const char musb_driver_name[] = "musb_hdrc";
139 MODULE_DESCRIPTION(DRIVER_INFO);
140 MODULE_AUTHOR(DRIVER_AUTHOR);
141 MODULE_LICENSE("GPL");
144 /*-------------------------------------------------------------------------*/
146 static inline struct musb *dev_to_musb(struct device *dev)
148 #ifdef CONFIG_USB_MUSB_HDRC_HCD
149 /* usbcore insists dev->driver_data is a "struct hcd *" */
150 return hcd_to_musb(dev_get_drvdata(dev));
152 return dev_get_drvdata(dev);
156 /*-------------------------------------------------------------------------*/
158 #ifndef CONFIG_USB_TUSB6010
160 * Load an endpoint's FIFO
162 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
164 void __iomem *fifo = hw_ep->fifo;
168 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
169 'T', hw_ep->epnum, fifo, len, src);
171 /* we can't assume unaligned reads work */
172 if (likely((0x01 & (unsigned long) src) == 0)) {
175 /* best case is 32bit-aligned source address */
176 if ((0x02 & (unsigned long) src) == 0) {
178 writesl(fifo, src + index, len >> 2);
179 index += len & ~0x03;
182 musb_writew(fifo, 0, *(u16 *)&src[index]);
187 writesw(fifo, src + index, len >> 1);
188 index += len & ~0x01;
192 musb_writeb(fifo, 0, src[index]);
195 writesb(fifo, src, len);
200 * Unload an endpoint's FIFO
202 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
204 void __iomem *fifo = hw_ep->fifo;
206 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
207 'R', hw_ep->epnum, fifo, len, dst);
209 /* we can't assume unaligned writes work */
210 if (likely((0x01 & (unsigned long) dst) == 0)) {
213 /* best case is 32bit-aligned destination address */
214 if ((0x02 & (unsigned long) dst) == 0) {
216 readsl(fifo, dst, len >> 2);
220 *(u16 *)&dst[index] = musb_readw(fifo, 0);
225 readsw(fifo, dst, len >> 1);
230 dst[index] = musb_readb(fifo, 0);
233 readsb(fifo, dst, len);
237 #endif /* normal PIO */
240 /*-------------------------------------------------------------------------*/
242 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
243 static const u8 musb_test_packet[53] = {
244 /* implicit SYNC then DATA0 to start */
247 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
249 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
251 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
252 /* JJJJJJJKKKKKKK x8 */
253 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
255 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
256 /* JKKKKKKK x10, JK */
257 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
259 /* implicit CRC16 then EOP to end */
262 void musb_load_testpacket(struct musb *musb)
264 void __iomem *regs = musb->endpoints[0].regs;
266 musb_ep_select(musb->mregs, 0);
267 musb_write_fifo(musb->control_ep,
268 sizeof(musb_test_packet), musb_test_packet);
269 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
272 /*-------------------------------------------------------------------------*/
274 const char *otg_state_string(struct musb *musb)
276 switch (musb->xceiv.state) {
277 case OTG_STATE_A_IDLE: return "a_idle";
278 case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise";
279 case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon";
280 case OTG_STATE_A_HOST: return "a_host";
281 case OTG_STATE_A_SUSPEND: return "a_suspend";
282 case OTG_STATE_A_PERIPHERAL: return "a_peripheral";
283 case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall";
284 case OTG_STATE_A_VBUS_ERR: return "a_vbus_err";
285 case OTG_STATE_B_IDLE: return "b_idle";
286 case OTG_STATE_B_SRP_INIT: return "b_srp_init";
287 case OTG_STATE_B_PERIPHERAL: return "b_peripheral";
288 case OTG_STATE_B_WAIT_ACON: return "b_wait_acon";
289 case OTG_STATE_B_HOST: return "b_host";
290 default: return "UNDEFINED";
294 #ifdef CONFIG_USB_MUSB_OTG
297 * See also USB_OTG_1-3.pdf 6.6.5 Timers
298 * REVISIT: Are the other timers done in the hardware?
300 #define TB_ASE0_BRST 100 /* Min 3.125 ms */
303 * Handles OTG hnp timeouts, such as b_ase0_brst
305 void musb_otg_timer_func(unsigned long data)
307 struct musb *musb = (struct musb *)data;
310 spin_lock_irqsave(&musb->lock, flags);
311 switch (musb->xceiv.state) {
312 case OTG_STATE_B_WAIT_ACON:
313 DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n");
314 musb_g_disconnect(musb);
315 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
318 case OTG_STATE_A_WAIT_BCON:
319 DBG(1, "HNP: a_wait_bcon timeout; back to a_host\n");
323 DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb));
325 musb->ignore_disconnect = 0;
326 spin_unlock_irqrestore(&musb->lock, flags);
329 static DEFINE_TIMER(musb_otg_timer, musb_otg_timer_func, 0, 0);
332 * Stops the B-device HNP state. Caller must take care of locking.
334 void musb_hnp_stop(struct musb *musb)
336 struct usb_hcd *hcd = musb_to_hcd(musb);
337 void __iomem *mbase = musb->mregs;
340 switch (musb->xceiv.state) {
341 case OTG_STATE_A_PERIPHERAL:
342 case OTG_STATE_A_WAIT_VFALL:
343 case OTG_STATE_A_WAIT_BCON:
344 DBG(1, "HNP: Switching back to A-host\n");
345 musb_g_disconnect(musb);
346 musb->xceiv.state = OTG_STATE_A_IDLE;
350 case OTG_STATE_B_HOST:
351 DBG(1, "HNP: Disabling HR\n");
352 hcd->self.is_b_host = 0;
353 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
355 reg = musb_readb(mbase, MUSB_POWER);
356 reg |= MUSB_POWER_SUSPENDM;
357 musb_writeb(mbase, MUSB_POWER, reg);
358 /* REVISIT: Start SESSION_REQUEST here? */
361 DBG(1, "HNP: Stopping in unknown state %s\n",
362 otg_state_string(musb));
366 * When returning to A state after HNP, avoid hub_port_rebounce(),
367 * which cause occasional OPT A "Did not receive reset after connect"
370 musb->port1_status &=
371 ~(1 << USB_PORT_FEAT_C_CONNECTION);
377 * Interrupt Service Routine to record USB "global" interrupts.
378 * Since these do not happen often and signify things of
379 * paramount importance, it seems OK to check them individually;
380 * the order of the tests is specified in the manual
382 * @param musb instance pointer
383 * @param int_usb register contents
388 #define STAGE0_MASK (MUSB_INTR_RESUME | MUSB_INTR_SESSREQ \
389 | MUSB_INTR_VBUSERROR | MUSB_INTR_CONNECT \
392 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
395 irqreturn_t handled = IRQ_NONE;
396 void __iomem *mbase = musb->mregs;
398 DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
401 /* in host mode, the peripheral may issue remote wakeup.
402 * in peripheral mode, the host may resume the link.
403 * spurious RESUME irqs happen too, paired with SUSPEND.
405 if (int_usb & MUSB_INTR_RESUME) {
406 handled = IRQ_HANDLED;
407 DBG(3, "RESUME (%s)\n", otg_state_string(musb));
409 if (devctl & MUSB_DEVCTL_HM) {
410 #ifdef CONFIG_USB_MUSB_HDRC_HCD
411 switch (musb->xceiv.state) {
412 case OTG_STATE_A_SUSPEND:
413 /* remote wakeup? later, GetPortStatus
414 * will stop RESUME signaling
417 if (power & MUSB_POWER_SUSPENDM) {
419 musb->int_usb &= ~MUSB_INTR_SUSPEND;
420 DBG(2, "Spurious SUSPENDM\n");
424 power &= ~MUSB_POWER_SUSPENDM;
425 musb_writeb(mbase, MUSB_POWER,
426 power | MUSB_POWER_RESUME);
428 musb->port1_status |=
429 (USB_PORT_STAT_C_SUSPEND << 16)
430 | MUSB_PORT_STAT_RESUME;
431 musb->rh_timer = jiffies
432 + msecs_to_jiffies(20);
434 musb->xceiv.state = OTG_STATE_A_HOST;
436 usb_hcd_resume_root_hub(musb_to_hcd(musb));
438 case OTG_STATE_B_WAIT_ACON:
439 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
444 WARN("bogus %s RESUME (%s)\n",
446 otg_state_string(musb));
450 switch (musb->xceiv.state) {
451 #ifdef CONFIG_USB_MUSB_HDRC_HCD
452 case OTG_STATE_A_SUSPEND:
453 /* possibly DISCONNECT is upcoming */
454 musb->xceiv.state = OTG_STATE_A_HOST;
455 usb_hcd_resume_root_hub(musb_to_hcd(musb));
458 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
459 case OTG_STATE_B_WAIT_ACON:
460 case OTG_STATE_B_PERIPHERAL:
461 /* disconnect while suspended? we may
462 * not get a disconnect irq...
464 if ((devctl & MUSB_DEVCTL_VBUS)
465 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
467 musb->int_usb |= MUSB_INTR_DISCONNECT;
468 musb->int_usb &= ~MUSB_INTR_SUSPEND;
473 case OTG_STATE_B_IDLE:
474 musb->int_usb &= ~MUSB_INTR_SUSPEND;
478 WARN("bogus %s RESUME (%s)\n",
480 otg_state_string(musb));
485 #ifdef CONFIG_USB_MUSB_HDRC_HCD
486 /* see manual for the order of the tests */
487 if (int_usb & MUSB_INTR_SESSREQ) {
488 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb));
490 /* IRQ arrives from ID pin sense or (later, if VBUS power
491 * is removed) SRP. responses are time critical:
492 * - turn on VBUS (with silicon-specific mechanism)
493 * - go through A_WAIT_VRISE
494 * - ... to A_WAIT_BCON.
495 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
497 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
498 musb->ep0_stage = MUSB_EP0_START;
499 musb->xceiv.state = OTG_STATE_A_IDLE;
501 musb_set_vbus(musb, 1);
503 handled = IRQ_HANDLED;
506 if (int_usb & MUSB_INTR_VBUSERROR) {
509 /* During connection as an A-Device, we may see a short
510 * current spikes causing voltage drop, because of cable
511 * and peripheral capacitance combined with vbus draw.
512 * (So: less common with truly self-powered devices, where
513 * vbus doesn't act like a power supply.)
515 * Such spikes are short; usually less than ~500 usec, max
516 * of ~2 msec. That is, they're not sustained overcurrent
517 * errors, though they're reported using VBUSERROR irqs.
519 * Workarounds: (a) hardware: use self powered devices.
520 * (b) software: ignore non-repeated VBUS errors.
522 * REVISIT: do delays from lots of DEBUG_KERNEL checks
523 * make trouble here, keeping VBUS < 4.4V ?
525 switch (musb->xceiv.state) {
526 case OTG_STATE_A_HOST:
527 /* recovery is dicey once we've gotten past the
528 * initial stages of enumeration, but if VBUS
529 * stayed ok at the other end of the link, and
530 * another reset is due (at least for high speed,
531 * to redo the chirp etc), it might work OK...
533 case OTG_STATE_A_WAIT_BCON:
534 case OTG_STATE_A_WAIT_VRISE:
535 if (musb->vbuserr_retry) {
536 musb->vbuserr_retry--;
538 devctl |= MUSB_DEVCTL_SESSION;
539 musb_writeb(mbase, MUSB_DEVCTL, devctl);
541 musb->port1_status |=
542 (1 << USB_PORT_FEAT_OVER_CURRENT)
543 | (1 << USB_PORT_FEAT_C_OVER_CURRENT);
550 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
551 otg_state_string(musb),
554 switch (devctl & MUSB_DEVCTL_VBUS) {
555 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
556 s = "<SessEnd"; break;
557 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
558 s = "<AValid"; break;
559 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
560 s = "<VBusValid"; break;
561 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
565 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
568 /* go through A_WAIT_VFALL then start a new session */
570 musb_set_vbus(musb, 0);
571 handled = IRQ_HANDLED;
574 if (int_usb & MUSB_INTR_CONNECT) {
575 struct usb_hcd *hcd = musb_to_hcd(musb);
577 handled = IRQ_HANDLED;
579 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
581 musb->ep0_stage = MUSB_EP0_START;
583 #ifdef CONFIG_USB_MUSB_OTG
584 /* flush endpoints when transitioning from Device Mode */
585 if (is_peripheral_active(musb)) {
586 /* REVISIT HNP; just force disconnect */
588 musb_writew(mbase, MUSB_INTRTXE, musb->epmask);
589 musb_writew(mbase, MUSB_INTRRXE, musb->epmask & 0xfffe);
590 musb_writeb(mbase, MUSB_INTRUSBE, 0xf7);
592 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
593 |USB_PORT_STAT_HIGH_SPEED
594 |USB_PORT_STAT_ENABLE
596 musb->port1_status |= USB_PORT_STAT_CONNECTION
597 |(USB_PORT_STAT_C_CONNECTION << 16);
599 /* high vs full speed is just a guess until after reset */
600 if (devctl & MUSB_DEVCTL_LSDEV)
601 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
604 usb_hcd_poll_rh_status(hcd);
606 usb_hcd_resume_root_hub(hcd);
610 /* indicate new connection to OTG machine */
611 switch (musb->xceiv.state) {
612 case OTG_STATE_B_PERIPHERAL:
613 if (int_usb & MUSB_INTR_SUSPEND) {
614 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n");
615 musb->xceiv.state = OTG_STATE_B_HOST;
616 hcd->self.is_b_host = 1;
617 int_usb &= ~MUSB_INTR_SUSPEND;
619 DBG(1, "CONNECT as b_peripheral???\n");
621 case OTG_STATE_B_WAIT_ACON:
622 DBG(1, "HNP: Waiting to switch to b_host state\n");
623 musb->xceiv.state = OTG_STATE_B_HOST;
624 hcd->self.is_b_host = 1;
627 if ((devctl & MUSB_DEVCTL_VBUS)
628 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
629 musb->xceiv.state = OTG_STATE_A_HOST;
630 hcd->self.is_b_host = 0;
634 DBG(1, "CONNECT (%s) devctl %02x\n",
635 otg_state_string(musb), devctl);
637 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
639 /* mentor saves a bit: bus reset and babble share the same irq.
640 * only host sees babble; only peripheral sees bus reset.
642 if (int_usb & MUSB_INTR_RESET) {
643 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
645 * Looks like non-HS BABBLE can be ignored, but
646 * HS BABBLE is an error condition. For HS the solution
647 * is to avoid babble in the first place and fix what
648 * caused BABBLE. When HS BABBLE happens we can only
651 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
652 DBG(1, "BABBLE devctl: %02x\n", devctl);
654 ERR("Stopping host session -- babble\n");
655 musb_writeb(mbase, MUSB_DEVCTL, 0);
657 } else if (is_peripheral_capable()) {
658 DBG(1, "BUS RESET as %s\n", otg_state_string(musb));
659 switch (musb->xceiv.state) {
660 #ifdef CONFIG_USB_OTG
661 case OTG_STATE_A_SUSPEND:
662 musb->ignore_disconnect = 0;
665 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
666 DBG(1, "HNP: Setting timer as %s\n",
667 otg_state_string(musb));
668 musb_otg_timer.data = (unsigned long)musb;
669 mod_timer(&musb_otg_timer, jiffies
670 + msecs_to_jiffies(100));
672 case OTG_STATE_A_PERIPHERAL:
675 case OTG_STATE_B_WAIT_ACON:
676 DBG(1, "HNP: RESET (%s), back to b_peripheral\n",
677 otg_state_string(musb));
678 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
682 case OTG_STATE_B_IDLE:
683 musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
685 case OTG_STATE_B_PERIPHERAL:
689 DBG(1, "Unhandled BUS RESET as %s\n",
690 otg_state_string(musb));
694 handled = IRQ_HANDLED;
696 schedule_work(&musb->irq_work);
702 * Interrupt Service Routine to record USB "global" interrupts.
703 * Since these do not happen often and signify things of
704 * paramount importance, it seems OK to check them individually;
705 * the order of the tests is specified in the manual
707 * @param musb instance pointer
708 * @param int_usb register contents
712 static irqreturn_t musb_stage2_irq(struct musb *musb, u8 int_usb,
715 irqreturn_t handled = IRQ_NONE;
718 /* REVISIT ... this would be for multiplexing periodic endpoints, or
719 * supporting transfer phasing to prevent exceeding ISO bandwidth
720 * limits of a given frame or microframe.
722 * It's not needed for peripheral side, which dedicates endpoints;
723 * though it _might_ use SOF irqs for other purposes.
725 * And it's not currently needed for host side, which also dedicates
726 * endpoints, relies on TX/RX interval registers, and isn't claimed
727 * to support ISO transfers yet.
729 if (int_usb & MUSB_INTR_SOF) {
730 void __iomem *mbase = musb->mregs;
731 struct musb_hw_ep *ep;
735 DBG(6, "START_OF_FRAME\n");
736 handled = IRQ_HANDLED;
738 /* start any periodic Tx transfers waiting for current frame */
739 frame = musb_readw(mbase, MUSB_FRAME);
740 ep = musb->endpoints;
741 for (epnum = 1; (epnum < musb->nr_endpoints)
742 && (musb->epmask >= (1 << epnum));
745 * FIXME handle framecounter wraps (12 bits)
746 * eliminate duplicated StartUrb logic
748 if (ep->dwWaitFrame >= frame) {
750 printk("SOF --> periodic TX%s on %d\n",
751 ep->tx_channel ? " DMA" : "",
754 musb_h_tx_start(musb, epnum);
756 cppi_hostdma_start(musb, epnum);
758 } /* end of for loop */
762 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
763 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
764 otg_state_string(musb),
765 MUSB_MODE(musb), devctl);
766 handled = IRQ_HANDLED;
768 switch (musb->xceiv.state) {
769 #ifdef CONFIG_USB_MUSB_HDRC_HCD
770 case OTG_STATE_A_HOST:
771 case OTG_STATE_A_SUSPEND:
772 musb_root_disconnect(musb);
773 if (musb->a_wait_bcon != 0)
774 musb_platform_try_idle(musb, jiffies
775 + msecs_to_jiffies(musb->a_wait_bcon));
778 #ifdef CONFIG_USB_MUSB_OTG
779 case OTG_STATE_B_HOST:
782 case OTG_STATE_A_PERIPHERAL:
784 musb_root_disconnect(musb);
786 case OTG_STATE_B_WAIT_ACON:
789 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
790 case OTG_STATE_B_PERIPHERAL:
791 case OTG_STATE_B_IDLE:
792 musb_g_disconnect(musb);
796 WARN("unhandled DISCONNECT transition (%s)\n",
797 otg_state_string(musb));
801 schedule_work(&musb->irq_work);
804 if (int_usb & MUSB_INTR_SUSPEND) {
805 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
806 otg_state_string(musb), devctl, power);
807 handled = IRQ_HANDLED;
809 switch (musb->xceiv.state) {
810 #ifdef CONFIG_USB_MUSB_OTG
811 case OTG_STATE_A_PERIPHERAL:
813 * We cannot stop HNP here, devctl BDEVICE might be
818 case OTG_STATE_B_PERIPHERAL:
819 musb_g_suspend(musb);
820 musb->is_active = is_otg_enabled(musb)
821 && musb->xceiv.gadget->b_hnp_enable;
822 if (musb->is_active) {
823 #ifdef CONFIG_USB_MUSB_OTG
824 musb->xceiv.state = OTG_STATE_B_WAIT_ACON;
825 DBG(1, "HNP: Setting timer for b_ase0_brst\n");
826 musb_otg_timer.data = (unsigned long)musb;
827 mod_timer(&musb_otg_timer, jiffies
828 + msecs_to_jiffies(TB_ASE0_BRST));
832 case OTG_STATE_A_WAIT_BCON:
833 if (musb->a_wait_bcon != 0)
834 musb_platform_try_idle(musb, jiffies
835 + msecs_to_jiffies(musb->a_wait_bcon));
837 case OTG_STATE_A_HOST:
838 musb->xceiv.state = OTG_STATE_A_SUSPEND;
839 musb->is_active = is_otg_enabled(musb)
840 && musb->xceiv.host->b_hnp_enable;
842 case OTG_STATE_B_HOST:
843 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
844 DBG(1, "REVISIT: SUSPEND as B_HOST\n");
847 /* "should not happen" */
851 schedule_work(&musb->irq_work);
858 /*-------------------------------------------------------------------------*/
861 * Program the HDRC to start (enable interrupts, dma, etc.).
863 void musb_start(struct musb *musb)
865 void __iomem *regs = musb->mregs;
866 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
868 DBG(2, "<== devctl %02x\n", devctl);
870 /* Set INT enable registers, enable interrupts */
871 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
872 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
873 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
875 musb_writeb(regs, MUSB_TESTMODE, 0);
877 /* put into basic highspeed mode and start session */
878 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
879 | MUSB_POWER_SOFTCONN
881 /* ENSUSPEND wedges tusb */
882 /* | MUSB_POWER_ENSUSPEND */
886 devctl = musb_readb(regs, MUSB_DEVCTL);
887 devctl &= ~MUSB_DEVCTL_SESSION;
889 if (is_otg_enabled(musb)) {
890 /* session started after:
891 * (a) ID-grounded irq, host mode;
892 * (b) vbus present/connect IRQ, peripheral mode;
893 * (c) peripheral initiates, using SRP
895 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
898 devctl |= MUSB_DEVCTL_SESSION;
900 } else if (is_host_enabled(musb)) {
901 /* assume ID pin is hard-wired to ground */
902 devctl |= MUSB_DEVCTL_SESSION;
904 } else /* peripheral is enabled */ {
905 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
908 musb_platform_enable(musb);
909 musb_writeb(regs, MUSB_DEVCTL, devctl);
913 static void musb_generic_disable(struct musb *musb)
915 void __iomem *mbase = musb->mregs;
918 /* disable interrupts */
919 musb_writeb(mbase, MUSB_INTRUSBE, 0);
920 musb_writew(mbase, MUSB_INTRTXE, 0);
921 musb_writew(mbase, MUSB_INTRRXE, 0);
924 musb_writeb(mbase, MUSB_DEVCTL, 0);
926 /* flush pending interrupts */
927 temp = musb_readb(mbase, MUSB_INTRUSB);
928 temp = musb_readw(mbase, MUSB_INTRTX);
929 temp = musb_readw(mbase, MUSB_INTRRX);
934 * Make the HDRC stop (disable interrupts, etc.);
935 * reversible by musb_start
936 * called on gadget driver unregister
937 * with controller locked, irqs blocked
938 * acts as a NOP unless some role activated the hardware
940 void musb_stop(struct musb *musb)
942 /* stop IRQs, timers, ... */
943 musb_platform_disable(musb);
944 musb_generic_disable(musb);
945 DBG(3, "HDRC disabled\n");
948 * - mark host and/or peripheral drivers unusable/inactive
949 * - disable DMA (and enable it in HdrcStart)
950 * - make sure we can musb_start() after musb_stop(); with
951 * OTG mode, gadget driver module rmmod/modprobe cycles that
954 musb_platform_try_idle(musb, 0);
957 static void musb_shutdown(struct platform_device *pdev)
959 struct musb *musb = dev_to_musb(&pdev->dev);
962 spin_lock_irqsave(&musb->lock, flags);
963 musb_platform_disable(musb);
964 musb_generic_disable(musb);
966 clk_put(musb->clock);
969 spin_unlock_irqrestore(&musb->lock, flags);
971 /* FIXME power down */
975 /*-------------------------------------------------------------------------*/
978 * The silicon either has hard-wired endpoint configurations, or else
979 * "dynamic fifo" sizing. The driver has support for both, though at this
980 * writing only the dynamic sizing is very well tested. We use normal
981 * idioms to so both modes are compile-tested, but dead code elimination
982 * leaves only the relevant one in the object file.
984 * We don't currently use dynamic fifo setup capability to do anything
985 * more than selecting one of a bunch of predefined configurations.
987 #ifdef MUSB_C_DYNFIFO_DEF
988 #define can_dynfifo() 1
990 #define can_dynfifo() 0
993 #if defined(CONFIG_USB_TUSB6010) || \
994 defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
995 static ushort __initdata fifo_mode = 4;
997 static ushort __initdata fifo_mode = 2;
1000 /* "modprobe ... fifo_mode=1" etc */
1001 module_param(fifo_mode, ushort, 0);
1002 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1005 #define DYN_FIFO_SIZE (1<<(MUSB_C_RAM_BITS+2))
1007 enum fifo_style { FIFO_RXTX, FIFO_TX, FIFO_RX } __attribute__ ((packed));
1008 enum buf_mode { BUF_SINGLE, BUF_DOUBLE } __attribute__ ((packed));
1012 enum fifo_style style;
1018 * tables defining fifo_mode values. define more if you like.
1019 * for host side, make sure both halves of ep1 are set up.
1022 /* mode 0 - fits in 2KB */
1023 static struct fifo_cfg __initdata mode_0_cfg[] = {
1024 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1025 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1026 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1027 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1028 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1031 /* mode 1 - fits in 4KB */
1032 static struct fifo_cfg __initdata mode_1_cfg[] = {
1033 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1034 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1035 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1036 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1037 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1040 /* mode 2 - fits in 4KB */
1041 static struct fifo_cfg __initdata mode_2_cfg[] = {
1042 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1043 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1044 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1045 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1046 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1047 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1050 /* mode 3 - fits in 4KB */
1051 static struct fifo_cfg __initdata mode_3_cfg[] = {
1052 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1053 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1054 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1055 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1056 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1057 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1060 /* mode 4 - fits in 16KB */
1061 static struct fifo_cfg __initdata mode_4_cfg[] = {
1062 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1063 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1064 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1065 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1066 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1067 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1068 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1069 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1070 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1071 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1072 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1073 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1074 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1075 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1076 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1077 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1078 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1079 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1080 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 512, },
1081 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 512, },
1082 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 512, },
1083 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 512, },
1084 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 512, },
1085 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 512, },
1086 { .hw_ep_num = 13, .style = FIFO_TX, .maxpacket = 512, },
1087 { .hw_ep_num = 13, .style = FIFO_RX, .maxpacket = 512, },
1088 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1089 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1094 * configure a fifo; for non-shared endpoints, this may be called
1095 * once for a tx fifo and once for an rx fifo.
1097 * returns negative errno or offset for next fifo.
1100 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1101 const struct fifo_cfg *cfg, u16 offset)
1103 void __iomem *mbase = musb->mregs;
1105 u16 maxpacket = cfg->maxpacket;
1106 u16 c_off = offset >> 3;
1109 /* expect hw_ep has already been zero-initialized */
1111 size = ffs(max(maxpacket, (u16) 8)) - 1;
1112 maxpacket = 1 << size;
1115 if (cfg->mode == BUF_DOUBLE) {
1116 if ((offset + (maxpacket << 1)) > DYN_FIFO_SIZE)
1118 c_size |= MUSB_FIFOSZ_DPB;
1120 if ((offset + maxpacket) > DYN_FIFO_SIZE)
1124 /* configure the FIFO */
1125 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1127 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1128 /* EP0 reserved endpoint for control, bidirectional;
1129 * EP1 reserved for bulk, two unidirection halves.
1131 if (hw_ep->epnum == 1)
1132 musb->bulk_ep = hw_ep;
1133 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1135 switch (cfg->style) {
1137 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
1138 musb_writew(mbase, MUSB_TXFIFOADD, c_off);
1139 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1140 hw_ep->max_packet_sz_tx = maxpacket;
1143 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
1144 musb_writew(mbase, MUSB_RXFIFOADD, c_off);
1145 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1146 hw_ep->max_packet_sz_rx = maxpacket;
1149 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
1150 musb_writew(mbase, MUSB_TXFIFOADD, c_off);
1151 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1152 hw_ep->max_packet_sz_rx = maxpacket;
1154 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
1155 musb_writew(mbase, MUSB_RXFIFOADD, c_off);
1156 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1157 hw_ep->max_packet_sz_tx = maxpacket;
1159 hw_ep->is_shared_fifo = true;
1163 /* NOTE rx and tx endpoint irqs aren't managed separately,
1164 * which happens to be ok
1166 musb->epmask |= (1 << hw_ep->epnum);
1168 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1171 static struct fifo_cfg __initdata ep0_cfg = {
1172 .style = FIFO_RXTX, .maxpacket = 64,
1175 static int __init ep_config_from_table(struct musb *musb)
1177 const struct fifo_cfg *cfg;
1180 struct musb_hw_ep *hw_ep = musb->endpoints;
1182 switch (fifo_mode) {
1188 n = ARRAY_SIZE(mode_0_cfg);
1192 n = ARRAY_SIZE(mode_1_cfg);
1196 n = ARRAY_SIZE(mode_2_cfg);
1200 n = ARRAY_SIZE(mode_3_cfg);
1204 n = ARRAY_SIZE(mode_4_cfg);
1208 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1209 musb_driver_name, fifo_mode);
1212 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1213 /* assert(offset > 0) */
1215 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1216 * be better than static MUSB_C_NUM_EPS and DYN_FIFO_SIZE...
1219 for (i = 0; i < n; i++) {
1220 u8 epn = cfg->hw_ep_num;
1222 if (epn >= MUSB_C_NUM_EPS) {
1223 pr_debug("%s: invalid ep %d\n",
1224 musb_driver_name, epn);
1227 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1229 pr_debug("%s: mem overrun, ep %d\n",
1230 musb_driver_name, epn);
1234 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1237 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1239 n + 1, MUSB_C_NUM_EPS * 2 - 1,
1240 offset, DYN_FIFO_SIZE);
1242 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1243 if (!musb->bulk_ep) {
1244 pr_debug("%s: missing bulk\n", musb_driver_name);
1254 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1255 * @param musb the controller
1257 static int __init ep_config_from_hw(struct musb *musb)
1260 struct musb_hw_ep *hw_ep;
1261 void *mbase = musb->mregs;
1263 DBG(2, "<== static silicon ep config\n");
1265 /* FIXME pick up ep0 maxpacket size */
1267 for (epnum = 1; epnum < MUSB_C_NUM_EPS; epnum++) {
1268 musb_ep_select(mbase, epnum);
1269 hw_ep = musb->endpoints + epnum;
1271 /* read from core using indexed model */
1272 reg = musb_readb(hw_ep->regs, 0x10 + MUSB_FIFOSIZE);
1274 /* 0's returned when no more endpoints */
1277 musb->nr_endpoints++;
1278 musb->epmask |= (1 << epnum);
1280 hw_ep->max_packet_sz_tx = 1 << (reg & 0x0f);
1282 /* shared TX/RX FIFO? */
1283 if ((reg & 0xf0) == 0xf0) {
1284 hw_ep->max_packet_sz_rx = hw_ep->max_packet_sz_tx;
1285 hw_ep->is_shared_fifo = true;
1288 hw_ep->max_packet_sz_rx = 1 << ((reg & 0xf0) >> 4);
1289 hw_ep->is_shared_fifo = false;
1292 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1294 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1295 /* pick an RX/TX endpoint for bulk */
1296 if (hw_ep->max_packet_sz_tx < 512
1297 || hw_ep->max_packet_sz_rx < 512)
1300 /* REVISIT: this algorithm is lazy, we should at least
1301 * try to pick a double buffered endpoint.
1305 musb->bulk_ep = hw_ep;
1309 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1310 if (!musb->bulk_ep) {
1311 pr_debug("%s: missing bulk\n", musb_driver_name);
1319 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1321 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1322 * configure endpoints, or take their config from silicon
1324 static int __init musb_core_init(u16 musb_type, struct musb *musb)
1331 u16 hwvers, rev_major, rev_minor;
1332 char aInfo[78], aRevision[32], aDate[12];
1333 void __iomem *mbase = musb->mregs;
1337 /* log core options (read using indexed model) */
1338 musb_ep_select(mbase, 0);
1339 reg = musb_readb(mbase, 0x10 + MUSB_CONFIGDATA);
1341 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1342 if (reg & MUSB_CONFIGDATA_DYNFIFO)
1343 strcat(aInfo, ", dyn FIFOs");
1344 if (reg & MUSB_CONFIGDATA_MPRXE) {
1345 strcat(aInfo, ", bulk combine");
1347 musb->bulk_combine = true;
1349 strcat(aInfo, " (X)"); /* no driver support */
1352 if (reg & MUSB_CONFIGDATA_MPTXE) {
1353 strcat(aInfo, ", bulk split");
1355 musb->bulk_split = true;
1357 strcat(aInfo, " (X)"); /* no driver support */
1360 if (reg & MUSB_CONFIGDATA_HBRXE) {
1361 strcat(aInfo, ", HB-ISO Rx");
1362 strcat(aInfo, " (X)"); /* no driver support */
1364 if (reg & MUSB_CONFIGDATA_HBTXE) {
1365 strcat(aInfo, ", HB-ISO Tx");
1366 strcat(aInfo, " (X)"); /* no driver support */
1368 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1369 strcat(aInfo, ", SoftConn");
1371 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1372 musb_driver_name, reg, aInfo);
1375 data = musb_readl(mbase, 0x404);
1376 sprintf(aDate, "%04d-%02x-%02x", (data & 0xffff),
1377 (data >> 16) & 0xff, (data >> 24) & 0xff);
1378 /* FIXME ID2 and ID3 are unused */
1379 data = musb_readl(mbase, 0x408);
1380 printk("ID2=%lx\n", (long unsigned)data);
1381 data = musb_readl(mbase, 0x40c);
1382 printk("ID3=%lx\n", (long unsigned)data);
1383 reg = musb_readb(mbase, 0x400);
1384 musb_type = ('M' == reg) ? MUSB_CONTROLLER_MHDRC : MUSB_CONTROLLER_HDRC;
1388 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1389 musb->is_multipoint = 1;
1392 musb->is_multipoint = 0;
1394 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1395 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1397 "%s: kernel must blacklist external hubs\n",
1403 /* log release info */
1404 hwvers = musb_readw(mbase, MUSB_HWVERS);
1405 rev_major = (hwvers >> 10) & 0x1f;
1406 rev_minor = hwvers & 0x3ff;
1407 snprintf(aRevision, 32, "%d.%d%s", rev_major,
1408 rev_minor, (hwvers & 0x8000) ? "RC" : "");
1409 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1410 musb_driver_name, type, aRevision, aDate);
1413 musb->endpoints[0].max_packet_sz_tx = MUSB_EP0_FIFOSIZE;
1414 musb->endpoints[0].max_packet_sz_rx = MUSB_EP0_FIFOSIZE;
1416 /* discover endpoint configuration */
1417 musb->nr_endpoints = 1;
1420 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1422 status = ep_config_from_table(musb);
1424 ERR("reconfigure software for Dynamic FIFOs\n");
1429 status = ep_config_from_hw(musb);
1431 ERR("reconfigure software for static FIFOs\n");
1439 /* finish init, and print endpoint config */
1440 for (i = 0; i < musb->nr_endpoints; i++) {
1441 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1443 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1444 #ifdef CONFIG_USB_TUSB6010
1445 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1446 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1447 hw_ep->fifo_sync_va =
1448 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1451 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1453 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1456 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1457 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1458 hw_ep->target_regs = MUSB_BUSCTL_OFFSET(i, 0) + mbase;
1459 hw_ep->rx_reinit = 1;
1460 hw_ep->tx_reinit = 1;
1463 if (hw_ep->max_packet_sz_tx) {
1465 "%s: hw_ep %d%s, %smax %d\n",
1466 musb_driver_name, i,
1467 hw_ep->is_shared_fifo ? "shared" : "tx",
1468 hw_ep->tx_double_buffered
1469 ? "doublebuffer, " : "",
1470 hw_ep->max_packet_sz_tx);
1472 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1474 "%s: hw_ep %d%s, %smax %d\n",
1475 musb_driver_name, i,
1477 hw_ep->rx_double_buffered
1478 ? "doublebuffer, " : "",
1479 hw_ep->max_packet_sz_rx);
1481 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1482 DBG(1, "hw_ep %d not configured\n", i);
1488 /*-------------------------------------------------------------------------*/
1490 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
1492 static irqreturn_t generic_interrupt(int irq, void *__hci)
1494 unsigned long flags;
1495 irqreturn_t retval = IRQ_NONE;
1496 struct musb *musb = __hci;
1498 spin_lock_irqsave(&musb->lock, flags);
1500 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1501 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1502 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1504 if (musb->int_usb || musb->int_tx || musb->int_rx)
1505 retval = musb_interrupt(musb);
1507 spin_unlock_irqrestore(&musb->lock, flags);
1509 /* REVISIT we sometimes get spurious IRQs on g_ep0
1512 if (retval != IRQ_HANDLED)
1513 DBG(5, "spurious?\n");
1519 #define generic_interrupt NULL
1523 * handle all the irqs defined by the HDRC core. for now we expect: other
1524 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1525 * will be assigned, and the irq will already have been acked.
1527 * called in irq context with spinlock held, irqs blocked
1529 irqreturn_t musb_interrupt(struct musb *musb)
1531 irqreturn_t retval = IRQ_NONE;
1536 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1537 power = musb_readb(musb->mregs, MUSB_POWER);
1539 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
1540 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1541 musb->int_usb, musb->int_tx, musb->int_rx);
1543 /* the core can interrupt us for multiple reasons; docs have
1544 * a generic interrupt flowchart to follow
1546 if (musb->int_usb & STAGE0_MASK)
1547 retval |= musb_stage0_irq(musb, musb->int_usb,
1550 /* "stage 1" is handling endpoint irqs */
1552 /* handle endpoint 0 first */
1553 if (musb->int_tx & 1) {
1554 if (devctl & MUSB_DEVCTL_HM)
1555 retval |= musb_h_ep0_irq(musb);
1557 retval |= musb_g_ep0_irq(musb);
1560 /* RX on endpoints 1-15 */
1561 reg = musb->int_rx >> 1;
1565 /* musb_ep_select(musb->mregs, ep_num); */
1566 /* REVISIT just retval = ep->rx_irq(...) */
1567 retval = IRQ_HANDLED;
1568 if (devctl & MUSB_DEVCTL_HM) {
1569 if (is_host_capable())
1570 musb_host_rx(musb, ep_num);
1572 if (is_peripheral_capable())
1573 musb_g_rx(musb, ep_num);
1581 /* TX on endpoints 1-15 */
1582 reg = musb->int_tx >> 1;
1586 /* musb_ep_select(musb->mregs, ep_num); */
1587 /* REVISIT just retval |= ep->tx_irq(...) */
1588 retval = IRQ_HANDLED;
1589 if (devctl & MUSB_DEVCTL_HM) {
1590 if (is_host_capable())
1591 musb_host_tx(musb, ep_num);
1593 if (is_peripheral_capable())
1594 musb_g_tx(musb, ep_num);
1601 /* finish handling "global" interrupts after handling fifos */
1603 retval |= musb_stage2_irq(musb,
1604 musb->int_usb, devctl, power);
1610 #ifndef CONFIG_MUSB_PIO_ONLY
1611 static int __initdata use_dma = 1;
1613 /* "modprobe ... use_dma=0" etc */
1614 module_param(use_dma, bool, 0);
1615 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1617 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1619 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1621 /* called with controller lock already held */
1624 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1625 if (!is_cppi_enabled()) {
1627 if (devctl & MUSB_DEVCTL_HM)
1628 musb_h_ep0_irq(musb);
1630 musb_g_ep0_irq(musb);
1634 /* endpoints 1..15 */
1636 if (devctl & MUSB_DEVCTL_HM) {
1637 if (is_host_capable())
1638 musb_host_tx(musb, epnum);
1640 if (is_peripheral_capable())
1641 musb_g_tx(musb, epnum);
1645 if (devctl & MUSB_DEVCTL_HM) {
1646 if (is_host_capable())
1647 musb_host_rx(musb, epnum);
1649 if (is_peripheral_capable())
1650 musb_g_rx(musb, epnum);
1660 /*-------------------------------------------------------------------------*/
1665 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1667 struct musb *musb = dev_to_musb(dev);
1668 unsigned long flags;
1671 spin_lock_irqsave(&musb->lock, flags);
1672 ret = sprintf(buf, "%s\n", otg_state_string(musb));
1673 spin_unlock_irqrestore(&musb->lock, flags);
1679 musb_mode_store(struct device *dev, struct device_attribute *attr,
1680 const char *buf, size_t n)
1682 struct musb *musb = dev_to_musb(dev);
1683 unsigned long flags;
1685 spin_lock_irqsave(&musb->lock, flags);
1686 if (!strncmp(buf, "host", 4))
1687 musb_platform_set_mode(musb, MUSB_HOST);
1688 if (!strncmp(buf, "peripheral", 10))
1689 musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1690 if (!strncmp(buf, "otg", 3))
1691 musb_platform_set_mode(musb, MUSB_OTG);
1692 spin_unlock_irqrestore(&musb->lock, flags);
1696 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1699 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1700 const char *buf, size_t n)
1702 struct musb *musb = dev_to_musb(dev);
1703 unsigned long flags;
1706 if (sscanf(buf, "%lu", &val) < 1) {
1707 printk(KERN_ERR "Invalid VBUS timeout ms value\n");
1711 spin_lock_irqsave(&musb->lock, flags);
1712 musb->a_wait_bcon = val;
1713 if (musb->xceiv.state == OTG_STATE_A_WAIT_BCON)
1714 musb->is_active = 0;
1715 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1716 spin_unlock_irqrestore(&musb->lock, flags);
1722 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1724 struct musb *musb = dev_to_musb(dev);
1725 unsigned long flags;
1729 spin_lock_irqsave(&musb->lock, flags);
1730 val = musb->a_wait_bcon;
1731 vbus = musb_platform_get_vbus_status(musb);
1732 spin_unlock_irqrestore(&musb->lock, flags);
1734 return sprintf(buf, "Vbus %s, timeout %lu\n",
1735 vbus ? "on" : "off", val);
1737 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1739 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1741 /* Gadget drivers can't know that a host is connected so they might want
1742 * to start SRP, but users can. This allows userspace to trigger SRP.
1745 musb_srp_store(struct device *dev, struct device_attribute *attr,
1746 const char *buf, size_t n)
1748 struct musb *musb = dev_to_musb(dev);
1751 if (sscanf(buf, "%hu", &srp) != 1
1753 printk(KERN_ERR "SRP: Value must be 1\n");
1758 musb_g_wakeup(musb);
1762 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1764 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
1768 /* Only used to provide driver mode change events */
1769 static void musb_irq_work(struct work_struct *data)
1771 struct musb *musb = container_of(data, struct musb, irq_work);
1772 static int old_state;
1774 if (musb->xceiv.state != old_state) {
1775 old_state = musb->xceiv.state;
1776 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1780 /* --------------------------------------------------------------------------
1784 static struct musb *__init
1785 allocate_instance(struct device *dev, void __iomem *mbase)
1788 struct musb_hw_ep *ep;
1790 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1791 struct usb_hcd *hcd;
1793 hcd = usb_create_hcd(&musb_hc_driver, dev, dev->bus_id);
1796 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1798 musb = hcd_to_musb(hcd);
1799 INIT_LIST_HEAD(&musb->control);
1800 INIT_LIST_HEAD(&musb->in_bulk);
1801 INIT_LIST_HEAD(&musb->out_bulk);
1803 hcd->uses_new_polling = 1;
1805 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1807 musb = kzalloc(sizeof *musb, GFP_KERNEL);
1810 dev_set_drvdata(dev, musb);
1814 musb->mregs = mbase;
1815 musb->ctrl_base = mbase;
1816 musb->nIrq = -ENODEV;
1817 for (epnum = 0, ep = musb->endpoints;
1818 epnum < MUSB_C_NUM_EPS;
1825 #ifdef CONFIG_USB_MUSB_OTG
1826 otg_set_transceiver(&musb->xceiv);
1828 musb->controller = dev;
1832 static void musb_free(struct musb *musb)
1834 /* this has multiple entry modes. it handles fault cleanup after
1835 * probe(), where things may be partially set up, as well as rmmod
1836 * cleanup after everything's been de-activated.
1840 device_remove_file(musb->controller, &dev_attr_mode);
1841 device_remove_file(musb->controller, &dev_attr_vbus);
1842 #ifdef CONFIG_USB_MUSB_OTG
1843 device_remove_file(musb->controller, &dev_attr_srp);
1847 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1848 musb_gadget_cleanup(musb);
1851 if (musb->nIrq >= 0) {
1852 disable_irq_wake(musb->nIrq);
1853 free_irq(musb->nIrq, musb);
1855 if (is_dma_capable() && musb->dma_controller) {
1856 struct dma_controller *c = musb->dma_controller;
1859 dma_controller_destroy(c);
1862 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1863 musb_platform_exit(musb);
1864 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1867 clk_disable(musb->clock);
1868 clk_put(musb->clock);
1871 #ifdef CONFIG_USB_MUSB_OTG
1872 put_device(musb->xceiv.dev);
1875 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1876 usb_put_hcd(musb_to_hcd(musb));
1883 * Perform generic per-controller initialization.
1885 * @pDevice: the controller (already clocked, etc)
1887 * @mregs: virtual address of controller registers,
1888 * not yet corrected for platform-specific offsets
1891 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1895 struct musb_hdrc_platform_data *plat = dev->platform_data;
1897 /* The driver might handle more features than the board; OK.
1898 * Fail when the board needs a feature that's not enabled.
1901 dev_dbg(dev, "no platform_data?\n");
1904 switch (plat->mode) {
1906 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1911 case MUSB_PERIPHERAL:
1912 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1918 #ifdef CONFIG_USB_MUSB_OTG
1924 dev_err(dev, "incompatible Kconfig role setting\n");
1929 musb = allocate_instance(dev, ctrl);
1933 spin_lock_init(&musb->lock);
1934 musb->board_mode = plat->mode;
1935 musb->board_set_power = plat->set_power;
1936 musb->set_clock = plat->set_clock;
1937 musb->min_power = plat->min_power;
1939 /* Clock usage is chip-specific ... functional clock (DaVinci,
1940 * OMAP2430), or PHY ref (some TUSB6010 boards). All this core
1941 * code does is make sure a clock handle is available; platform
1942 * code manages it during start/stop and suspend/resume.
1945 musb->clock = clk_get(dev, plat->clock);
1946 if (IS_ERR(musb->clock)) {
1947 status = PTR_ERR(musb->clock);
1953 /* assume vbus is off */
1955 /* platform adjusts musb->mregs and musb->isr if needed,
1956 * and activates clocks
1958 musb->isr = generic_interrupt;
1959 status = musb_platform_init(musb);
1968 #ifndef CONFIG_MUSB_PIO_ONLY
1969 if (use_dma && dev->dma_mask) {
1970 struct dma_controller *c;
1972 c = dma_controller_create(musb, musb->mregs);
1973 musb->dma_controller = c;
1978 /* ideally this would be abstracted in platform setup */
1979 if (!is_dma_capable() || !musb->dma_controller)
1980 dev->dma_mask = NULL;
1982 /* be sure interrupts are disabled before connecting ISR */
1983 musb_platform_disable(musb);
1984 musb_generic_disable(musb);
1986 /* setup musb parts of the core (especially endpoints) */
1987 status = musb_core_init(plat->multipoint
1988 ? MUSB_CONTROLLER_MHDRC
1989 : MUSB_CONTROLLER_HDRC, musb);
1993 /* Init IRQ workqueue before request_irq */
1994 INIT_WORK(&musb->irq_work, musb_irq_work);
1996 /* attach to the IRQ */
1997 if (request_irq(nIrq, musb->isr, 0, dev->bus_id, musb)) {
1998 dev_err(dev, "request_irq %d failed!\n", nIrq);
2003 /* FIXME this handles wakeup irqs wrong */
2004 if (enable_irq_wake(nIrq) == 0)
2005 device_init_wakeup(dev, 1);
2007 pr_info("%s: USB %s mode controller at %p using %s, IRQ %d\n",
2010 switch (musb->board_mode) {
2011 case MUSB_HOST: s = "Host"; break;
2012 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2013 default: s = "OTG"; break;
2016 (is_dma_capable() && musb->dma_controller)
2020 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2021 /* host side needs more setup, except for no-host modes */
2022 if (musb->board_mode != MUSB_PERIPHERAL) {
2023 struct usb_hcd *hcd = musb_to_hcd(musb);
2025 if (musb->board_mode == MUSB_OTG)
2026 hcd->self.otg_port = 1;
2027 musb->xceiv.host = &hcd->self;
2028 hcd->power_budget = 2 * (plat->power ? : 250);
2030 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
2032 /* For the host-only role, we can activate right away.
2033 * (We expect the ID pin to be forcibly grounded!!)
2034 * Otherwise, wait till the gadget driver hooks up.
2036 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2037 MUSB_HST_MODE(musb);
2038 musb->xceiv.default_a = 1;
2039 musb->xceiv.state = OTG_STATE_A_IDLE;
2041 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2043 DBG(1, "%s mode, status %d, devctl %02x %c\n",
2045 musb_readb(musb->mregs, MUSB_DEVCTL),
2046 (musb_readb(musb->mregs, MUSB_DEVCTL)
2047 & MUSB_DEVCTL_BDEVICE
2050 } else /* peripheral is enabled */ {
2051 MUSB_DEV_MODE(musb);
2052 musb->xceiv.default_a = 0;
2053 musb->xceiv.state = OTG_STATE_B_IDLE;
2055 status = musb_gadget_setup(musb);
2057 DBG(1, "%s mode, status %d, dev%02x\n",
2058 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2060 musb_readb(musb->mregs, MUSB_DEVCTL));
2065 musb_debug_create("driver/musb_hdrc", musb);
2069 clk_put(musb->clock);
2070 device_init_wakeup(dev, 0);
2076 status = device_create_file(dev, &dev_attr_mode);
2077 status = device_create_file(dev, &dev_attr_vbus);
2078 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2079 status = device_create_file(dev, &dev_attr_srp);
2080 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
2087 musb_platform_exit(musb);
2091 /*-------------------------------------------------------------------------*/
2093 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2094 * bridge to a platform device; this driver then suffices.
2097 #ifndef CONFIG_MUSB_PIO_ONLY
2098 static u64 *orig_dma_mask;
2101 static int __init musb_probe(struct platform_device *pdev)
2103 struct device *dev = &pdev->dev;
2104 int irq = platform_get_irq(pdev, 0);
2105 struct resource *iomem;
2108 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2109 if (!iomem || irq == 0)
2112 base = ioremap(iomem->start, iomem->end - iomem->start + 1);
2114 dev_err(dev, "ioremap failed\n");
2118 #ifndef CONFIG_MUSB_PIO_ONLY
2119 /* clobbered by use_dma=n */
2120 orig_dma_mask = dev->dma_mask;
2122 return musb_init_controller(dev, irq, base);
2125 static int __devexit musb_remove(struct platform_device *pdev)
2127 struct musb *musb = dev_to_musb(&pdev->dev);
2128 void __iomem *ctrl_base = musb->ctrl_base;
2130 /* this gets called on rmmod.
2131 * - Host mode: host may still be active
2132 * - Peripheral mode: peripheral is deactivated (or never-activated)
2133 * - OTG mode: both roles are deactivated (or never-activated)
2135 musb_shutdown(pdev);
2136 musb_debug_delete("driver/musb_hdrc", musb);
2137 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2138 if (musb->board_mode == MUSB_HOST)
2139 usb_remove_hcd(musb_to_hcd(musb));
2143 device_init_wakeup(&pdev->dev, 0);
2144 #ifndef CONFIG_MUSB_PIO_ONLY
2145 pdev->dev.dma_mask = orig_dma_mask;
2152 static int musb_suspend(struct platform_device *pdev, pm_message_t message)
2154 unsigned long flags;
2155 struct musb *musb = dev_to_musb(&pdev->dev);
2160 spin_lock_irqsave(&musb->lock, flags);
2162 if (is_peripheral_active(musb)) {
2163 /* FIXME force disconnect unless we know USB will wake
2164 * the system up quickly enough to respond ...
2166 } else if (is_host_active(musb)) {
2167 /* we know all the children are suspended; sometimes
2168 * they will even be wakeup-enabled.
2172 if (musb->set_clock)
2173 musb->set_clock(musb->clock, 0);
2175 clk_disable(musb->clock);
2176 spin_unlock_irqrestore(&musb->lock, flags);
2180 static int musb_resume(struct platform_device *pdev)
2182 unsigned long flags;
2183 struct musb *musb = dev_to_musb(&pdev->dev);
2188 spin_lock_irqsave(&musb->lock, flags);
2190 if (musb->set_clock)
2191 musb->set_clock(musb->clock, 1);
2193 clk_enable(musb->clock);
2195 /* for static cmos like DaVinci, register values were preserved
2196 * unless for some reason the whole soc powered down and we're
2197 * not treating that as a whole-system restart (e.g. swsusp)
2199 spin_unlock_irqrestore(&musb->lock, flags);
2204 #define musb_suspend NULL
2205 #define musb_resume NULL
2208 static struct platform_driver musb_driver = {
2210 .name = (char *)musb_driver_name,
2211 .bus = &platform_bus_type,
2212 .owner = THIS_MODULE,
2214 .remove = __devexit_p(musb_remove),
2215 .shutdown = musb_shutdown,
2216 .suspend = musb_suspend,
2217 .resume = musb_resume,
2220 /*-------------------------------------------------------------------------*/
2222 static int __init musb_init(void)
2224 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2229 pr_info("%s: version " MUSB_VERSION ", "
2230 #ifdef CONFIG_MUSB_PIO_ONLY
2232 #elif defined(CONFIG_USB_TI_CPPI_DMA)
2234 #elif defined(CONFIG_USB_INVENTRA_DMA)
2236 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
2242 #ifdef CONFIG_USB_MUSB_OTG
2243 "otg (peripheral+host)"
2244 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
2246 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2250 musb_driver_name, debug);
2251 return platform_driver_probe(&musb_driver, musb_probe);
2254 /* make us init after usbcore and before usb
2255 * gadget and host-side drivers start to register
2257 subsys_initcall(musb_init);
2259 static void __exit musb_cleanup(void)
2261 platform_driver_unregister(&musb_driver);
2263 module_exit(musb_cleanup);