drivers/usb/musb/g_ep0.c

   1 /******************************************************************
   2  * Copyright 2005 Mentor Graphics Corporation
   3  * Copyright (C) 2005-2006 by Texas Instruments
   4  *
   5  * This file is part of the Inventra Controller Driver for Linux.
   6  *
   7  * The Inventra Controller Driver for Linux is free software; you
   8  * can redistribute it and/or modify it under the terms of the GNU
   9  * General Public License version 2 as published by the Free Software
  10  * Foundation.
  11  *
  12  * The Inventra Controller Driver for Linux is distributed in
  13  * the hope that it will be useful, but WITHOUT ANY WARRANTY;
  14  * without even the implied warranty of MERCHANTABILITY or
  15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16  * License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with The Inventra Controller Driver for Linux ; if not,
  20  * write to the Free Software Foundation, Inc., 59 Temple Place,
  21  * Suite 330, Boston, MA  02111-1307  USA
  22  *
  23  * ANY DOWNLOAD, USE, REPRODUCTION, MODIFICATION OR DISTRIBUTION
  24  * OF THIS DRIVER INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE
  25  * OF THOSE TERMS.THIS DRIVER IS PROVIDED "AS IS" AND MENTOR GRAPHICS
  26  * MAKES NO WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THIS DRIVER.
  27  * MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES
  28  * OF MERCHANTABILITY; FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NON-INFRINGEMENT.  MENTOR GRAPHICS DOES NOT PROVIDE SUPPORT
  30  * SERVICES OR UPDATES FOR THIS DRIVER, EVEN IF YOU ARE A MENTOR
  31  * GRAPHICS SUPPORT CUSTOMER.
  32  ******************************************************************/
  33
  34 #include <linux/kernel.h>
  35 #include <linux/list.h>
  36 #include <linux/timer.h>
  37 #include <linux/spinlock.h>
  38 #include <linux/init.h>
  39 #include <linux/device.h>
  40 #include <linux/interrupt.h>
  41
  42 #include "musbdefs.h"
  43
  44 /* ep0 is always musb->aLocalEnd[0].ep_in */
  45 #define next_ep0_request(musb)  next_in_request(&(musb)->aLocalEnd[0])
  46
  47 /*
  48  * Locking note:  we use only the controller lock, for simpler correctness.
  49  * It's always held with IRQs blocked.
  50  *
  51  * It protects the ep0 request queue as well as ep0_state, not just the
  52  * controller and indexed registers.  And that lock stays held unless it
  53  * needs to be dropped to allow reentering this driver ... like upcalls to
  54  * the gadget driver, or adjusting endpoint halt status.
  55  */
  56
  57 static char *decode_ep0stage(u8 stage)
  58 {
  59         switch(stage) {
  60         case MGC_END0_STAGE_SETUP:      return "idle";
  61         case MGC_END0_STAGE_TX:         return "in";
  62         case MGC_END0_STAGE_RX:         return "out";
  63         case MGC_END0_STAGE_ACKWAIT:    return "wait";
  64         case MGC_END0_STAGE_STATUSIN:   return "in/status";
  65         case MGC_END0_STAGE_STATUSOUT:  return "out/status";
  66         default:                        return "?";
  67         }
  68 }
  69
  70 /* handle a standard GET_STATUS request
  71  * Context:  caller holds controller lock
  72  */
  73 static int service_tx_status_request(
  74         struct musb *musb,
  75         const struct usb_ctrlrequest *pControlRequest)
  76 {
  77         void __iomem    *pBase = musb->pRegs;
  78         int handled = 1;
  79         u8 bResult[2], bEnd = 0;
  80         const u8 bRecip = pControlRequest->bRequestType & USB_RECIP_MASK;
  81
  82         bResult[1] = 0;
  83
  84         switch (bRecip) {
  85         case USB_RECIP_DEVICE:
  86                 bResult[0] = musb->is_self_powered << USB_DEVICE_SELF_POWERED;
  87                 bResult[0] |= musb->may_wakeup << USB_DEVICE_REMOTE_WAKEUP;
  88 #ifdef CONFIG_USB_MUSB_OTG
  89                 if (musb->g.is_otg) {
  90                         bResult[0] |= musb->g.b_hnp_enable
  91                                 << USB_DEVICE_B_HNP_ENABLE;
  92                         bResult[0] |= musb->g.a_alt_hnp_support
  93                                 << USB_DEVICE_A_ALT_HNP_SUPPORT;
  94                         bResult[0] |= musb->g.a_hnp_support
  95                                 << USB_DEVICE_A_HNP_SUPPORT;
  96                 }
  97 #endif
  98                 break;
  99
 100         case USB_RECIP_INTERFACE:
 101                 bResult[0] = 0;
 102                 break;
 103
 104         case USB_RECIP_ENDPOINT: {
 105                 int             is_in;
 106                 struct musb_ep  *ep;
 107                 u16             tmp;
 108                 void __iomem    *regs;
 109
 110                 bEnd = (u8) pControlRequest->wIndex;
 111                 if (!bEnd) {
 112                         bResult[0] = 0;
 113                         break;
 114                 }
 115
 116                 is_in = bEnd & USB_DIR_IN;
 117                 if (is_in) {
 118                         bEnd &= 0x0f;
 119                         ep = &musb->aLocalEnd[bEnd].ep_in;
 120                 } else {
 121                         ep = &musb->aLocalEnd[bEnd].ep_out;
 122                 }
 123                 regs = musb->aLocalEnd[bEnd].regs;
 124
 125                 if (bEnd >= MUSB_C_NUM_EPS || !ep->desc) {
 126                         handled = -EINVAL;
 127                         break;
 128                 }
 129
 130                 MGC_SelectEnd(pBase, bEnd);
 131                 if (is_in)
 132                         tmp = musb_readw(regs, MGC_O_HDRC_TXCSR)
 133                                                 & MGC_M_TXCSR_P_SENDSTALL;
 134                 else
 135                         tmp = musb_readw(regs, MGC_O_HDRC_RXCSR)
 136                                                 & MGC_M_RXCSR_P_SENDSTALL;
 137                 MGC_SelectEnd(pBase, 0);
 138
 139                 bResult[0] = tmp ? 1 : 0;
 140                 } break;
 141
 142         default:
 143                 /* class, vendor, etc ... delegate */
 144                 handled = 0;
 145                 break;
 146         }
 147
 148         /* fill up the fifo; caller updates csr0 */
 149         if (handled > 0) {
 150                 u16     len = le16_to_cpu(pControlRequest->wLength);
 151
 152                 if (len > 2)
 153                         len = 2;
 154                 musb_write_fifo(&musb->aLocalEnd[0], len, bResult);
 155         }
 156
 157         return handled;
 158 }
 159
 160 /*
 161  * handle a control-IN request, the end0 buffer contains the current request
 162  * that is supposed to be a standard control request. Assumes the fifo to
 163  * be at least 2 bytes long.
 164  *
 165  * @return 0 if the request was NOT HANDLED,
 166  * < 0 when error
 167  * > 0 when the request is processed
 168  *
 169  * Context:  caller holds controller lock
 170  */
 171 static int
 172 service_in_request(struct musb *musb,
 173                 const struct usb_ctrlrequest *pControlRequest)
 174 {
 175         int handled = 0;        /* not handled */
 176
 177         if ((pControlRequest->bRequestType & USB_TYPE_MASK)
 178                         == USB_TYPE_STANDARD) {
 179                 switch (pControlRequest->bRequest) {
 180                 case USB_REQ_GET_STATUS:
 181                         handled = service_tx_status_request(musb,
 182                                         pControlRequest);
 183                         break;
 184
 185                 /* case USB_REQ_SYNC_FRAME: */
 186
 187                 default:
 188                         break;
 189                 }
 190         }
 191         return handled;
 192 }
 193
 194 /*
 195  * Context:  caller holds controller lock
 196  */
 197 static void musb_g_ep0_giveback(struct musb *musb, struct usb_request *req)
 198 {
 199         musb->ep0_state = MGC_END0_STAGE_SETUP;
 200         musb_g_giveback(&musb->aLocalEnd[0].ep_in, req, 0);
 201 }
 202
 203 /*
 204  * Tries to start B-device HNP negotiation if enabled via sysfs
 205  */
 206 static inline void musb_try_b_hnp_enable(struct musb *musb)
 207 {
 208         void __iomem    *pBase = musb->pRegs;
 209         u8              devctl;
 210
 211         DBG(1, "HNP: Setting HR\n");
 212         devctl = musb_readb(pBase, MGC_O_HDRC_DEVCTL);
 213         musb_writeb(pBase, MGC_O_HDRC_DEVCTL, devctl | MGC_M_DEVCTL_HR);
 214 }
 215
 216 /*
 217  * Handle all control requests with no DATA stage, including standard
 218  * requests such as:
 219  * USB_REQ_SET_CONFIGURATION, USB_REQ_SET_INTERFACE, unrecognized
 220  *      always delegated to the gadget driver
 221  * USB_REQ_SET_ADDRESS, USB_REQ_CLEAR_FEATURE, USB_REQ_SET_FEATURE
 222  *      always handled here, except for class/vendor/... features
 223  *
 224  * Context:  caller holds controller lock
 225  */
 226 static int
 227 service_zero_data_request(struct musb *musb,
 228                 struct usb_ctrlrequest *pControlRequest)
 229 __releases(musb->Lock)
 230 __acquires(musb->Lock)
 231 {
 232         int handled = -EINVAL;
 233         void __iomem *pBase = musb->pRegs;
 234         const u8 bRecip = pControlRequest->bRequestType & USB_RECIP_MASK;
 235
 236         /* the gadget driver handles everything except what we MUST handle */
 237         if ((pControlRequest->bRequestType & USB_TYPE_MASK)
 238                         == USB_TYPE_STANDARD) {
 239                 switch (pControlRequest->bRequest) {
 240                 case USB_REQ_SET_ADDRESS:
 241                         /* change it after the status stage */
 242                         musb->bSetAddress = TRUE;
 243                         musb->bAddress = (u8) (pControlRequest->wValue & 0x7f);
 244                         handled = 1;
 245                         break;
 246
 247                 case USB_REQ_CLEAR_FEATURE:
 248                         switch (bRecip) {
 249                         case USB_RECIP_DEVICE:
 250                                 if (pControlRequest->wValue
 251                                                 != USB_DEVICE_REMOTE_WAKEUP)
 252                                         break;
 253                                 musb->may_wakeup = 0;
 254                                 handled = 1;
 255                                 break;
 256                         case USB_RECIP_INTERFACE:
 257                                 break;
 258                         case USB_RECIP_ENDPOINT:{
 259                                 const u8 bEnd = pControlRequest->wIndex & 0x0f;
 260                                 struct musb_ep *pEnd;
 261
 262                                 if (bEnd == 0
 263                                                 || bEnd >= MUSB_C_NUM_EPS
 264                                                 || pControlRequest->wValue
 265                                                         != USB_ENDPOINT_HALT)
 266                                         break;
 267
 268                                 if (pControlRequest->wIndex & USB_DIR_IN)
 269                                         pEnd = &musb->aLocalEnd[bEnd].ep_in;
 270                                 else
 271                                         pEnd = &musb->aLocalEnd[bEnd].ep_out;
 272                                 if (!pEnd->desc)
 273                                         break;
 274
 275                                 /* REVISIT do it directly, no locking games */
 276                                 spin_unlock(&musb->Lock);
 277                                 musb_gadget_set_halt(&pEnd->end_point, 0);
 278                                 spin_lock(&musb->Lock);
 279
 280                                 /* select ep0 again */
 281                                 MGC_SelectEnd(pBase, 0);
 282                                 handled = 1;
 283                                 } break;
 284                         default:
 285                                 /* class, vendor, etc ... delegate */
 286                                 handled = 0;
 287                                 break;
 288                         }
 289                         break;
 290
 291                 case USB_REQ_SET_FEATURE:
 292                         switch (bRecip) {
 293                         case USB_RECIP_DEVICE:
 294                                 handled = 1;
 295                                 switch (pControlRequest->wValue) {
 296                                 case USB_DEVICE_REMOTE_WAKEUP:
 297                                         musb->may_wakeup = 1;
 298                                         break;
 299                                 case USB_DEVICE_TEST_MODE:
 300                                         if (musb->g.speed != USB_SPEED_HIGH)
 301                                                 goto stall;
 302                                         if (pControlRequest->wIndex & 0xff)
 303                                                 goto stall;
 304
 305                                         switch (pControlRequest->wIndex >> 8) {
 306                                         case 1:
 307                                                 pr_debug("TEST_J\n");
 308                                                 /* TEST_J */
 309                                                 musb->bTestModeValue =
 310                                                         MGC_M_TEST_J;
 311                                                 break;
 312                                         case 2:
 313                                                 /* TEST_K */
 314                                                 pr_debug("TEST_K\n");
 315                                                 musb->bTestModeValue =
 316                                                         MGC_M_TEST_K;
 317                                                 break;
 318                                         case 3:
 319                                                 /* TEST_SE0_NAK */
 320                                                 pr_debug("TEST_SE0_NAK\n");
 321                                                 musb->bTestModeValue =
 322                                                         MGC_M_TEST_SE0_NAK;
 323                                                 break;
 324                                         case 4:
 325                                                 /* TEST_PACKET */
 326                                                 pr_debug("TEST_PACKET\n");
 327                                                 musb->bTestModeValue =
 328                                                         MGC_M_TEST_PACKET;
 329                                                 break;
 330                                         default:
 331                                                 goto stall;
 332                                         }
 333
 334                                         /* enter test mode after irq */
 335                                         if (handled > 0)
 336                                                 musb->bTestMode = TRUE;
 337                                         break;
 338 #ifdef CONFIG_USB_MUSB_OTG
 339                                 case USB_DEVICE_B_HNP_ENABLE:
 340                                         if (!musb->g.is_otg)
 341                                                 goto stall;
 342                                         musb->g.b_hnp_enable = 1;
 343                                         musb_try_b_hnp_enable(musb);
 344                                         break;
 345                                 case USB_DEVICE_A_HNP_SUPPORT:
 346                                         if (!musb->g.is_otg)
 347                                                 goto stall;
 348                                         musb->g.a_hnp_support = 1;
 349                                         break;
 350                                 case USB_DEVICE_A_ALT_HNP_SUPPORT:
 351                                         if (!musb->g.is_otg)
 352                                                 goto stall;
 353                                         musb->g.a_alt_hnp_support = 1;
 354                                         break;
 355 #endif
 356 stall:
 357                                 default:
 358                                         handled = -EINVAL;
 359                                         break;
 360                                 }
 361                                 break;
 362
 363                         case USB_RECIP_INTERFACE:
 364                                 break;
 365
 366                         case USB_RECIP_ENDPOINT:{
 367                                 const u8                bEnd =
 368                                         pControlRequest->wIndex & 0x0f;
 369                                 struct musb_ep          *pEnd;
 370                                 struct musb_hw_ep       *ep;
 371                                 void __iomem            *regs;
 372                                 int                     is_in;
 373                                 u16                     csr;
 374
 375                                 if (bEnd == 0
 376                                                 || bEnd >= MUSB_C_NUM_EPS
 377                                                 || pControlRequest->wValue
 378                                                         != USB_ENDPOINT_HALT)
 379                                         break;
 380
 381                                 ep = musb->aLocalEnd + bEnd;
 382                                 regs = ep->regs;
 383                                 is_in = pControlRequest->wIndex & USB_DIR_IN;
 384                                 if (is_in)
 385                                         pEnd = &ep->ep_in;
 386                                 else
 387                                         pEnd = &ep->ep_out;
 388                                 if (!pEnd->desc)
 389                                         break;
 390
 391                                 MGC_SelectEnd(pBase, bEnd);
 392                                 if (is_in) {
 393                                         csr = musb_readw(regs,
 394                                                         MGC_O_HDRC_TXCSR);
 395                                         if (csr & MGC_M_TXCSR_FIFONOTEMPTY)
 396                                                 csr |= MGC_M_TXCSR_FLUSHFIFO;
 397                                         csr |= MGC_M_TXCSR_P_SENDSTALL
 398                                                 | MGC_M_TXCSR_CLRDATATOG
 399                                                 | MGC_M_TXCSR_P_WZC_BITS;
 400                                         musb_writew(regs, MGC_O_HDRC_TXCSR,
 401                                                         csr);
 402                                 } else {
 403                                         csr = musb_readw(regs,
 404                                                         MGC_O_HDRC_RXCSR);
 405                                         csr |= MGC_M_RXCSR_P_SENDSTALL
 406                                                 | MGC_M_RXCSR_FLUSHFIFO
 407                                                 | MGC_M_RXCSR_CLRDATATOG
 408                                                 | MGC_M_TXCSR_P_WZC_BITS;
 409                                         musb_writew(regs, MGC_O_HDRC_RXCSR,
 410                                                         csr);
 411                                 }
 412
 413                                 /* select ep0 again */
 414                                 MGC_SelectEnd(pBase, 0);
 415                                 handled = 1;
 416                                 } break;
 417
 418                         default:
 419                                 /* class, vendor, etc ... delegate */
 420                                 handled = 0;
 421                                 break;
 422                         }
 423                         break;
 424                 default:
 425                         /* delegate SET_CONFIGURATION, etc */
 426                         handled = 0;
 427                 }
 428         } else
 429                 handled = 0;
 430         return handled;
 431 }
 432
 433 /* we have an ep0out data packet
 434  * Context:  caller holds controller lock
 435  */
 436 static void ep0_rxstate(struct musb *this)
 437 {
 438         void __iomem            *regs = this->control_ep->regs;
 439         struct usb_request      *req;
 440         u16                     tmp;
 441
 442         req = next_ep0_request(this);
 443
 444         /* read packet and ack; or stall because of gadget driver bug:
 445          * should have provided the rx buffer before setup() returned.
 446          */
 447         if (req) {
 448                 void            *buf = req->buf + req->actual;
 449                 unsigned        len = req->length - req->actual;
 450
 451                 /* read the buffer */
 452                 tmp = musb_readb(regs, MGC_O_HDRC_COUNT0);
 453                 if (tmp > len) {
 454                         req->status = -EOVERFLOW;
 455                         tmp = len;
 456                 }
 457                 musb_read_fifo(&this->aLocalEnd[0], tmp, buf);
 458                 req->actual += tmp;
 459                 tmp = MGC_M_CSR0_P_SVDRXPKTRDY;
 460                 if (tmp < 64 || req->actual == req->length) {
 461                         this->ep0_state = MGC_END0_STAGE_STATUSIN;
 462                         tmp |= MGC_M_CSR0_P_DATAEND;
 463                 } else
 464                         req = NULL;
 465         } else
 466                 tmp = MGC_M_CSR0_P_SVDRXPKTRDY | MGC_M_CSR0_P_SENDSTALL;
 467         musb_writew(regs, MGC_O_HDRC_CSR0, tmp);
 468
 469
 470         /* NOTE:  we "should" hold off reporting DATAEND and going to
 471          * STATUSIN until after the completion handler decides whether
 472          * to issue a stall instead, since this hardware can do that.
 473          */
 474         if (req)
 475                 musb_g_ep0_giveback(this, req);
 476 }
 477
 478 /*
 479  * transmitting to the host (IN), this code might be called from IRQ
 480  * and from kernel thread.
 481  *
 482  * Context:  caller holds controller lock
 483  */
 484 static void ep0_txstate(struct musb *musb)
 485 {
 486         void __iomem            *regs = musb->control_ep->regs;
 487         struct usb_request      *pRequest = next_ep0_request(musb);
 488         u16                     wCsrVal = MGC_M_CSR0_TXPKTRDY;
 489         u8                      *pFifoSource;
 490         u8                      wFifoCount;
 491
 492         if (!pRequest) {
 493                 // WARN_ON(1);
 494                 DBG(2, "odd; csr0 %04x\n", musb_readw(regs, MGC_O_HDRC_CSR0));
 495                 return;
 496         }
 497
 498         /* load the data */
 499         pFifoSource = (u8 *) pRequest->buf + pRequest->actual;
 500         wFifoCount = min((unsigned) MGC_END0_FIFOSIZE,
 501                 pRequest->length - pRequest->actual);
 502         musb_write_fifo(&musb->aLocalEnd[0], wFifoCount, pFifoSource);
 503         pRequest->actual += wFifoCount;
 504
 505         /* update the flags */
 506         if (wFifoCount < MUSB_MAX_END0_PACKET
 507                         || pRequest->actual == pRequest->length) {
 508                 musb->ep0_state = MGC_END0_STAGE_STATUSOUT;
 509                 wCsrVal |= MGC_M_CSR0_P_DATAEND;
 510         } else
 511                 pRequest = NULL;
 512
 513         /* send it out, triggering a "txpktrdy cleared" irq */
 514         musb_writew(regs, MGC_O_HDRC_CSR0, wCsrVal);
 515
 516         /* report completions as soon as the fifo's loaded; there's no
 517          * win in waiting till this last packet gets acked.  (other than
 518          * very precise fault reporting, needed by USB TMC; possible with
 519          * this hardware, but not usable from portable gadget drivers.)
 520          */
 521         if (pRequest)
 522                 musb_g_ep0_giveback(musb, pRequest);
 523 }
 524
 525 /*
 526  * Read a SETUP packet (struct usb_ctrlrequest) from the hardware.
 527  * Fields are left in USB byte-order.
 528  *
 529  * Context:  caller holds controller lock.
 530  */
 531 static void
 532 musb_read_setup(struct musb *musb, struct usb_ctrlrequest *req)
 533 {
 534         struct usb_request      *r;
 535         void __iomem            *regs = musb->control_ep->regs;
 536
 537         musb_read_fifo(&musb->aLocalEnd[0], sizeof *req, (u8 *)req);
 538
 539         /* NOTE:  earlier 2.6 versions changed setup packets to host
 540          * order, but now USB packets always stay in USB byte order.
 541          */
 542         DBG(3, "SETUP req%02x.%02x v%04x i%04x l%d\n",
 543                 req->bRequestType,
 544                 req->bRequest,
 545                 le16_to_cpu(req->wValue),
 546                 le16_to_cpu(req->wIndex),
 547                 le16_to_cpu(req->wLength));
 548
 549         /* clean up any leftover transfers */
 550         r = next_ep0_request(musb);
 551         if (r)
 552                 musb_g_ep0_giveback(musb, r);
 553
 554         /* For zero-data requests we want to delay the STATUS stage to
 555          * avoid SETUPEND errors.  If we read data (OUT), delay accepting
 556          * packets until there's a buffer to store them in.
 557          *
 558          * If we write data, the controller acts happier if we enable
 559          * the TX FIFO right away, and give the controller a moment
 560          * to switch modes...
 561          */
 562         musb->bSetAddress = FALSE;
 563         musb->ackpend = MGC_M_CSR0_P_SVDRXPKTRDY;
 564         if (req->wLength == 0) {
 565                 if (req->bRequestType & USB_DIR_IN)
 566                         musb->ackpend |= MGC_M_CSR0_TXPKTRDY;
 567                 musb->ep0_state = MGC_END0_STAGE_ACKWAIT;
 568         } else if (req->bRequestType & USB_DIR_IN) {
 569                 musb->ep0_state = MGC_END0_STAGE_TX;
 570                 musb_writew(regs, MGC_O_HDRC_CSR0, MGC_M_CSR0_P_SVDRXPKTRDY);
 571                 while ((musb_readw(regs, MGC_O_HDRC_CSR0)
 572                                 & MGC_M_CSR0_RXPKTRDY) != 0)
 573                         cpu_relax();
 574                 musb->ackpend = 0;
 575         } else
 576                 musb->ep0_state = MGC_END0_STAGE_RX;
 577 }
 578
 579 static int
 580 forward_to_driver(struct musb *musb,
 581                 const struct usb_ctrlrequest *pControlRequest)
 582 __releases(musb->Lock)
 583 __acquires(musb->Lock)
 584 {
 585         int retval;
 586         if (!musb->pGadgetDriver)
 587                 return -EOPNOTSUPP;
 588         spin_unlock(&musb->Lock);
 589         retval = musb->pGadgetDriver->setup(&musb->g, pControlRequest);
 590         spin_lock(&musb->Lock);
 591         return retval;
 592 }
 593
 594 /*
 595  * Handle peripheral ep0 interrupt
 596  *
 597  * Context: irq handler; we won't re-enter the driver that way.
 598  */
 599 irqreturn_t musb_g_ep0_irq(struct musb *musb)
 600 {
 601         u16             wCsrVal;
 602         u16             wCount;
 603         void __iomem    *pBase = musb->pRegs;
 604         void __iomem    *regs = musb->aLocalEnd[0].regs;
 605         irqreturn_t     retval = IRQ_NONE;
 606
 607         MGC_SelectEnd(pBase, 0);        /* select ep0 */
 608         wCsrVal = musb_readw(regs, MGC_O_HDRC_CSR0);
 609         wCount = musb_readb(regs, MGC_O_HDRC_COUNT0);
 610
 611         DBG(4, "csr %04x, count %d, myaddr %d, ep0stage %s\n",
 612                         wCsrVal, wCount,
 613                         musb_readb(pBase, MGC_O_HDRC_FADDR),
 614                         decode_ep0stage(musb->ep0_state));
 615
 616         /* I sent a stall.. need to acknowledge it now.. */
 617         if (wCsrVal & MGC_M_CSR0_P_SENTSTALL) {
 618                 musb_writew(regs, MGC_O_HDRC_CSR0,
 619                                 wCsrVal & ~MGC_M_CSR0_P_SENTSTALL);
 620                 retval = IRQ_HANDLED;
 621                 musb->ep0_state = MGC_END0_STAGE_SETUP;
 622                 wCsrVal = musb_readw(regs, MGC_O_HDRC_CSR0);
 623         }
 624
 625         /* request ended "early" */
 626         if (wCsrVal & MGC_M_CSR0_P_SETUPEND) {
 627                 musb_writew(regs, MGC_O_HDRC_CSR0, MGC_M_CSR0_P_SVDSETUPEND);
 628                 retval = IRQ_HANDLED;
 629                 musb->ep0_state = MGC_END0_STAGE_SETUP;
 630                 wCsrVal = musb_readw(regs, MGC_O_HDRC_CSR0);
 631                 /* NOTE:  request may need completion */
 632         }
 633
 634         /* docs from Mentor only describe tx, rx, and idle/setup states.
 635          * we need to handle nuances around status stages, and also the
 636          * case where status and setup stages come back-to-back ...
 637          */
 638         switch (musb->ep0_state) {
 639
 640         case MGC_END0_STAGE_TX:
 641                 /* irq on clearing txpktrdy */
 642                 if ((wCsrVal & MGC_M_CSR0_TXPKTRDY) == 0) {
 643                         ep0_txstate(musb);
 644                         retval = IRQ_HANDLED;
 645                 }
 646                 break;
 647
 648         case MGC_END0_STAGE_RX:
 649                 /* irq on set rxpktrdy */
 650                 if (wCsrVal & MGC_M_CSR0_RXPKTRDY) {
 651                         ep0_rxstate(musb);
 652                         retval = IRQ_HANDLED;
 653                 }
 654                 break;
 655
 656         case MGC_END0_STAGE_STATUSIN:
 657                 /* end of sequence #2 (OUT/RX state) or #3 (no data) */
 658
 659                 /* update address (if needed) only @ the end of the
 660                  * status phase per usb spec, which also guarantees
 661                  * we get 10 msec to receive this irq... until this
 662                  * is done we won't see the next packet.
 663                  */
 664                 if (musb->bSetAddress) {
 665                         musb->bSetAddress = FALSE;
 666                         musb_writeb(pBase, MGC_O_HDRC_FADDR, musb->bAddress);
 667                 }
 668
 669                 /* enter test mode if needed (exit by reset) */
 670                 else if (musb->bTestMode) {
 671                         DBG(1, "entering TESTMODE\n");
 672
 673                         if (MGC_M_TEST_PACKET == musb->bTestModeValue)
 674                                 musb_load_testpacket(musb);
 675
 676                         musb_writeb(pBase, MGC_O_HDRC_TESTMODE,
 677                                         musb->bTestModeValue);
 678                 }
 679                 /* FALLTHROUGH */
 680
 681         case MGC_END0_STAGE_STATUSOUT:
 682                 /* end of sequence #1: write to host (TX state) */
 683                 {
 684                         struct usb_request      *req;
 685
 686                         req = next_ep0_request(musb);
 687                         if (req)
 688                                 musb_g_ep0_giveback(musb, req);
 689                 }
 690                 retval = IRQ_HANDLED;
 691                 musb->ep0_state = MGC_END0_STAGE_SETUP;
 692                 /* FALLTHROUGH */
 693
 694         case MGC_END0_STAGE_SETUP:
 695                 if (wCsrVal & MGC_M_CSR0_RXPKTRDY) {
 696                         struct usb_ctrlrequest  setup;
 697                         int                     handled = 0;
 698
 699                         if (wCount != 8) {
 700                                 ERR("SETUP packet len %d != 8 ?\n", wCount);
 701                                 break;
 702                         }
 703                         musb_read_setup(musb, &setup);
 704                         retval = IRQ_HANDLED;
 705
 706                         /* sometimes the RESET won't be reported */
 707                         if (unlikely(musb->g.speed == USB_SPEED_UNKNOWN)) {
 708                                 u8      power;
 709
 710                                 printk(KERN_NOTICE "%s: peripheral reset "
 711                                                 "irq lost!\n",
 712                                                 musb_driver_name);
 713                                 power = musb_readb(pBase, MGC_O_HDRC_POWER);
 714                                 musb->g.speed = (power & MGC_M_POWER_HSMODE)
 715                                         ? USB_SPEED_HIGH : USB_SPEED_FULL;
 716
 717                         }
 718
 719                         switch (musb->ep0_state) {
 720
 721                         /* sequence #3 (no data stage), includes requests
 722                          * we can't forward (notably SET_ADDRESS and the
 723                          * device/endpoint feature set/clear operations)
 724                          * plus SET_CONFIGURATION and others we must
 725                          */
 726                         case MGC_END0_STAGE_ACKWAIT:
 727                                 handled = service_zero_data_request(
 728                                                 musb, &setup);
 729
 730                                 /* status stage might be immediate */
 731                                 if (handled > 0) {
 732                                         musb->ackpend |= MGC_M_CSR0_P_DATAEND;
 733                                         musb->ep0_state =
 734                                                 MGC_END0_STAGE_STATUSIN;
 735                                 }
 736                                 break;
 737
 738                         /* sequence #1 (IN to host), includes GET_STATUS
 739                          * requests that we can't forward, GET_DESCRIPTOR
 740                          * and others that we must
 741                          */
 742                         case MGC_END0_STAGE_TX:
 743                                 handled = service_in_request(musb, &setup);
 744                                 if (handled > 0) {
 745                                         musb->ackpend = MGC_M_CSR0_TXPKTRDY
 746                                                 | MGC_M_CSR0_P_DATAEND;
 747                                         musb->ep0_state =
 748                                                 MGC_END0_STAGE_STATUSOUT;
 749                                 }
 750                                 break;
 751
 752                         /* sequence #2 (OUT from host), always forward */
 753                         default:                /* MGC_END0_STAGE_RX */
 754                                 break;
 755                         }
 756
 757                         DBG(3, "handled %d, csr %04x, ep0stage %s\n",
 758                                 handled, wCsrVal,
 759                                 decode_ep0stage(musb->ep0_state));
 760
 761                         /* unless we need to delegate this to the gadget
 762                          * driver, we know how to wrap this up:  csr0 has
 763                          * not yet been written.
 764                          */
 765                         if (handled < 0)
 766                                 goto stall;
 767                         else if (handled > 0)
 768                                 goto finish;
 769
 770                         handled = forward_to_driver(musb, &setup);
 771                         if (handled < 0) {
 772                                 MGC_SelectEnd(pBase, 0);
 773 stall:
 774                                 DBG(3, "stall (%d)\n", handled);
 775                                 musb->ackpend |= MGC_M_CSR0_P_SENDSTALL;
 776                                 musb->ep0_state = MGC_END0_STAGE_SETUP;
 777 finish:
 778                                 musb_writew(regs, MGC_O_HDRC_CSR0,
 779                                                 musb->ackpend);
 780                                 musb->ackpend = 0;
 781                         }
 782                 }
 783                 break;
 784
 785         case MGC_END0_STAGE_ACKWAIT:
 786                 /* This should not happen. But happens with tusb6010 with
 787                  * g_file_storage and high speed. Do nothing.
 788                  */
 789                 retval = IRQ_HANDLED;
 790                 break;
 791
 792         default:
 793                 /* "can't happen" */
 794                 WARN_ON(1);
 795                 musb_writew(regs, MGC_O_HDRC_CSR0, MGC_M_CSR0_P_SENDSTALL);
 796                 musb->ep0_state = MGC_END0_STAGE_SETUP;
 797                 break;
 798         }
 799
 800         return retval;
 801 }
 802
 803
 804 static int
 805 musb_g_ep0_enable(struct usb_ep *ep, const struct usb_endpoint_descriptor *desc)
 806 {
 807         /* always enabled */
 808         return -EINVAL;
 809 }
 810
 811 static int musb_g_ep0_disable(struct usb_ep *e)
 812 {
 813         /* always enabled */
 814         return -EINVAL;
 815 }
 816
 817 static void *musb_g_ep0_alloc_buffer(struct usb_ep *ep, unsigned bytes,
 818                         dma_addr_t * dma, gfp_t gfp_flags)
 819 {
 820         *dma = DMA_ADDR_INVALID;
 821         return kmalloc(bytes, gfp_flags);
 822 }
 823
 824 static void musb_g_ep0_free_buffer(struct usb_ep *ep, void *address,
 825                         dma_addr_t dma, unsigned bytes)
 826 {
 827         kfree(address);
 828 }
 829
 830 static int
 831 musb_g_ep0_queue(struct usb_ep *e, struct usb_request *r, gfp_t gfp_flags)
 832 {
 833         struct musb_ep          *ep;
 834         struct musb_request     *req;
 835         struct musb             *musb;
 836         int                     status;
 837         unsigned long           lockflags;
 838         void __iomem            *regs;
 839
 840         if (!e || !r)
 841                 return -EINVAL;
 842
 843         ep = to_musb_ep(e);
 844         musb = ep->pThis;
 845         regs = musb->control_ep->regs;
 846
 847         req = to_musb_request(r);
 848         req->musb = musb;
 849         req->request.actual = 0;
 850         req->request.status = -EINPROGRESS;
 851         req->bTx = ep->is_in;
 852
 853         spin_lock_irqsave(&musb->Lock, lockflags);
 854
 855         if (!list_empty(&ep->req_list)) {
 856                 status = -EBUSY;
 857                 goto cleanup;
 858         }
 859
 860         switch (musb->ep0_state) {
 861         case MGC_END0_STAGE_RX:         /* control-OUT data */
 862         case MGC_END0_STAGE_TX:         /* control-IN data */
 863         case MGC_END0_STAGE_ACKWAIT:    /* zero-length data */
 864                 status = 0;
 865                 break;
 866         default:
 867                 DBG(1, "ep0 request queued in state %d\n",
 868                                 musb->ep0_state);
 869                 status = -EINVAL;
 870                 goto cleanup;
 871         }
 872
 873         /* add request to the list */
 874         list_add_tail(&(req->request.list), &(ep->req_list));
 875
 876         DBG(3, "queue to %s (%s), length=%d\n",
 877                         ep->name, ep->is_in ? "IN/TX" : "OUT/RX",
 878                         req->request.length);
 879
 880         MGC_SelectEnd(musb->pRegs, 0);
 881
 882         /* sequence #1, IN ... start writing the data */
 883         if (musb->ep0_state == MGC_END0_STAGE_TX)
 884                 ep0_txstate(musb);
 885
 886         /* sequence #3, no-data ... issue IN status */
 887         else if (musb->ep0_state == MGC_END0_STAGE_ACKWAIT) {
 888                 if (req->request.length)
 889                         status = -EINVAL;
 890                 else {
 891                         musb->ep0_state = MGC_END0_STAGE_STATUSIN;
 892                         musb_writew(regs, MGC_O_HDRC_CSR0,
 893                                         musb->ackpend | MGC_M_CSR0_P_DATAEND);
 894                         musb->ackpend = 0;
 895                         musb_g_ep0_giveback(ep->pThis, r);
 896                 }
 897
 898         /* else for sequence #2 (OUT), caller provides a buffer
 899          * before the next packet arrives.  deferred responses
 900          * (after SETUP is acked) are racey.
 901          */
 902         } else if (musb->ackpend) {
 903                 musb_writew(regs, MGC_O_HDRC_CSR0, musb->ackpend);
 904                 musb->ackpend = 0;
 905         }
 906
 907 cleanup:
 908         spin_unlock_irqrestore(&musb->Lock, lockflags);
 909         return status;
 910 }
 911
 912 static int
 913 musb_g_ep0_dequeue(struct usb_ep *ep, struct usb_request *req)
 914 {
 915         /* we just won't support this */
 916         return -EINVAL;
 917 }
 918
 919 static int musb_g_ep0_halt(struct usb_ep *e, int value)
 920 {
 921         struct musb_ep          *ep;
 922         struct musb             *musb;
 923         void __iomem            *base, *regs;
 924         unsigned long           flags;
 925         int                     status;
 926         u16                     csr;
 927
 928         if (!e || !value)
 929                 return -EINVAL;
 930
 931         ep = to_musb_ep(e);
 932         musb = ep->pThis;
 933         base = musb->pRegs;
 934         regs = musb->control_ep->regs;
 935
 936         spin_lock_irqsave(&musb->Lock, flags);
 937
 938         if (!list_empty(&ep->req_list)) {
 939                 status = -EBUSY;
 940                 goto cleanup;
 941         }
 942
 943         switch (musb->ep0_state) {
 944         case MGC_END0_STAGE_TX:         /* control-IN data */
 945         case MGC_END0_STAGE_ACKWAIT:    /* STALL for zero-length data */
 946         case MGC_END0_STAGE_RX:         /* control-OUT data */
 947                 status = 0;
 948
 949                 MGC_SelectEnd(base, 0);
 950                 csr = musb_readw(regs, MGC_O_HDRC_CSR0);
 951                 csr |= MGC_M_CSR0_P_SENDSTALL;
 952                 musb_writew(regs, MGC_O_HDRC_CSR0, csr);
 953                 musb->ep0_state = MGC_END0_STAGE_SETUP;
 954                 break;
 955         default:
 956                 DBG(1, "ep0 can't halt in state %d\n", musb->ep0_state);
 957                 status = -EINVAL;
 958         }
 959
 960 cleanup:
 961         spin_unlock_irqrestore(&musb->Lock, flags);
 962         return status;
 963 }
 964
 965 const struct usb_ep_ops musb_g_ep0_ops = {
 966         .enable         = musb_g_ep0_enable,
 967         .disable        = musb_g_ep0_disable,
 968         .alloc_request  = musb_alloc_request,
 969         .free_request   = musb_free_request,
 970         .alloc_buffer   = musb_g_ep0_alloc_buffer,
 971         .free_buffer    = musb_g_ep0_free_buffer,
 972         .queue          = musb_g_ep0_queue,
 973         .dequeue        = musb_g_ep0_dequeue,
 974         .set_halt       = musb_g_ep0_halt,
 975         .fifo_status    = NULL,
 976         .fifo_flush     = NULL,
 977 };