1 /******************************************************************
2 * Copyright 2005 Mentor Graphics Corporation
3 * Copyright (C) 2005-2006 by Texas Instruments
5 * This file is part of the Inventra Controller Driver for Linux.
7 * The Inventra Controller Driver for Linux is free software; you
8 * can redistribute it and/or modify it under the terms of the GNU
9 * General Public License version 2 as published by the Free Software
12 * The Inventra Controller Driver for Linux is distributed in
13 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
14 * without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 * License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with The Inventra Controller Driver for Linux ; if not,
20 * write to the Free Software Foundation, Inc., 59 Temple Place,
21 * Suite 330, Boston, MA 02111-1307 USA
23 * ANY DOWNLOAD, USE, REPRODUCTION, MODIFICATION OR DISTRIBUTION
24 * OF THIS DRIVER INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE
25 * OF THOSE TERMS.THIS DRIVER IS PROVIDED "AS IS" AND MENTOR GRAPHICS
26 * MAKES NO WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THIS DRIVER.
27 * MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES
28 * OF MERCHANTABILITY; FITNESS FOR A PARTICULAR PURPOSE AND
29 * NON-INFRINGEMENT. MENTOR GRAPHICS DOES NOT PROVIDE SUPPORT
30 * SERVICES OR UPDATES FOR THIS DRIVER, EVEN IF YOU ARE A MENTOR
31 * GRAPHICS SUPPORT CUSTOMER.
32 ******************************************************************/
34 #include <linux/kernel.h>
35 #include <linux/list.h>
36 #include <linux/timer.h>
37 #include <linux/spinlock.h>
38 #include <linux/init.h>
39 #include <linux/device.h>
40 #include <linux/interrupt.h>
44 /* ep0 is always musb->aLocalEnd[0].ep_in */
45 #define next_ep0_request(musb) next_in_request(&(musb)->aLocalEnd[0])
48 * Locking note: we use only the controller lock, for simpler correctness.
49 * It's always held with IRQs blocked.
51 * It protects the ep0 request queue as well as ep0_state, not just the
52 * controller and indexed registers. And that lock stays held unless it
53 * needs to be dropped to allow reentering this driver ... like upcalls to
54 * the gadget driver, or adjusting endpoint halt status.
57 static char *decode_ep0stage(u8 stage)
60 case MGC_END0_STAGE_SETUP: return "idle";
61 case MGC_END0_STAGE_TX: return "in";
62 case MGC_END0_STAGE_RX: return "out";
63 case MGC_END0_STAGE_ACKWAIT: return "wait";
64 case MGC_END0_STAGE_STATUSIN: return "in/status";
65 case MGC_END0_STAGE_STATUSOUT: return "out/status";
70 /* handle a standard GET_STATUS request
71 * Context: caller holds controller lock
73 static int service_tx_status_request(
75 const struct usb_ctrlrequest *pControlRequest)
77 void __iomem *pBase = musb->pRegs;
79 u8 bResult[2], bEnd = 0;
80 const u8 bRecip = pControlRequest->bRequestType & USB_RECIP_MASK;
85 case USB_RECIP_DEVICE:
86 bResult[0] = musb->is_self_powered << USB_DEVICE_SELF_POWERED;
87 bResult[0] |= musb->may_wakeup << USB_DEVICE_REMOTE_WAKEUP;
88 #ifdef CONFIG_USB_MUSB_OTG
90 bResult[0] |= musb->g.b_hnp_enable
91 << USB_DEVICE_B_HNP_ENABLE;
92 bResult[0] |= musb->g.a_alt_hnp_support
93 << USB_DEVICE_A_ALT_HNP_SUPPORT;
94 bResult[0] |= musb->g.a_hnp_support
95 << USB_DEVICE_A_HNP_SUPPORT;
100 case USB_RECIP_INTERFACE:
104 case USB_RECIP_ENDPOINT: {
110 bEnd = (u8) pControlRequest->wIndex;
116 is_in = bEnd & USB_DIR_IN;
119 ep = &musb->aLocalEnd[bEnd].ep_in;
121 ep = &musb->aLocalEnd[bEnd].ep_out;
123 regs = musb->aLocalEnd[bEnd].regs;
125 if (bEnd >= MUSB_C_NUM_EPS || !ep->desc) {
130 MGC_SelectEnd(pBase, bEnd);
132 tmp = musb_readw(regs, MGC_O_HDRC_TXCSR)
133 & MGC_M_TXCSR_P_SENDSTALL;
135 tmp = musb_readw(regs, MGC_O_HDRC_RXCSR)
136 & MGC_M_RXCSR_P_SENDSTALL;
137 MGC_SelectEnd(pBase, 0);
139 bResult[0] = tmp ? 1 : 0;
143 /* class, vendor, etc ... delegate */
148 /* fill up the fifo; caller updates csr0 */
150 u16 len = le16_to_cpu(pControlRequest->wLength);
154 musb_write_fifo(&musb->aLocalEnd[0], len, bResult);
161 * handle a control-IN request, the end0 buffer contains the current request
162 * that is supposed to be a standard control request. Assumes the fifo to
163 * be at least 2 bytes long.
165 * @return 0 if the request was NOT HANDLED,
167 * > 0 when the request is processed
169 * Context: caller holds controller lock
172 service_in_request(struct musb *musb,
173 const struct usb_ctrlrequest *pControlRequest)
175 int handled = 0; /* not handled */
177 if ((pControlRequest->bRequestType & USB_TYPE_MASK)
178 == USB_TYPE_STANDARD) {
179 switch (pControlRequest->bRequest) {
180 case USB_REQ_GET_STATUS:
181 handled = service_tx_status_request(musb,
185 /* case USB_REQ_SYNC_FRAME: */
195 * Context: caller holds controller lock
197 static void musb_g_ep0_giveback(struct musb *musb, struct usb_request *req)
199 musb->ep0_state = MGC_END0_STAGE_SETUP;
200 musb_g_giveback(&musb->aLocalEnd[0].ep_in, req, 0);
204 * Tries to start B-device HNP negotiation if enabled via sysfs
206 static inline void musb_try_b_hnp_enable(struct musb *musb)
208 void __iomem *pBase = musb->pRegs;
211 DBG(1, "HNP: Setting HR\n");
212 devctl = musb_readb(pBase, MGC_O_HDRC_DEVCTL);
213 musb_writeb(pBase, MGC_O_HDRC_DEVCTL, devctl | MGC_M_DEVCTL_HR);
217 * Handle all control requests with no DATA stage, including standard
219 * USB_REQ_SET_CONFIGURATION, USB_REQ_SET_INTERFACE, unrecognized
220 * always delegated to the gadget driver
221 * USB_REQ_SET_ADDRESS, USB_REQ_CLEAR_FEATURE, USB_REQ_SET_FEATURE
222 * always handled here, except for class/vendor/... features
224 * Context: caller holds controller lock
227 service_zero_data_request(struct musb *musb,
228 struct usb_ctrlrequest *pControlRequest)
229 __releases(musb->Lock)
230 __acquires(musb->Lock)
232 int handled = -EINVAL;
233 void __iomem *pBase = musb->pRegs;
234 const u8 bRecip = pControlRequest->bRequestType & USB_RECIP_MASK;
236 /* the gadget driver handles everything except what we MUST handle */
237 if ((pControlRequest->bRequestType & USB_TYPE_MASK)
238 == USB_TYPE_STANDARD) {
239 switch (pControlRequest->bRequest) {
240 case USB_REQ_SET_ADDRESS:
241 /* change it after the status stage */
242 musb->bSetAddress = TRUE;
243 musb->bAddress = (u8) (pControlRequest->wValue & 0x7f);
247 case USB_REQ_CLEAR_FEATURE:
249 case USB_RECIP_DEVICE:
250 if (pControlRequest->wValue
251 != USB_DEVICE_REMOTE_WAKEUP)
253 musb->may_wakeup = 0;
256 case USB_RECIP_INTERFACE:
258 case USB_RECIP_ENDPOINT:{
259 const u8 bEnd = pControlRequest->wIndex & 0x0f;
260 struct musb_ep *pEnd;
263 || bEnd >= MUSB_C_NUM_EPS
264 || pControlRequest->wValue
265 != USB_ENDPOINT_HALT)
268 if (pControlRequest->wIndex & USB_DIR_IN)
269 pEnd = &musb->aLocalEnd[bEnd].ep_in;
271 pEnd = &musb->aLocalEnd[bEnd].ep_out;
275 /* REVISIT do it directly, no locking games */
276 spin_unlock(&musb->Lock);
277 musb_gadget_set_halt(&pEnd->end_point, 0);
278 spin_lock(&musb->Lock);
280 /* select ep0 again */
281 MGC_SelectEnd(pBase, 0);
285 /* class, vendor, etc ... delegate */
291 case USB_REQ_SET_FEATURE:
293 case USB_RECIP_DEVICE:
295 switch (pControlRequest->wValue) {
296 case USB_DEVICE_REMOTE_WAKEUP:
297 musb->may_wakeup = 1;
299 case USB_DEVICE_TEST_MODE:
300 if (musb->g.speed != USB_SPEED_HIGH)
302 if (pControlRequest->wIndex & 0xff)
305 switch (pControlRequest->wIndex >> 8) {
307 pr_debug("TEST_J\n");
309 musb->bTestModeValue =
314 pr_debug("TEST_K\n");
315 musb->bTestModeValue =
320 pr_debug("TEST_SE0_NAK\n");
321 musb->bTestModeValue =
326 pr_debug("TEST_PACKET\n");
327 musb->bTestModeValue =
334 /* enter test mode after irq */
336 musb->bTestMode = TRUE;
338 #ifdef CONFIG_USB_MUSB_OTG
339 case USB_DEVICE_B_HNP_ENABLE:
342 musb->g.b_hnp_enable = 1;
343 musb_try_b_hnp_enable(musb);
345 case USB_DEVICE_A_HNP_SUPPORT:
348 musb->g.a_hnp_support = 1;
350 case USB_DEVICE_A_ALT_HNP_SUPPORT:
353 musb->g.a_alt_hnp_support = 1;
363 case USB_RECIP_INTERFACE:
366 case USB_RECIP_ENDPOINT:{
368 pControlRequest->wIndex & 0x0f;
369 struct musb_ep *pEnd;
370 struct musb_hw_ep *ep;
376 || bEnd >= MUSB_C_NUM_EPS
377 || pControlRequest->wValue
378 != USB_ENDPOINT_HALT)
381 ep = musb->aLocalEnd + bEnd;
383 is_in = pControlRequest->wIndex & USB_DIR_IN;
391 MGC_SelectEnd(pBase, bEnd);
393 csr = musb_readw(regs,
395 if (csr & MGC_M_TXCSR_FIFONOTEMPTY)
396 csr |= MGC_M_TXCSR_FLUSHFIFO;
397 csr |= MGC_M_TXCSR_P_SENDSTALL
398 | MGC_M_TXCSR_CLRDATATOG
399 | MGC_M_TXCSR_P_WZC_BITS;
400 musb_writew(regs, MGC_O_HDRC_TXCSR,
403 csr = musb_readw(regs,
405 csr |= MGC_M_RXCSR_P_SENDSTALL
406 | MGC_M_RXCSR_FLUSHFIFO
407 | MGC_M_RXCSR_CLRDATATOG
408 | MGC_M_TXCSR_P_WZC_BITS;
409 musb_writew(regs, MGC_O_HDRC_RXCSR,
413 /* select ep0 again */
414 MGC_SelectEnd(pBase, 0);
419 /* class, vendor, etc ... delegate */
425 /* delegate SET_CONFIGURATION, etc */
433 /* we have an ep0out data packet
434 * Context: caller holds controller lock
436 static void ep0_rxstate(struct musb *this)
438 void __iomem *regs = this->control_ep->regs;
439 struct usb_request *req;
442 req = next_ep0_request(this);
444 /* read packet and ack; or stall because of gadget driver bug:
445 * should have provided the rx buffer before setup() returned.
448 void *buf = req->buf + req->actual;
449 unsigned len = req->length - req->actual;
451 /* read the buffer */
452 tmp = musb_readb(regs, MGC_O_HDRC_COUNT0);
454 req->status = -EOVERFLOW;
457 musb_read_fifo(&this->aLocalEnd[0], tmp, buf);
459 tmp = MGC_M_CSR0_P_SVDRXPKTRDY;
460 if (tmp < 64 || req->actual == req->length) {
461 this->ep0_state = MGC_END0_STAGE_STATUSIN;
462 tmp |= MGC_M_CSR0_P_DATAEND;
466 tmp = MGC_M_CSR0_P_SVDRXPKTRDY | MGC_M_CSR0_P_SENDSTALL;
467 musb_writew(regs, MGC_O_HDRC_CSR0, tmp);
470 /* NOTE: we "should" hold off reporting DATAEND and going to
471 * STATUSIN until after the completion handler decides whether
472 * to issue a stall instead, since this hardware can do that.
475 musb_g_ep0_giveback(this, req);
479 * transmitting to the host (IN), this code might be called from IRQ
480 * and from kernel thread.
482 * Context: caller holds controller lock
484 static void ep0_txstate(struct musb *musb)
486 void __iomem *regs = musb->control_ep->regs;
487 struct usb_request *pRequest = next_ep0_request(musb);
488 u16 wCsrVal = MGC_M_CSR0_TXPKTRDY;
494 DBG(2, "odd; csr0 %04x\n", musb_readw(regs, MGC_O_HDRC_CSR0));
499 pFifoSource = (u8 *) pRequest->buf + pRequest->actual;
500 wFifoCount = min((unsigned) MGC_END0_FIFOSIZE,
501 pRequest->length - pRequest->actual);
502 musb_write_fifo(&musb->aLocalEnd[0], wFifoCount, pFifoSource);
503 pRequest->actual += wFifoCount;
505 /* update the flags */
506 if (wFifoCount < MUSB_MAX_END0_PACKET
507 || pRequest->actual == pRequest->length) {
508 musb->ep0_state = MGC_END0_STAGE_STATUSOUT;
509 wCsrVal |= MGC_M_CSR0_P_DATAEND;
513 /* send it out, triggering a "txpktrdy cleared" irq */
514 musb_writew(regs, MGC_O_HDRC_CSR0, wCsrVal);
516 /* report completions as soon as the fifo's loaded; there's no
517 * win in waiting till this last packet gets acked. (other than
518 * very precise fault reporting, needed by USB TMC; possible with
519 * this hardware, but not usable from portable gadget drivers.)
522 musb_g_ep0_giveback(musb, pRequest);
526 * Read a SETUP packet (struct usb_ctrlrequest) from the hardware.
527 * Fields are left in USB byte-order.
529 * Context: caller holds controller lock.
532 musb_read_setup(struct musb *musb, struct usb_ctrlrequest *req)
534 struct usb_request *r;
535 void __iomem *regs = musb->control_ep->regs;
537 musb_read_fifo(&musb->aLocalEnd[0], sizeof *req, (u8 *)req);
539 /* NOTE: earlier 2.6 versions changed setup packets to host
540 * order, but now USB packets always stay in USB byte order.
542 DBG(3, "SETUP req%02x.%02x v%04x i%04x l%d\n",
545 le16_to_cpu(req->wValue),
546 le16_to_cpu(req->wIndex),
547 le16_to_cpu(req->wLength));
549 /* clean up any leftover transfers */
550 r = next_ep0_request(musb);
552 musb_g_ep0_giveback(musb, r);
554 /* For zero-data requests we want to delay the STATUS stage to
555 * avoid SETUPEND errors. If we read data (OUT), delay accepting
556 * packets until there's a buffer to store them in.
558 * If we write data, the controller acts happier if we enable
559 * the TX FIFO right away, and give the controller a moment
562 musb->bSetAddress = FALSE;
563 musb->ackpend = MGC_M_CSR0_P_SVDRXPKTRDY;
564 if (req->wLength == 0) {
565 if (req->bRequestType & USB_DIR_IN)
566 musb->ackpend |= MGC_M_CSR0_TXPKTRDY;
567 musb->ep0_state = MGC_END0_STAGE_ACKWAIT;
568 } else if (req->bRequestType & USB_DIR_IN) {
569 musb->ep0_state = MGC_END0_STAGE_TX;
570 musb_writew(regs, MGC_O_HDRC_CSR0, MGC_M_CSR0_P_SVDRXPKTRDY);
571 while ((musb_readw(regs, MGC_O_HDRC_CSR0)
572 & MGC_M_CSR0_RXPKTRDY) != 0)
576 musb->ep0_state = MGC_END0_STAGE_RX;
580 forward_to_driver(struct musb *musb,
581 const struct usb_ctrlrequest *pControlRequest)
582 __releases(musb->Lock)
583 __acquires(musb->Lock)
586 if (!musb->pGadgetDriver)
588 spin_unlock(&musb->Lock);
589 retval = musb->pGadgetDriver->setup(&musb->g, pControlRequest);
590 spin_lock(&musb->Lock);
595 * Handle peripheral ep0 interrupt
597 * Context: irq handler; we won't re-enter the driver that way.
599 irqreturn_t musb_g_ep0_irq(struct musb *musb)
603 void __iomem *pBase = musb->pRegs;
604 void __iomem *regs = musb->aLocalEnd[0].regs;
605 irqreturn_t retval = IRQ_NONE;
607 MGC_SelectEnd(pBase, 0); /* select ep0 */
608 wCsrVal = musb_readw(regs, MGC_O_HDRC_CSR0);
609 wCount = musb_readb(regs, MGC_O_HDRC_COUNT0);
611 DBG(4, "csr %04x, count %d, myaddr %d, ep0stage %s\n",
613 musb_readb(pBase, MGC_O_HDRC_FADDR),
614 decode_ep0stage(musb->ep0_state));
616 /* I sent a stall.. need to acknowledge it now.. */
617 if (wCsrVal & MGC_M_CSR0_P_SENTSTALL) {
618 musb_writew(regs, MGC_O_HDRC_CSR0,
619 wCsrVal & ~MGC_M_CSR0_P_SENTSTALL);
620 retval = IRQ_HANDLED;
621 musb->ep0_state = MGC_END0_STAGE_SETUP;
622 wCsrVal = musb_readw(regs, MGC_O_HDRC_CSR0);
625 /* request ended "early" */
626 if (wCsrVal & MGC_M_CSR0_P_SETUPEND) {
627 musb_writew(regs, MGC_O_HDRC_CSR0, MGC_M_CSR0_P_SVDSETUPEND);
628 retval = IRQ_HANDLED;
629 musb->ep0_state = MGC_END0_STAGE_SETUP;
630 wCsrVal = musb_readw(regs, MGC_O_HDRC_CSR0);
631 /* NOTE: request may need completion */
634 /* docs from Mentor only describe tx, rx, and idle/setup states.
635 * we need to handle nuances around status stages, and also the
636 * case where status and setup stages come back-to-back ...
638 switch (musb->ep0_state) {
640 case MGC_END0_STAGE_TX:
641 /* irq on clearing txpktrdy */
642 if ((wCsrVal & MGC_M_CSR0_TXPKTRDY) == 0) {
644 retval = IRQ_HANDLED;
648 case MGC_END0_STAGE_RX:
649 /* irq on set rxpktrdy */
650 if (wCsrVal & MGC_M_CSR0_RXPKTRDY) {
652 retval = IRQ_HANDLED;
656 case MGC_END0_STAGE_STATUSIN:
657 /* end of sequence #2 (OUT/RX state) or #3 (no data) */
659 /* update address (if needed) only @ the end of the
660 * status phase per usb spec, which also guarantees
661 * we get 10 msec to receive this irq... until this
662 * is done we won't see the next packet.
664 if (musb->bSetAddress) {
665 musb->bSetAddress = FALSE;
666 musb_writeb(pBase, MGC_O_HDRC_FADDR, musb->bAddress);
669 /* enter test mode if needed (exit by reset) */
670 else if (musb->bTestMode) {
671 DBG(1, "entering TESTMODE\n");
673 if (MGC_M_TEST_PACKET == musb->bTestModeValue)
674 musb_load_testpacket(musb);
676 musb_writeb(pBase, MGC_O_HDRC_TESTMODE,
677 musb->bTestModeValue);
681 case MGC_END0_STAGE_STATUSOUT:
682 /* end of sequence #1: write to host (TX state) */
684 struct usb_request *req;
686 req = next_ep0_request(musb);
688 musb_g_ep0_giveback(musb, req);
690 retval = IRQ_HANDLED;
691 musb->ep0_state = MGC_END0_STAGE_SETUP;
694 case MGC_END0_STAGE_SETUP:
695 if (wCsrVal & MGC_M_CSR0_RXPKTRDY) {
696 struct usb_ctrlrequest setup;
700 ERR("SETUP packet len %d != 8 ?\n", wCount);
703 musb_read_setup(musb, &setup);
704 retval = IRQ_HANDLED;
706 /* sometimes the RESET won't be reported */
707 if (unlikely(musb->g.speed == USB_SPEED_UNKNOWN)) {
710 printk(KERN_NOTICE "%s: peripheral reset "
713 power = musb_readb(pBase, MGC_O_HDRC_POWER);
714 musb->g.speed = (power & MGC_M_POWER_HSMODE)
715 ? USB_SPEED_HIGH : USB_SPEED_FULL;
719 switch (musb->ep0_state) {
721 /* sequence #3 (no data stage), includes requests
722 * we can't forward (notably SET_ADDRESS and the
723 * device/endpoint feature set/clear operations)
724 * plus SET_CONFIGURATION and others we must
726 case MGC_END0_STAGE_ACKWAIT:
727 handled = service_zero_data_request(
730 /* status stage might be immediate */
732 musb->ackpend |= MGC_M_CSR0_P_DATAEND;
734 MGC_END0_STAGE_STATUSIN;
738 /* sequence #1 (IN to host), includes GET_STATUS
739 * requests that we can't forward, GET_DESCRIPTOR
740 * and others that we must
742 case MGC_END0_STAGE_TX:
743 handled = service_in_request(musb, &setup);
745 musb->ackpend = MGC_M_CSR0_TXPKTRDY
746 | MGC_M_CSR0_P_DATAEND;
748 MGC_END0_STAGE_STATUSOUT;
752 /* sequence #2 (OUT from host), always forward */
753 default: /* MGC_END0_STAGE_RX */
757 DBG(3, "handled %d, csr %04x, ep0stage %s\n",
759 decode_ep0stage(musb->ep0_state));
761 /* unless we need to delegate this to the gadget
762 * driver, we know how to wrap this up: csr0 has
763 * not yet been written.
767 else if (handled > 0)
770 handled = forward_to_driver(musb, &setup);
772 MGC_SelectEnd(pBase, 0);
774 DBG(3, "stall (%d)\n", handled);
775 musb->ackpend |= MGC_M_CSR0_P_SENDSTALL;
776 musb->ep0_state = MGC_END0_STAGE_SETUP;
778 musb_writew(regs, MGC_O_HDRC_CSR0,
785 case MGC_END0_STAGE_ACKWAIT:
786 /* This should not happen. But happens with tusb6010 with
787 * g_file_storage and high speed. Do nothing.
789 retval = IRQ_HANDLED;
795 musb_writew(regs, MGC_O_HDRC_CSR0, MGC_M_CSR0_P_SENDSTALL);
796 musb->ep0_state = MGC_END0_STAGE_SETUP;
805 musb_g_ep0_enable(struct usb_ep *ep, const struct usb_endpoint_descriptor *desc)
811 static int musb_g_ep0_disable(struct usb_ep *e)
818 musb_g_ep0_queue(struct usb_ep *e, struct usb_request *r, gfp_t gfp_flags)
821 struct musb_request *req;
824 unsigned long lockflags;
832 regs = musb->control_ep->regs;
834 req = to_musb_request(r);
836 req->request.actual = 0;
837 req->request.status = -EINPROGRESS;
838 req->bTx = ep->is_in;
840 spin_lock_irqsave(&musb->Lock, lockflags);
842 if (!list_empty(&ep->req_list)) {
847 switch (musb->ep0_state) {
848 case MGC_END0_STAGE_RX: /* control-OUT data */
849 case MGC_END0_STAGE_TX: /* control-IN data */
850 case MGC_END0_STAGE_ACKWAIT: /* zero-length data */
854 DBG(1, "ep0 request queued in state %d\n",
860 /* add request to the list */
861 list_add_tail(&(req->request.list), &(ep->req_list));
863 DBG(3, "queue to %s (%s), length=%d\n",
864 ep->name, ep->is_in ? "IN/TX" : "OUT/RX",
865 req->request.length);
867 MGC_SelectEnd(musb->pRegs, 0);
869 /* sequence #1, IN ... start writing the data */
870 if (musb->ep0_state == MGC_END0_STAGE_TX)
873 /* sequence #3, no-data ... issue IN status */
874 else if (musb->ep0_state == MGC_END0_STAGE_ACKWAIT) {
875 if (req->request.length)
878 musb->ep0_state = MGC_END0_STAGE_STATUSIN;
879 musb_writew(regs, MGC_O_HDRC_CSR0,
880 musb->ackpend | MGC_M_CSR0_P_DATAEND);
882 musb_g_ep0_giveback(ep->pThis, r);
885 /* else for sequence #2 (OUT), caller provides a buffer
886 * before the next packet arrives. deferred responses
887 * (after SETUP is acked) are racey.
889 } else if (musb->ackpend) {
890 musb_writew(regs, MGC_O_HDRC_CSR0, musb->ackpend);
895 spin_unlock_irqrestore(&musb->Lock, lockflags);
900 musb_g_ep0_dequeue(struct usb_ep *ep, struct usb_request *req)
902 /* we just won't support this */
906 static int musb_g_ep0_halt(struct usb_ep *e, int value)
910 void __iomem *base, *regs;
921 regs = musb->control_ep->regs;
923 spin_lock_irqsave(&musb->Lock, flags);
925 if (!list_empty(&ep->req_list)) {
930 switch (musb->ep0_state) {
931 case MGC_END0_STAGE_TX: /* control-IN data */
932 case MGC_END0_STAGE_ACKWAIT: /* STALL for zero-length data */
933 case MGC_END0_STAGE_RX: /* control-OUT data */
936 MGC_SelectEnd(base, 0);
937 csr = musb_readw(regs, MGC_O_HDRC_CSR0);
938 csr |= MGC_M_CSR0_P_SENDSTALL;
939 musb_writew(regs, MGC_O_HDRC_CSR0, csr);
940 musb->ep0_state = MGC_END0_STAGE_SETUP;
943 DBG(1, "ep0 can't halt in state %d\n", musb->ep0_state);
948 spin_unlock_irqrestore(&musb->Lock, flags);
952 const struct usb_ep_ops musb_g_ep0_ops = {
953 .enable = musb_g_ep0_enable,
954 .disable = musb_g_ep0_disable,
955 .alloc_request = musb_alloc_request,
956 .free_request = musb_free_request,
957 .queue = musb_g_ep0_queue,
958 .dequeue = musb_g_ep0_dequeue,
959 .set_halt = musb_g_ep0_halt,