2 * Copyright (C) 2005-2006 by Texas Instruments
4 * This file is part of the Inventra Controller Driver for Linux.
6 * The Inventra Controller Driver for Linux is free software; you
7 * can redistribute it and/or modify it under the terms of the GNU
8 * General Public License version 2 as published by the Free Software
11 * The Inventra Controller Driver for Linux is distributed in
12 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
13 * without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 * License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with The Inventra Controller Driver for Linux ; if not,
19 * write to the Free Software Foundation, Inc., 59 Temple Place,
20 * Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
27 #include <linux/slab.h>
28 #include <linux/init.h>
29 #include <linux/list.h>
30 #include <linux/delay.h>
31 #include <linux/clk.h>
33 #include <linux/gpio.h>
35 #include <asm/arch/hardware.h>
36 #include <asm/arch/memory.h>
37 #include <asm/arch/gpio.h>
38 #include <asm/mach-types.h>
40 #include "musb_core.h"
42 #ifdef CONFIG_MACH_DAVINCI_EVM
43 #define GPIO_nVBUS_DRV 87
50 /* REVISIT (PM) we should be able to keep the PHY in low power mode most
51 * of the time (24 MHZ oscillator and PLL off, etc) by setting POWER.D0
52 * and, when in host mode, autosuspending idle root ports... PHYPLLON
53 * (overriding SUSPENDM?) then likely needs to stay off.
56 static inline void phy_on(void)
58 /* start the on-chip PHY and its PLL */
59 __raw_writel(USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON,
60 (void __force __iomem *) IO_ADDRESS(USBPHY_CTL_PADDR));
61 while ((__raw_readl((void __force __iomem *)
62 IO_ADDRESS(USBPHY_CTL_PADDR))
63 & USBPHY_PHYCLKGD) == 0)
67 static inline void phy_off(void)
69 /* powerdown the on-chip PHY and its oscillator */
70 __raw_writel(USBPHY_OSCPDWN | USBPHY_PHYPDWN, (void __force __iomem *)
71 IO_ADDRESS(USBPHY_CTL_PADDR));
74 static int dma_off = 1;
76 void musb_platform_enable(struct musb *musb)
80 /* workaround: setup irqs through both register sets */
81 tmp = (musb->epmask & DAVINCI_USB_TX_ENDPTS_MASK)
82 << DAVINCI_USB_TXINT_SHIFT;
83 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
85 tmp = (musb->epmask & (0xfffe & DAVINCI_USB_RX_ENDPTS_MASK))
86 << DAVINCI_USB_RXINT_SHIFT;
87 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
91 tmp |= ((val & 0x01ff) << DAVINCI_USB_USBINT_SHIFT);
92 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
94 if (is_dma_capable() && !dma_off)
95 printk(KERN_WARNING "%s %s: dma not reactivated\n",
100 /* force a DRVVBUS irq so we can start polling for ID change */
101 if (is_otg_enabled(musb))
102 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
103 DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT);
107 * Disable the HDRC and flush interrupts
109 void musb_platform_disable(struct musb *musb)
111 /* because we don't set CTRLR.UINT, "important" to:
112 * - not read/write INTRUSB/INTRUSBE
113 * - (except during initial setup, as workaround)
114 * - use INTSETR/INTCLRR instead
116 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_CLR_REG,
117 DAVINCI_USB_USBINT_MASK
118 | DAVINCI_USB_TXINT_MASK
119 | DAVINCI_USB_RXINT_MASK);
120 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
121 musb_writel(musb->ctrl_base, DAVINCI_USB_EOI_REG, 0);
123 if (is_dma_capable() && !dma_off)
124 WARNING("dma still active\n");
128 /* REVISIT it's not clear whether DaVinci can support full OTG. */
130 static int vbus_state = -1;
132 #ifdef CONFIG_USB_MUSB_HDRC_HCD
133 #define portstate(stmt) stmt
135 #define portstate(stmt)
139 /* VBUS SWITCHING IS BOARD-SPECIFIC */
141 #ifdef CONFIG_MACH_DAVINCI_EVM
143 /* I2C operations are always synchronous, and require a task context.
144 * With unloaded systems, using the shared workqueue seems to suffice
145 * to satisfy the 100msec A_WAIT_VRISE timeout...
147 static void evm_deferred_drvvbus(struct work_struct *ignored)
149 gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state);
150 vbus_state = !vbus_state;
152 static DECLARE_WORK(evm_vbus_work, evm_deferred_drvvbus);
156 static void davinci_source_power(struct musb *musb, int is_on, int immediate)
161 if (vbus_state == is_on)
163 vbus_state = !is_on; /* 0/1 vs "-1 == unknown/init" */
165 #ifdef CONFIG_MACH_DAVINCI_EVM
166 if (machine_is_davinci_evm()) {
168 gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state);
170 schedule_work(&evm_vbus_work);
177 static void davinci_set_vbus(struct musb *musb, int is_on)
179 WARN_ON(is_on && is_peripheral_active(musb));
180 davinci_source_power(musb, is_on, 0);
184 #define POLL_SECONDS 2
186 static struct timer_list otg_workaround;
188 static void otg_timer(unsigned long _musb)
190 struct musb *musb = (void *)_musb;
191 void __iomem *mregs = musb->mregs;
195 /* We poll because DaVinci's won't expose several OTG-critical
196 * status change events (from the transceiver) otherwise.
198 devctl = musb_readb(mregs, MUSB_DEVCTL);
199 DBG(7, "poll devctl %02x (%s)\n", devctl, otg_state_string(musb));
201 spin_lock_irqsave(&musb->lock, flags);
202 switch (musb->xceiv.state) {
203 case OTG_STATE_A_WAIT_VFALL:
204 /* Wait till VBUS falls below SessionEnd (~0.2V); the 1.3 RTL
205 * seems to mis-handle session "start" otherwise (or in our
206 * case "recover"), in routine "VBUS was valid by the time
207 * VBUSERR got reported during enumeration" cases.
209 if (devctl & MUSB_DEVCTL_VBUS) {
210 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
213 musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
214 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
215 MUSB_INTR_VBUSERROR << DAVINCI_USB_USBINT_SHIFT);
217 case OTG_STATE_B_IDLE:
218 if (!is_peripheral_enabled(musb))
221 /* There's no ID-changed IRQ, so we have no good way to tell
222 * when to switch to the A-Default state machine (by setting
223 * the DEVCTL.SESSION flag).
225 * Workaround: whenever we're in B_IDLE, try setting the
226 * session flag every few seconds. If it works, ID was
227 * grounded and we're now in the A-Default state machine.
229 * NOTE setting the session flag is _supposed_ to trigger
230 * SRP, but clearly it doesn't.
232 musb_writeb(mregs, MUSB_DEVCTL,
233 devctl | MUSB_DEVCTL_SESSION);
234 devctl = musb_readb(mregs, MUSB_DEVCTL);
235 if (devctl & MUSB_DEVCTL_BDEVICE)
236 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
238 musb->xceiv.state = OTG_STATE_A_IDLE;
243 spin_unlock_irqrestore(&musb->lock, flags);
246 static irqreturn_t davinci_interrupt(int irq, void *__hci)
249 irqreturn_t retval = IRQ_NONE;
250 struct musb *musb = __hci;
251 void __iomem *tibase = musb->ctrl_base;
254 spin_lock_irqsave(&musb->lock, flags);
256 /* NOTE: DaVinci shadows the Mentor IRQs. Don't manage them through
257 * the Mentor registers (except for setup), use the TI ones and EOI.
259 * Docs describe irq "vector" registers asociated with the CPPI and
260 * USB EOI registers. These hold a bitmask corresponding to the
261 * current IRQ, not an irq handler address. Would using those bits
262 * resolve some of the races observed in this dispatch code??
265 /* CPPI interrupts share the same IRQ line, but have their own
266 * mask, state, "vector", and EOI registers.
268 if (is_cppi_enabled()) {
269 u32 cppi_tx = musb_readl(tibase, DAVINCI_TXCPPI_MASKED_REG);
270 u32 cppi_rx = musb_readl(tibase, DAVINCI_RXCPPI_MASKED_REG);
272 if (cppi_tx || cppi_rx) {
273 DBG(4, "CPPI IRQ t%x r%x\n", cppi_tx, cppi_rx);
274 cppi_completion(musb, cppi_rx, cppi_tx);
275 retval = IRQ_HANDLED;
279 /* ack and handle non-CPPI interrupts */
280 tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG);
281 musb_writel(tibase, DAVINCI_USB_INT_SRC_CLR_REG, tmp);
282 DBG(4, "IRQ %08x\n", tmp);
284 musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK)
285 >> DAVINCI_USB_RXINT_SHIFT;
286 musb->int_tx = (tmp & DAVINCI_USB_TXINT_MASK)
287 >> DAVINCI_USB_TXINT_SHIFT;
288 musb->int_usb = (tmp & DAVINCI_USB_USBINT_MASK)
289 >> DAVINCI_USB_USBINT_SHIFT;
291 /* DRVVBUS irqs are the only proxy we have (a very poor one!) for
292 * DaVinci's missing ID change IRQ. We need an ID change IRQ to
293 * switch appropriately between halves of the OTG state machine.
294 * Managing DEVCTL.SESSION per Mentor docs requires we know its
295 * value, but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
296 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
298 if (tmp & (DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT)) {
299 int drvvbus = musb_readl(tibase, DAVINCI_USB_STAT_REG);
300 void __iomem *mregs = musb->mregs;
301 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
302 int err = musb->int_usb & MUSB_INTR_VBUSERROR;
304 err = is_host_enabled(musb)
305 && (musb->int_usb & MUSB_INTR_VBUSERROR);
307 /* The Mentor core doesn't debounce VBUS as needed
308 * to cope with device connect current spikes. This
309 * means it's not uncommon for bus-powered devices
310 * to get VBUS errors during enumeration.
312 * This is a workaround, but newer RTL from Mentor
313 * seems to allow a better one: "re"starting sessions
314 * without waiting (on EVM, a **long** time) for VBUS
315 * to stop registering in devctl.
317 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
318 musb->xceiv.state = OTG_STATE_A_WAIT_VFALL;
319 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
320 WARNING("VBUS error workaround (delay coming)\n");
321 } else if (is_host_enabled(musb) && drvvbus) {
324 musb->xceiv.default_a = 1;
325 musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
326 portstate(musb->port1_status |= USB_PORT_STAT_POWER);
327 del_timer(&otg_workaround);
331 musb->xceiv.default_a = 0;
332 musb->xceiv.state = OTG_STATE_B_IDLE;
333 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
336 /* NOTE: this must complete poweron within 100 msec */
337 davinci_source_power(musb, drvvbus, 0);
338 DBG(2, "VBUS %s (%s)%s, devctl %02x\n",
339 drvvbus ? "on" : "off",
340 otg_state_string(musb),
343 retval = IRQ_HANDLED;
346 if (musb->int_tx || musb->int_rx || musb->int_usb)
347 retval |= musb_interrupt(musb);
349 /* irq stays asserted until EOI is written */
350 musb_writel(tibase, DAVINCI_USB_EOI_REG, 0);
352 /* poll for ID change */
353 if (is_otg_enabled(musb)
354 && musb->xceiv.state == OTG_STATE_B_IDLE)
355 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
357 spin_unlock_irqrestore(&musb->lock, flags);
359 /* REVISIT we sometimes get unhandled IRQs
360 * (e.g. ep0). not clear why...
362 if (retval != IRQ_HANDLED)
363 DBG(5, "unhandled? %08x\n", tmp);
367 int __init musb_platform_init(struct musb *musb)
369 void __iomem *tibase = musb->ctrl_base;
372 musb->mregs += DAVINCI_BASE_OFFSET;
374 /* REVISIT there's something odd about clocking, this
375 * didn't appear do the job ...
377 musb->clock = clk_get(pDevice, "usb");
378 if (IS_ERR(musb->clock))
379 return PTR_ERR(musb->clock);
381 status = clk_enable(musb->clock);
386 /* returns zero if e.g. not clocked */
387 revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG);
391 if (is_host_enabled(musb))
392 setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
394 musb->board_set_vbus = davinci_set_vbus;
395 davinci_source_power(musb, 0, 1);
397 /* reset the controller */
398 musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1);
400 /* start the on-chip PHY and its PLL */
405 /* NOTE: irqs are in mixed mode, not bypass to pure-musb */
406 pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n",
407 revision, __raw_readl((void __force __iomem *)
408 IO_ADDRESS(USBPHY_CTL_PADDR)),
409 musb_readb(tibase, DAVINCI_USB_CTRL_REG));
411 musb->isr = davinci_interrupt;
415 int musb_platform_exit(struct musb *musb)
417 if (is_host_enabled(musb))
418 del_timer_sync(&otg_workaround);
420 davinci_source_power(musb, 0 /*off*/, 1);
422 /* delay, to avoid problems with module reload */
423 if (is_host_enabled(musb) && musb->xceiv.default_a) {
427 /* if there's no peripheral connected, this can take a
428 * long time to fall, especially on EVM with huge C133.
431 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
432 if (!(devctl & MUSB_DEVCTL_VBUS))
434 if ((devctl & MUSB_DEVCTL_VBUS) != warn) {
435 warn = devctl & MUSB_DEVCTL_VBUS;
437 warn >> MUSB_DEVCTL_VBUS_SHIFT);
441 } while (maxdelay > 0);
443 /* in OTG mode, another host might be connected */
444 if (devctl & MUSB_DEVCTL_VBUS)
445 DBG(1, "VBUS off timeout (devctl %02x)\n", devctl);