2 * Copyright (C) 2005-2006 by Texas Instruments
4 * This file is part of the Inventra Controller Driver for Linux.
6 * The Inventra Controller Driver for Linux is free software; you
7 * can redistribute it and/or modify it under the terms of the GNU
8 * General Public License version 2 as published by the Free Software
11 * The Inventra Controller Driver for Linux is distributed in
12 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
13 * without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 * License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with The Inventra Controller Driver for Linux ; if not,
19 * write to the Free Software Foundation, Inc., 59 Temple Place,
20 * Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
27 #include <linux/slab.h>
28 #include <linux/init.h>
29 #include <linux/list.h>
30 #include <linux/delay.h>
31 #include <linux/clk.h>
34 #include <asm/arch/hardware.h>
35 #include <asm/arch/memory.h>
36 #include <asm/arch/gpio.h>
37 #include <asm/mach-types.h>
39 #include "musb_core.h"
42 #ifdef CONFIG_MACH_DAVINCI_EVM
43 #include <asm/arch/i2c-client.h>
50 /* REVISIT (PM) we should be able to keep the PHY in low power mode most
51 * of the time (24 MHZ oscillator and PLL off, etc) by setting POWER.D0
52 * and, when in host mode, autosuspending idle root ports... PHYPLLON
53 * (overriding SUSPENDM?) then likely needs to stay off.
56 static inline void phy_on(void)
58 /* start the on-chip PHY and its PLL */
59 __raw_writel(USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON,
60 (void __force __iomem *) IO_ADDRESS(USBPHY_CTL_PADDR));
61 while ((__raw_readl((void __force __iomem *)
62 IO_ADDRESS(USBPHY_CTL_PADDR))
63 & USBPHY_PHYCLKGD) == 0)
67 static inline void phy_off(void)
69 /* powerdown the on-chip PHY and its oscillator */
70 __raw_writel(USBPHY_OSCPDWN | USBPHY_PHYPDWN, (void __force __iomem *)
71 IO_ADDRESS(USBPHY_CTL_PADDR));
74 static int dma_off = 1;
76 void musb_platform_enable(struct musb *musb)
80 /* workaround: setup irqs through both register sets */
81 tmp = (musb->epmask & DAVINCI_USB_TX_ENDPTS_MASK)
82 << DAVINCI_USB_TXINT_SHIFT;
83 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
85 tmp = (musb->epmask & (0xfffe & DAVINCI_USB_RX_ENDPTS_MASK))
86 << DAVINCI_USB_RXINT_SHIFT;
87 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
91 tmp |= ((val & 0x01ff) << DAVINCI_USB_USBINT_SHIFT);
92 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
94 if (is_dma_capable() && !dma_off)
95 printk(KERN_WARNING "%s %s: dma not reactivated\n",
96 __FILE__, __FUNCTION__);
100 /* force a DRVVBUS irq so we can start polling for ID change */
101 if (is_otg_enabled(musb))
102 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
103 DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT);
107 * Disable the HDRC and flush interrupts
109 void musb_platform_disable(struct musb *musb)
111 /* because we don't set CTRLR.UINT, "important" to:
112 * - not read/write INTRUSB/INTRUSBE
113 * - (except during initial setup, as workaround)
114 * - use INTSETR/INTCLRR instead
116 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_CLR_REG,
117 DAVINCI_USB_USBINT_MASK
118 | DAVINCI_USB_TXINT_MASK
119 | DAVINCI_USB_RXINT_MASK);
120 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
121 musb_writel(musb->ctrl_base, DAVINCI_USB_EOI_REG, 0);
123 if (is_dma_capable() && !dma_off)
124 WARN("dma still active\n");
128 /* REVISIT it's not clear whether DaVinci can support full OTG. */
130 static int vbus_state = -1;
132 #ifdef CONFIG_USB_MUSB_HDRC_HCD
133 #define portstate(stmt) stmt
135 #define portstate(stmt)
139 /* VBUS SWITCHING IS BOARD-SPECIFIC */
141 #ifdef CONFIG_MACH_DAVINCI_EVM
142 #ifndef CONFIG_MACH_DAVINCI_EVM_OTG
144 /* I2C operations are always synchronous, and require a task context.
145 * With unloaded systems, using the shared workqueue seems to suffice
146 * to satisfy the 100msec A_WAIT_VRISE timeout...
148 static void evm_deferred_drvvbus(struct work_struct *ignored)
150 davinci_i2c_expander_op(0x3a, USB_DRVVBUS, vbus_state);
151 vbus_state = !vbus_state;
153 static DECLARE_WORK(evm_vbus_work, evm_deferred_drvvbus);
155 #endif /* modified board */
158 static void davinci_source_power(struct musb *musb, int is_on, int immediate)
163 if (vbus_state == is_on)
165 vbus_state = !is_on; /* 0/1 vs "-1 == unknown/init" */
167 #ifdef CONFIG_MACH_DAVINCI_EVM
168 if (machine_is_davinci_evm()) {
169 #ifdef CONFIG_MACH_DAVINCI_EVM_OTG
170 /* modified EVM board switching VBUS with GPIO(6) not I2C
171 * NOTE: PINMUX0.RGB888 (bit23) must be clear
180 davinci_i2c_expander_op(0x3a, USB_DRVVBUS, !is_on);
182 schedule_work(&evm_vbus_work);
190 static void davinci_set_vbus(struct musb *musb, int is_on)
192 WARN_ON(is_on && is_peripheral_active(musb));
193 davinci_source_power(musb, is_on, 0);
197 #define POLL_SECONDS 2
199 static struct timer_list otg_workaround;
201 static void otg_timer(unsigned long _musb)
203 struct musb *musb = (void *)_musb;
204 void __iomem *mregs = musb->mregs;
208 /* We poll because DaVinci's won't expose several OTG-critical
209 * status change events (from the transceiver) otherwise.
211 devctl = musb_readb(mregs, MUSB_DEVCTL);
212 DBG(7, "poll devctl %02x (%s)\n", devctl, otg_state_string(musb));
214 spin_lock_irqsave(&musb->lock, flags);
215 switch (musb->xceiv.state) {
216 case OTG_STATE_A_WAIT_VFALL:
217 /* Wait till VBUS falls below SessionEnd (~0.2V); the 1.3 RTL
218 * seems to mis-handle session "start" otherwise (or in our
219 * case "recover"), in routine "VBUS was valid by the time
220 * VBUSERR got reported during enumeration" cases.
222 if (devctl & MUSB_DEVCTL_VBUS) {
223 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
226 musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
227 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
228 MUSB_INTR_VBUSERROR << DAVINCI_USB_USBINT_SHIFT);
230 case OTG_STATE_B_IDLE:
231 if (!is_peripheral_enabled(musb))
234 /* There's no ID-changed IRQ, so we have no good way to tell
235 * when to switch to the A-Default state machine (by setting
236 * the DEVCTL.SESSION flag).
238 * Workaround: whenever we're in B_IDLE, try setting the
239 * session flag every few seconds. If it works, ID was
240 * grounded and we're now in the A-Default state machine.
242 * NOTE setting the session flag is _supposed_ to trigger
243 * SRP, but clearly it doesn't.
245 musb_writeb(mregs, MUSB_DEVCTL,
246 devctl | MUSB_DEVCTL_SESSION);
247 devctl = musb_readb(mregs, MUSB_DEVCTL);
248 if (devctl & MUSB_DEVCTL_BDEVICE)
249 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
251 musb->xceiv.state = OTG_STATE_A_IDLE;
256 spin_unlock_irqrestore(&musb->lock, flags);
259 static irqreturn_t davinci_interrupt(int irq, void *__hci)
262 irqreturn_t retval = IRQ_NONE;
263 struct musb *musb = __hci;
264 void __iomem *tibase = musb->ctrl_base;
267 spin_lock_irqsave(&musb->lock, flags);
269 /* NOTE: DaVinci shadows the Mentor IRQs. Don't manage them through
270 * the Mentor registers (except for setup), use the TI ones and EOI.
272 * Docs describe irq "vector" registers asociated with the CPPI and
273 * USB EOI registers. These hold a bitmask corresponding to the
274 * current IRQ, not an irq handler address. Would using those bits
275 * resolve some of the races observed in this dispatch code??
278 /* CPPI interrupts share the same IRQ line, but have their own
279 * mask, state, "vector", and EOI registers.
281 if (is_cppi_enabled()) {
282 u32 cppi_tx = musb_readl(tibase, DAVINCI_TXCPPI_MASKED_REG);
283 u32 cppi_rx = musb_readl(tibase, DAVINCI_RXCPPI_MASKED_REG);
285 if (cppi_tx || cppi_rx) {
286 DBG(4, "CPPI IRQ t%x r%x\n", cppi_tx, cppi_rx);
287 cppi_completion(musb, cppi_rx, cppi_tx);
288 retval = IRQ_HANDLED;
292 /* ack and handle non-CPPI interrupts */
293 tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG);
294 musb_writel(tibase, DAVINCI_USB_INT_SRC_CLR_REG, tmp);
295 DBG(4, "IRQ %08x\n", tmp);
297 musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK)
298 >> DAVINCI_USB_RXINT_SHIFT;
299 musb->int_tx = (tmp & DAVINCI_USB_TXINT_MASK)
300 >> DAVINCI_USB_TXINT_SHIFT;
301 musb->int_usb = (tmp & DAVINCI_USB_USBINT_MASK)
302 >> DAVINCI_USB_USBINT_SHIFT;
304 /* DRVVBUS irqs are the only proxy we have (a very poor one!) for
305 * DaVinci's missing ID change IRQ. We need an ID change IRQ to
306 * switch appropriately between halves of the OTG state machine.
307 * Managing DEVCTL.SESSION per Mentor docs requires we know its
308 * value, but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
309 * Also, DRVVBUS pulses for SRP (but not at 5V) ...
311 if (tmp & (DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT)) {
312 int drvvbus = musb_readl(tibase, DAVINCI_USB_STAT_REG);
313 void __iomem *mregs = musb->mregs;
314 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
315 int err = musb->int_usb & MUSB_INTR_VBUSERROR;
317 err = is_host_enabled(musb)
318 && (musb->int_usb & MUSB_INTR_VBUSERROR);
320 /* The Mentor core doesn't debounce VBUS as needed
321 * to cope with device connect current spikes. This
322 * means it's not uncommon for bus-powered devices
323 * to get VBUS errors during enumeration.
325 * This is a workaround, but newer RTL from Mentor
326 * seems to allow a better one: "re"starting sessions
327 * without waiting (on EVM, a **long** time) for VBUS
328 * to stop registering in devctl.
330 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
331 musb->xceiv.state = OTG_STATE_A_WAIT_VFALL;
332 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
333 WARN("VBUS error workaround (delay coming)\n");
334 } else if (is_host_enabled(musb) && drvvbus) {
337 musb->xceiv.default_a = 1;
338 musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
339 portstate(musb->port1_status |= USB_PORT_STAT_POWER);
340 del_timer(&otg_workaround);
344 musb->xceiv.default_a = 0;
345 musb->xceiv.state = OTG_STATE_B_IDLE;
346 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
349 /* NOTE: this must complete poweron within 100 msec */
350 davinci_source_power(musb, drvvbus, 0);
351 DBG(2, "VBUS %s (%s)%s, devctl %02x\n",
352 drvvbus ? "on" : "off",
353 otg_state_string(musb),
356 retval = IRQ_HANDLED;
359 if (musb->int_tx || musb->int_rx || musb->int_usb)
360 retval |= musb_interrupt(musb);
362 /* irq stays asserted until EOI is written */
363 musb_writel(tibase, DAVINCI_USB_EOI_REG, 0);
365 /* poll for ID change */
366 if (is_otg_enabled(musb)
367 && musb->xceiv.state == OTG_STATE_B_IDLE)
368 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
370 spin_unlock_irqrestore(&musb->lock, flags);
372 /* REVISIT we sometimes get unhandled IRQs
373 * (e.g. ep0). not clear why...
375 if (retval != IRQ_HANDLED)
376 DBG(5, "unhandled? %08x\n", tmp);
380 int __init musb_platform_init(struct musb *musb)
382 void __iomem *tibase = musb->ctrl_base;
385 musb->mregs += DAVINCI_BASE_OFFSET;
387 /* REVISIT there's something odd about clocking, this
388 * didn't appear do the job ...
390 musb->clock = clk_get(pDevice, "usb");
391 if (IS_ERR(musb->clock))
392 return PTR_ERR(musb->clock);
394 status = clk_enable(musb->clock);
399 /* returns zero if e.g. not clocked */
400 revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG);
404 if (is_host_enabled(musb))
405 setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
407 musb->board_set_vbus = davinci_set_vbus;
408 davinci_source_power(musb, 0, 1);
410 /* reset the controller */
411 musb_writel(tibase, DAVINCI_USB_CTRL_REG, 0x1);
413 /* start the on-chip PHY and its PLL */
418 /* NOTE: irqs are in mixed mode, not bypass to pure-musb */
419 pr_debug("DaVinci OTG revision %08x phy %03x control %02x\n",
420 revision, __raw_readl((void __force __iomem *)
421 IO_ADDRESS(USBPHY_CTL_PADDR)),
422 musb_readb(tibase, DAVINCI_USB_CTRL_REG));
424 musb->isr = davinci_interrupt;
428 int musb_platform_exit(struct musb *musb)
430 if (is_host_enabled(musb))
431 del_timer_sync(&otg_workaround);
433 davinci_source_power(musb, 0 /*off*/, 1);
435 /* delay, to avoid problems with module reload */
436 if (is_host_enabled(musb) && musb->xceiv.default_a) {
440 /* if there's no peripheral connected, this can take a
441 * long time to fall, especially on EVM with huge C133.
444 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
445 if (!(devctl & MUSB_DEVCTL_VBUS))
447 if ((devctl & MUSB_DEVCTL_VBUS) != warn) {
448 warn = devctl & MUSB_DEVCTL_VBUS;
449 DBG(1, "VBUS %d\n", warn >> MUSB_DEVCTL_VBUS_SHIFT);
453 } while (maxdelay > 0);
455 /* in OTG mode, another host might be connected */
456 if (devctl & MUSB_DEVCTL_VBUS)
457 DBG(1, "VBUS off timeout (devctl %02x)\n", devctl);