2 * OHCI HCD (Host Controller Driver) for USB.
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
6 * (C) Copyright 2002 Hewlett-Packard Company
10 * Written by Christopher Hoover <ch@hpl.hp.com>
11 * Based on fragments of previous driver by Russell King et al.
13 * Modified for LH7A404 from ohci-sa1111.c
14 * by Durgesh Pattamatta <pattamattad@sharpsec.com>
16 * Modified for pxa27x from ohci-lh7a404.c
17 * by Nick Bane <nick@cecomputing.co.uk> 26-8-2004
19 * This file is licenced under the GPL.
22 #include <linux/device.h>
23 #include <linux/signal.h>
24 #include <linux/platform_device.h>
25 #include <linux/clk.h>
27 #include <mach/hardware.h>
28 #include <mach/pxa2xx-regs.h> /* FIXME: for PSSR */
29 #include <mach/ohci.h>
32 * UHC: USB Host Controller (OHCI-like) register definitions
34 #define UHC_BASE_PHYS (0x4C000000)
35 #define UHCREV __REG(0x4C000000) /* UHC HCI Spec Revision */
36 #define UHCHCON __REG(0x4C000004) /* UHC Host Control Register */
37 #define UHCCOMS __REG(0x4C000008) /* UHC Command Status Register */
38 #define UHCINTS __REG(0x4C00000C) /* UHC Interrupt Status Register */
39 #define UHCINTE __REG(0x4C000010) /* UHC Interrupt Enable */
40 #define UHCINTD __REG(0x4C000014) /* UHC Interrupt Disable */
41 #define UHCHCCA __REG(0x4C000018) /* UHC Host Controller Comm. Area */
42 #define UHCPCED __REG(0x4C00001C) /* UHC Period Current Endpt Descr */
43 #define UHCCHED __REG(0x4C000020) /* UHC Control Head Endpt Descr */
44 #define UHCCCED __REG(0x4C000024) /* UHC Control Current Endpt Descr */
45 #define UHCBHED __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */
46 #define UHCBCED __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */
47 #define UHCDHEAD __REG(0x4C000030) /* UHC Done Head */
48 #define UHCFMI __REG(0x4C000034) /* UHC Frame Interval */
49 #define UHCFMR __REG(0x4C000038) /* UHC Frame Remaining */
50 #define UHCFMN __REG(0x4C00003C) /* UHC Frame Number */
51 #define UHCPERS __REG(0x4C000040) /* UHC Periodic Start */
52 #define UHCLS __REG(0x4C000044) /* UHC Low Speed Threshold */
54 #define UHCRHDA __REG(0x4C000048) /* UHC Root Hub Descriptor A */
55 #define UHCRHDA_NOCP (1 << 12) /* No over current protection */
56 #define UHCRHDA_OCPM (1 << 11) /* Over Current Protection Mode */
57 #define UHCRHDA_POTPGT(x) \
58 (((x) & 0xff) << 24) /* Power On To Power Good Time */
60 #define UHCRHDB __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
61 #define UHCRHS __REG(0x4C000050) /* UHC Root Hub Status */
62 #define UHCRHPS1 __REG(0x4C000054) /* UHC Root Hub Port 1 Status */
63 #define UHCRHPS2 __REG(0x4C000058) /* UHC Root Hub Port 2 Status */
64 #define UHCRHPS3 __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */
66 #define UHCSTAT __REG(0x4C000060) /* UHC Status Register */
67 #define UHCSTAT_UPS3 (1 << 16) /* USB Power Sense Port3 */
68 #define UHCSTAT_SBMAI (1 << 15) /* System Bus Master Abort Interrupt*/
69 #define UHCSTAT_SBTAI (1 << 14) /* System Bus Target Abort Interrupt*/
70 #define UHCSTAT_UPRI (1 << 13) /* USB Port Resume Interrupt */
71 #define UHCSTAT_UPS2 (1 << 12) /* USB Power Sense Port 2 */
72 #define UHCSTAT_UPS1 (1 << 11) /* USB Power Sense Port 1 */
73 #define UHCSTAT_HTA (1 << 10) /* HCI Target Abort */
74 #define UHCSTAT_HBA (1 << 8) /* HCI Buffer Active */
75 #define UHCSTAT_RWUE (1 << 7) /* HCI Remote Wake Up Event */
77 #define UHCHR __REG(0x4C000064) /* UHC Reset Register */
78 #define UHCHR_SSEP3 (1 << 11) /* Sleep Standby Enable for Port3 */
79 #define UHCHR_SSEP2 (1 << 10) /* Sleep Standby Enable for Port2 */
80 #define UHCHR_SSEP1 (1 << 9) /* Sleep Standby Enable for Port1 */
81 #define UHCHR_PCPL (1 << 7) /* Power control polarity low */
82 #define UHCHR_PSPL (1 << 6) /* Power sense polarity low */
83 #define UHCHR_SSE (1 << 5) /* Sleep Standby Enable */
84 #define UHCHR_UIT (1 << 4) /* USB Interrupt Test */
85 #define UHCHR_SSDC (1 << 3) /* Simulation Scale Down Clock */
86 #define UHCHR_CGR (1 << 2) /* Clock Generation Reset */
87 #define UHCHR_FHR (1 << 1) /* Force Host Controller Reset */
88 #define UHCHR_FSBIR (1 << 0) /* Force System Bus Iface Reset */
90 #define UHCHIE __REG(0x4C000068) /* UHC Interrupt Enable Register*/
91 #define UHCHIE_UPS3IE (1 << 14) /* Power Sense Port3 IntEn */
92 #define UHCHIE_UPRIE (1 << 13) /* Port Resume IntEn */
93 #define UHCHIE_UPS2IE (1 << 12) /* Power Sense Port2 IntEn */
94 #define UHCHIE_UPS1IE (1 << 11) /* Power Sense Port1 IntEn */
95 #define UHCHIE_TAIE (1 << 10) /* HCI Interface Transfer Abort
97 #define UHCHIE_HBAIE (1 << 8) /* HCI Buffer Active IntEn */
98 #define UHCHIE_RWIE (1 << 7) /* Remote Wake-up IntEn */
100 #define UHCHIT __REG(0x4C00006C) /* UHC Interrupt Test register */
103 #define PXA_UHC_MAX_PORTNUM 3
105 #define UHCRHPS(x) __REG2( 0x4C000050, (x)<<2 )
107 static struct clk *usb_clk;
110 PMM_NPS_MODE -- PMM Non-power switching mode
111 Ports are powered continuously.
113 PMM_GLOBAL_MODE -- PMM global switching mode
114 All ports are powered at the same time.
116 PMM_PERPORT_MODE -- PMM per port switching mode
117 Ports are powered individually.
119 static int pxa27x_ohci_select_pmm( int mode )
125 case PMM_GLOBAL_MODE:
126 UHCRHDA &= ~(RH_A_NPS & RH_A_PSM);
128 case PMM_PERPORT_MODE:
129 UHCRHDA &= ~(RH_A_NPS);
132 /* Set port power control mask bits, only 3 ports. */
133 UHCRHDB |= (0x7<<17);
137 "Invalid mode %d, set to non-power switch mode.\n",
146 extern int usb_disabled(void);
148 /*-------------------------------------------------------------------------*/
150 static inline void pxa27x_setup_hc(struct pxaohci_platform_data *inf)
152 uint32_t uhchr = UHCHR;
153 uint32_t uhcrhda = UHCRHDA;
155 if (inf->flags & ENABLE_PORT1)
156 uhchr &= ~UHCHR_SSEP1;
158 if (inf->flags & ENABLE_PORT2)
159 uhchr &= ~UHCHR_SSEP2;
161 if (inf->flags & ENABLE_PORT3)
162 uhchr &= ~UHCHR_SSEP3;
164 if (inf->flags & POWER_CONTROL_LOW)
167 if (inf->flags & POWER_SENSE_LOW)
170 if (inf->flags & NO_OC_PROTECTION)
171 uhcrhda |= UHCRHDA_NOCP;
173 if (inf->flags & OC_MODE_PERPORT)
174 uhcrhda |= UHCRHDA_OCPM;
176 if (inf->power_on_delay) {
177 uhcrhda &= ~UHCRHDA_POTPGT(0xff);
178 uhcrhda |= UHCRHDA_POTPGT(inf->power_on_delay / 2);
185 static int pxa27x_start_hc(struct device *dev)
188 struct pxaohci_platform_data *inf;
190 inf = dev->platform_data;
198 UHCHR |= UHCHR_FSBIR;
199 while (UHCHR & UHCHR_FSBIR)
202 pxa27x_setup_hc(inf);
205 retval = inf->init(dev);
212 UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
214 /* Clear any OTG Pin Hold */
215 if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH))
221 static void pxa27x_stop_hc(struct device *dev)
223 struct pxaohci_platform_data *inf;
225 inf = dev->platform_data;
237 clk_disable(usb_clk);
241 /*-------------------------------------------------------------------------*/
243 /* configure so an HC device and id are always provided */
244 /* always called with process context; sleeping is OK */
248 * usb_hcd_pxa27x_probe - initialize pxa27x-based HCDs
249 * Context: !in_interrupt()
251 * Allocates basic resources for this USB host controller, and
252 * then invokes the start() method for the HCD associated with it
253 * through the hotplug entry's driver_data.
256 int usb_hcd_pxa27x_probe (const struct hc_driver *driver, struct platform_device *pdev)
260 struct pxaohci_platform_data *inf;
262 inf = pdev->dev.platform_data;
267 if (pdev->resource[1].flags != IORESOURCE_IRQ) {
268 pr_debug ("resource[1] is not IORESOURCE_IRQ");
272 usb_clk = clk_get(&pdev->dev, "USBCLK");
274 return PTR_ERR(usb_clk);
276 hcd = usb_create_hcd (driver, &pdev->dev, "pxa27x");
279 hcd->rsrc_start = pdev->resource[0].start;
280 hcd->rsrc_len = pdev->resource[0].end - pdev->resource[0].start + 1;
282 if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
283 pr_debug("request_mem_region failed");
288 hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
290 pr_debug("ioremap failed");
295 if ((retval = pxa27x_start_hc(&pdev->dev)) < 0) {
296 pr_debug("pxa27x_start_hc failed");
300 /* Select Power Management Mode */
301 pxa27x_ohci_select_pmm(inf->port_mode);
303 if (inf->power_budget)
304 hcd->power_budget = inf->power_budget;
306 ohci_hcd_init(hcd_to_ohci(hcd));
308 retval = usb_add_hcd(hcd, pdev->resource[1].start, IRQF_DISABLED);
312 pxa27x_stop_hc(&pdev->dev);
316 release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
324 /* may be called without controller electrically present */
325 /* may be called with controller, bus, and devices active */
328 * usb_hcd_pxa27x_remove - shutdown processing for pxa27x-based HCDs
329 * @dev: USB Host Controller being removed
330 * Context: !in_interrupt()
332 * Reverses the effect of usb_hcd_pxa27x_probe(), first invoking
333 * the HCD's stop() method. It is always called from a thread
334 * context, normally "rmmod", "apmd", or something similar.
337 void usb_hcd_pxa27x_remove (struct usb_hcd *hcd, struct platform_device *pdev)
340 pxa27x_stop_hc(&pdev->dev);
342 release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
347 /*-------------------------------------------------------------------------*/
350 ohci_pxa27x_start (struct usb_hcd *hcd)
352 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
355 ohci_dbg (ohci, "ohci_pxa27x_start, ohci:%p", ohci);
357 /* The value of NDP in roothub_a is incorrect on this hardware */
360 if ((ret = ohci_init(ohci)) < 0)
363 if ((ret = ohci_run (ohci)) < 0) {
364 err ("can't start %s", hcd->self.bus_name);
372 /*-------------------------------------------------------------------------*/
374 static const struct hc_driver ohci_pxa27x_hc_driver = {
375 .description = hcd_name,
376 .product_desc = "PXA27x OHCI",
377 .hcd_priv_size = sizeof(struct ohci_hcd),
380 * generic hardware linkage
383 .flags = HCD_USB11 | HCD_MEMORY,
386 * basic lifecycle operations
388 .start = ohci_pxa27x_start,
390 .shutdown = ohci_shutdown,
393 * managing i/o requests and associated device resources
395 .urb_enqueue = ohci_urb_enqueue,
396 .urb_dequeue = ohci_urb_dequeue,
397 .endpoint_disable = ohci_endpoint_disable,
402 .get_frame_number = ohci_get_frame,
407 .hub_status_data = ohci_hub_status_data,
408 .hub_control = ohci_hub_control,
410 .bus_suspend = ohci_bus_suspend,
411 .bus_resume = ohci_bus_resume,
413 .start_port_reset = ohci_start_port_reset,
416 /*-------------------------------------------------------------------------*/
418 static int ohci_hcd_pxa27x_drv_probe(struct platform_device *pdev)
420 pr_debug ("In ohci_hcd_pxa27x_drv_probe");
425 return usb_hcd_pxa27x_probe(&ohci_pxa27x_hc_driver, pdev);
428 static int ohci_hcd_pxa27x_drv_remove(struct platform_device *pdev)
430 struct usb_hcd *hcd = platform_get_drvdata(pdev);
432 usb_hcd_pxa27x_remove(hcd, pdev);
433 platform_set_drvdata(pdev, NULL);
438 static int ohci_hcd_pxa27x_drv_suspend(struct platform_device *pdev, pm_message_t state)
440 struct usb_hcd *hcd = platform_get_drvdata(pdev);
441 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
443 if (time_before(jiffies, ohci->next_statechange))
445 ohci->next_statechange = jiffies;
447 pxa27x_stop_hc(&pdev->dev);
448 hcd->state = HC_STATE_SUSPENDED;
453 static int ohci_hcd_pxa27x_drv_resume(struct platform_device *pdev)
455 struct usb_hcd *hcd = platform_get_drvdata(pdev);
456 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
459 if (time_before(jiffies, ohci->next_statechange))
461 ohci->next_statechange = jiffies;
463 if ((status = pxa27x_start_hc(&pdev->dev)) < 0)
466 ohci_finish_controller_resume(hcd);
471 /* work with hotplug and coldplug */
472 MODULE_ALIAS("platform:pxa27x-ohci");
474 static struct platform_driver ohci_hcd_pxa27x_driver = {
475 .probe = ohci_hcd_pxa27x_drv_probe,
476 .remove = ohci_hcd_pxa27x_drv_remove,
477 .shutdown = usb_hcd_platform_shutdown,
479 .suspend = ohci_hcd_pxa27x_drv_suspend,
480 .resume = ohci_hcd_pxa27x_drv_resume,
483 .name = "pxa27x-ohci",
484 .owner = THIS_MODULE,