drivers/usb/host/ehci-omap.c

   1 /*
   2  * ehci-omap.c - driver for USBHOST on OMAP 34xx processor
   3  *
   4  * Bus Glue for OMAP34xx USBHOST 3 port EHCI controller
   5  * Tested on OMAP3430 ES2.0 SDP
   6  *
   7  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   8  * Copyright (C) 2007-2008 Vikram Pandita <vikram.pandita@ti.com>
   9  * Based on "ehci-fsl.c" by David Brownell and
  10  *          "ehci-au1xxx.c" by K.Boge <karsten.boge@amd.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  25  *
  26  */
  27
  28 #include <linux/platform_device.h>
  29 #include <linux/clk.h>
  30 #include <asm/arch/gpio.h>
  31
  32 #include "ehci-omap.h"
  33
  34
  35 #ifdef CONFIG_OMAP_EHCI_PHY_MODE
  36 /* EHCI connected to External PHY */
  37
  38 /* External USB connectivity board: 750-2083-001
  39  * Connected to OMAP3430 SDP
  40  * The board has Port1 and Port2 connected to ISP1504 in 12-pin ULPI mode
  41  */
  42
  43 /* ISSUE1:
  44  *      ISP1504 for input clocking mode needs special reset handling
  45  *      Hold the PHY in reset by asserting RESET_N signal
  46  *      Then start the 60Mhz clock input to PHY
  47  *      Release the reset after a delay -
  48  *              to get the PHY state machine in working state
  49  */
  50 #define EXTERNAL_PHY_RESET
  51 #define EXT_PHY_RESET_GPIO_PORT1        (57)
  52 #define EXT_PHY_RESET_GPIO_PORT2        (61)
  53 #define EXT_PHY_RESET_DELAY             (10)
  54
  55 /* ISSUE2:
  56  * USBHOST supports External charge pump PHYs only
  57  * Use the VBUS from Port1 to power VBUS of Port2 externally
  58  * So use Port2 as the working ULPI port
  59  */
  60 #define VBUS_INTERNAL_CHARGEPUMP_HACK
  61
  62 #endif /* CONFIG_OMAP_EHCI_PHY_MODE */
  63
  64 /*-------------------------------------------------------------------------*/
  65
  66 /* Define USBHOST clocks for clock management */
  67 struct ehci_omap_clock_defs {
  68         struct clk      *usbhost_ick_clk;
  69         struct clk      *usbhost2_120m_fck_clk;
  70         struct clk      *usbhost1_48m_fck_clk;
  71         struct clk      *usbtll_fck_clk;
  72         struct clk      *usbtll_ick_clk;
  73 };
  74
  75 /* Clock names as per clock framework: May change so keep as #defs */
  76 #define USBHOST_ICKL    "usbhost_l4_ick"
  77 #define USBHOST_120M_FCLK       "usbhost_120m_fck"
  78 #define USBHOST_48M_FCLK        "usbhost_48m_fck"
  79 #define USBHOST_TLL_ICKL        "usbtll_ick"
  80 #define USBHOST_TLL_FCLK        "usbtll_fck"
  81 /*-------------------------------------------------------------------------*/
  82
  83
  84 #ifndef CONFIG_OMAP_EHCI_PHY_MODE
  85
  86 static void omap_usb_utmi_init(struct usb_hcd *hcd, u8 tll_channel_mask)
  87 {
  88         int i;
  89
  90         /* Use UTMI Ports of TLL */
  91         omap_writel((1 << OMAP_UHH_HOSTCONFIG_ULPI_BYPASS_SHIFT),
  92                                                 OMAP_UHH_HOSTCONFIG);
  93         /* Enusre bit is set */
  94         while (!(omap_readl(OMAP_UHH_HOSTCONFIG) &
  95                 (1 << OMAP_UHH_HOSTCONFIG_ULPI_BYPASS_SHIFT)));
  96
  97         dev_dbg(hcd->self.controller, "\nEntered UTMI MODE: success\n");
  98
  99         /* Program the 3 TLL channels upfront */
 100
 101         for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) {
 102
 103                 /* Disable AutoIdle */
 104                 omap_writel(omap_readl(OMAP_TLL_CHANNEL_CONF(i)) &
 105                             ~(1<<OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE_SHIFT),
 106                             OMAP_TLL_CHANNEL_CONF(i));
 107                 /* Disable BitStuffing */
 108                 omap_writel(omap_readl(OMAP_TLL_CHANNEL_CONF(i)) &
 109                             ~(1<<OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF_SHIFT),
 110                             OMAP_TLL_CHANNEL_CONF(i));
 111                 /* SDR Mode */
 112                 omap_writel(omap_readl(OMAP_TLL_CHANNEL_CONF(i)) &
 113                             ~(1<<OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE_SHIFT),
 114                             OMAP_TLL_CHANNEL_CONF(i));
 115
 116         }
 117
 118         /* Program Common TLL register */
 119         omap_writel((1 << OMAP_TLL_SHARED_CONF_FCLK_IS_ON_SHIFT) |
 120                         (1 << OMAP_TLL_SHARED_CONF_USB_DIVRATION_SHIFT) |
 121                         (0 << OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN_SHIFT) |
 122                         (0 << OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN_SHFT),
 123                                 OMAP_TLL_SHARED_CONF);
 124
 125         /* Enable channels now */
 126         for (i = 0; i < OMAP_TLL_CHANNEL_COUNT; i++) {
 127
 128                 /* Enable only the channel that is needed */
 129                 if (!(tll_channel_mask & 1<<i))
 130                         continue;
 131
 132                 omap_writel(omap_readl(OMAP_TLL_CHANNEL_CONF(i)) |
 133                             (1<<OMAP_TLL_CHANNEL_CONF_CHANEN_SHIFT),
 134                             OMAP_TLL_CHANNEL_CONF(i));
 135
 136                 omap_writeb(0xBE, OMAP_TLL_ULPI_SCRATCH_REGISTER(i));
 137                 dev_dbg(hcd->self.controller, "\nULPI_SCRATCH_REG[ch=%d]"
 138                         "= 0x%02x\n",
 139                         i+1, omap_readb(OMAP_TLL_ULPI_SCRATCH_REGISTER(i)));
 140         }
 141 }
 142
 143 #else
 144 # define omap_usb_utmi_init(x, y)       0
 145 #endif
 146
 147
 148 /* omap_start_ehc
 149  *      - Start the TI USBHOST controller
 150  */
 151 static int omap_start_ehc(struct platform_device *dev, struct usb_hcd *hcd)
 152 {
 153         struct ehci_omap_clock_defs *ehci_clocks;
 154
 155         dev_dbg(hcd->self.controller, ": starting TI EHCI USB Controller\n");
 156
 157         ehci_clocks = (struct ehci_omap_clock_defs *)(
 158                                 ((char *)hcd_to_ehci(hcd)) +
 159                                         sizeof(struct ehci_hcd));
 160
 161         /* Start DPLL5 Programming:
 162          * Clock Framework is not doing this now:
 163          * This will be done in clock framework later
 164          */
 165         /* Enable DPLL 5 : Based on Input of 13Mhz*/
 166         cm_write_mod_reg((12 << OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT)|
 167                         (120 << OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT),
 168                         PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
 169
 170         cm_write_mod_reg(1 << OMAP3430ES2_DIV_120M_SHIFT,
 171                         PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
 172
 173         cm_write_mod_reg((7 << OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT) |
 174                         (7 << OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT),
 175                         PLL_MOD, OMAP3430ES2_CM_CLKEN2);
 176
 177         while (!(cm_read_mod_reg(PLL_MOD, CM_IDLEST2) &
 178                                 OMAP3430_ST_PERIPH2_CLK))
 179                 dev_dbg(hcd->self.controller,
 180                         "idlest2 = 0x%x\n",
 181                         cm_read_mod_reg(PLL_MOD, CM_IDLEST2));
 182         /* End DPLL5 programming */
 183
 184
 185         /* PRCM settings for USBHOST:
 186          * Interface clk un-related to domain transition
 187          */
 188         cm_write_mod_reg(0 << OMAP3430ES2_AUTO_USBHOST_SHIFT,
 189                                 OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
 190
 191         /* Disable sleep dependency with MPU and IVA */
 192         cm_write_mod_reg((0 << OMAP3430ES2_EN_MPU_SHIFT) |
 193                                 (0 << OMAP3430ES2_EN_IVA2_SHIFT),
 194                                 OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
 195
 196         /* Disable Automatic transition of clock */
 197         cm_write_mod_reg(0 << OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT,
 198                                 OMAP3430ES2_USBHOST_MOD, CM_CLKSTCTRL);
 199
 200         /* Enable Clocks for USBHOST */
 201         ehci_clocks->usbhost_ick_clk = clk_get(&dev->dev,
 202                                                 USBHOST_ICKL);
 203         if (IS_ERR(ehci_clocks->usbhost_ick_clk))
 204                 return PTR_ERR(ehci_clocks->usbhost_ick_clk);
 205         clk_enable(ehci_clocks->usbhost_ick_clk);
 206
 207
 208         ehci_clocks->usbhost2_120m_fck_clk = clk_get(&dev->dev,
 209                                                         USBHOST_120M_FCLK);
 210         if (IS_ERR(ehci_clocks->usbhost2_120m_fck_clk))
 211                 return PTR_ERR(ehci_clocks->usbhost2_120m_fck_clk);
 212         clk_enable(ehci_clocks->usbhost2_120m_fck_clk);
 213
 214         ehci_clocks->usbhost1_48m_fck_clk = clk_get(&dev->dev,
 215                                                 USBHOST_48M_FCLK);
 216         if (IS_ERR(ehci_clocks->usbhost1_48m_fck_clk))
 217                 return PTR_ERR(ehci_clocks->usbhost1_48m_fck_clk);
 218         clk_enable(ehci_clocks->usbhost1_48m_fck_clk);
 219
 220
 221 #ifdef EXTERNAL_PHY_RESET
 222         /* Refer: ISSUE1 */
 223         omap_request_gpio(EXT_PHY_RESET_GPIO_PORT1);
 224         omap_set_gpio_direction(EXT_PHY_RESET_GPIO_PORT1, 0);
 225         omap_request_gpio(EXT_PHY_RESET_GPIO_PORT2);
 226         omap_set_gpio_direction(EXT_PHY_RESET_GPIO_PORT2, 0);
 227         omap_set_gpio_dataout(EXT_PHY_RESET_GPIO_PORT1, 0);
 228         omap_set_gpio_dataout(EXT_PHY_RESET_GPIO_PORT2, 0);
 229         /* Hold the PHY in RESET for enough time till DIR is high */
 230         udelay(EXT_PHY_RESET_DELAY);
 231 #endif
 232
 233         /* Configure TLL for 60Mhz clk for ULPI */
 234         ehci_clocks->usbtll_fck_clk = clk_get(&dev->dev, USBHOST_TLL_FCLK);
 235         if (IS_ERR(ehci_clocks->usbtll_fck_clk))
 236                 return PTR_ERR(ehci_clocks->usbtll_fck_clk);
 237         clk_enable(ehci_clocks->usbtll_fck_clk);
 238
 239         ehci_clocks->usbtll_ick_clk = clk_get(&dev->dev, USBHOST_TLL_ICKL);
 240         if (IS_ERR(ehci_clocks->usbtll_ick_clk))
 241                 return PTR_ERR(ehci_clocks->usbtll_ick_clk);
 242         clk_enable(ehci_clocks->usbtll_ick_clk);
 243
 244         /* Disable Auto Idle of USBTLL */
 245         cm_write_mod_reg((0 << OMAP3430_AUTO_USBTLL_SHIFT),
 246                                 CORE_MOD, OMAP3430_CM_AUTOIDLE3_CORE);
 247
 248         /* Wait for TLL to be Active */
 249         while ((cm_read_mod_reg(CORE_MOD, OMAP3430_CM_IDLEST3_CORE) &
 250                 (1 << OMAP3430_ST_USBTLL_SHIFT)));
 251
 252         /* perform TLL soft reset, and wait until reset is complete */
 253         omap_writel(1 << OMAP_USBTLL_SYSCONFIG_SOFTRESET_SHIFT,
 254                         OMAP_USBTLL_SYSCONFIG);
 255         /* Wait for TLL reset to complete */
 256         while (!(omap_readl(OMAP_USBTLL_SYSSTATUS) &
 257                 (1 << OMAP_USBTLL_SYSSTATUS_RESETDONE_SHIFT)));
 258
 259         dev_dbg(hcd->self.controller, "\n TLL RESET DONE\n");
 260
 261         /* (1<<3) = no idle mode only for initial debugging */
 262         omap_writel((1 << OMAP_USBTLL_SYSCONFIG_ENAWAKEUP_SHIFT) |
 263                         (1 << OMAP_USBTLL_SYSCONFIG_SIDLEMODE_SHIFT) |
 264                         (1 << OMAP_USBTLL_SYSCONFIG_CACTIVITY_SHIFT),
 265                         OMAP_USBTLL_SYSCONFIG);
 266
 267
 268         /* Put UHH in NoIdle/NoStandby mode */
 269         omap_writel((0 << OMAP_UHH_SYSCONFIG_AUTOIDLE_SHIFT) |
 270                         (1 << OMAP_UHH_SYSCONFIG_ENAWAKEUP_SHIFT) |
 271                         (1 << OMAP_UHH_SYSCONFIG_SIDLEMODE_SHIFT) |
 272                         (1 << OMAP_UHH_SYSCONFIG_CACTIVITY_SHIFT) |
 273                         (1 << OMAP_UHH_SYSCONFIG_MIDLEMODE_SHIFT),
 274                         OMAP_UHH_SYSCONFIG);
 275
 276 #ifdef CONFIG_OMAP_EHCI_PHY_MODE
 277         /* Bypass the TLL module for PHY mode operation */
 278         omap_writel((0 << OMAP_UHH_HOSTCONFIG_ULPI_BYPASS_SHIFT),
 279                                                 OMAP_UHH_HOSTCONFIG);
 280         /* Ensure that BYPASS is set */
 281         while (omap_readl(OMAP_UHH_HOSTCONFIG) &
 282                 (1 << OMAP_UHH_HOSTCONFIG_ULPI_BYPASS_SHIFT));
 283
 284         dev_dbg(hcd->self.controller, "Entered ULPI PHY MODE: success");
 285
 286 #else
 287         /* Enable UTMI mode for all 3 TLL channels */
 288         omap_usb_utmi_init(hcd,
 289                 OMAP_TLL_CHANNEL_1_EN_MASK |
 290                 OMAP_TLL_CHANNEL_2_EN_MASK |
 291                 OMAP_TLL_CHANNEL_3_EN_MASK
 292                 );
 293 #endif
 294
 295 #ifdef EXTERNAL_PHY_RESET
 296         /* Refer ISSUE1:
 297          * Hold the PHY in RESET for enough time till PHY is settled and ready
 298          */
 299         udelay(EXT_PHY_RESET_DELAY);
 300         omap_set_gpio_dataout(EXT_PHY_RESET_GPIO_PORT1, 1);
 301         omap_set_gpio_dataout(EXT_PHY_RESET_GPIO_PORT2, 1);
 302 #endif
 303
 304 #ifdef VBUS_INTERNAL_CHARGEPUMP_HACK
 305         /* Refer ISSUE2: LINK assumes external charge pump */
 306
 307         /* use Port1 VBUS to charge externally Port2:
 308          *      So for PHY mode operation use Port2 only
 309          */
 310         omap_writel((0xA << EHCI_INSNREG05_ULPI_REGADD_SHIFT) |/* OTG ctrl reg*/
 311                         (2 << EHCI_INSNREG05_ULPI_OPSEL_SHIFT) |/*   Write */
 312                         (1 << EHCI_INSNREG05_ULPI_PORTSEL_SHIFT) |/* Port1 */
 313                         (1 << EHCI_INSNREG05_ULPI_CONTROL_SHIFT) |/* Start */
 314                         (0x26),
 315                         EHCI_INSNREG05_ULPI);
 316
 317         while (!(omap_readl(EHCI_INSNREG05_ULPI) &
 318                 (1<<EHCI_INSNREG05_ULPI_CONTROL_SHIFT)));
 319
 320 #endif
 321
 322         return 0;
 323 }
 324
 325 /*-------------------------------------------------------------------------*/
 326
 327 static void omap_stop_ehc(struct platform_device *dev, struct usb_hcd *hcd)
 328 {
 329         struct ehci_omap_clock_defs *ehci_clocks;
 330
 331         ehci_clocks = (struct ehci_omap_clock_defs *)
 332                         (((char *)hcd_to_ehci(hcd)) + sizeof(struct ehci_hcd));
 333
 334         dev_dbg(hcd->self.controller, ": stopping TI EHCI USB Controller\n");
 335
 336         /* Reset OMAP modules for insmod/rmmod to work */
 337         omap_writel((1<<1), OMAP_UHH_SYSCONFIG);
 338         while (!(omap_readl(OMAP_UHH_SYSSTATUS) & (1<<0)));
 339         while (!(omap_readl(OMAP_UHH_SYSSTATUS) & (1<<1)));
 340         while (!(omap_readl(OMAP_UHH_SYSSTATUS) & (1<<2)));
 341         dev_dbg(hcd->self.controller,
 342                 "UHH RESET DONE OMAP_UHH_SYSSTATUS %x !!\n",
 343                         omap_readl(OMAP_UHH_SYSSTATUS));
 344
 345         omap_writel((1<<1), OMAP_USBTLL_SYSCONFIG);
 346         while (!(omap_readl(OMAP_USBTLL_SYSSTATUS) & (1<<0)));
 347         dev_dbg(hcd->self.controller, ":TLL RESEET DONE");
 348
 349         if (ehci_clocks->usbtll_fck_clk != NULL) {
 350                 clk_disable(ehci_clocks->usbtll_fck_clk);
 351                 clk_put(ehci_clocks->usbtll_fck_clk);
 352                 ehci_clocks->usbtll_fck_clk = NULL;
 353         }
 354
 355         if (ehci_clocks->usbhost_ick_clk != NULL) {
 356                 clk_disable(ehci_clocks->usbhost_ick_clk);
 357                 clk_put(ehci_clocks->usbhost_ick_clk);
 358                 ehci_clocks->usbhost_ick_clk = NULL;
 359         }
 360
 361         if (ehci_clocks->usbhost1_48m_fck_clk != NULL) {
 362                 clk_disable(ehci_clocks->usbhost1_48m_fck_clk);
 363                 clk_put(ehci_clocks->usbhost1_48m_fck_clk);
 364                 ehci_clocks->usbhost1_48m_fck_clk = NULL;
 365         }
 366
 367         if (ehci_clocks->usbhost2_120m_fck_clk != NULL) {
 368                 clk_disable(ehci_clocks->usbhost2_120m_fck_clk);
 369                 clk_put(ehci_clocks->usbhost2_120m_fck_clk);
 370                 ehci_clocks->usbhost2_120m_fck_clk = NULL;
 371         }
 372
 373         if (ehci_clocks->usbtll_ick_clk != NULL) {
 374                 clk_disable(ehci_clocks->usbtll_ick_clk);
 375                 clk_put(ehci_clocks->usbtll_ick_clk);
 376                 ehci_clocks->usbtll_ick_clk = NULL;
 377         }
 378
 379
 380 #ifdef EXTERNAL_PHY_RESET
 381         omap_free_gpio(EXT_PHY_RESET_GPIO_PORT1);
 382         omap_free_gpio(EXT_PHY_RESET_GPIO_PORT2);
 383 #endif
 384
 385         dev_dbg(hcd->self.controller,
 386                 ": Clock to USB host has been disabled\n");
 387 }
 388
 389 static const struct hc_driver ehci_omap_hc_driver;
 390
 391 /*-------------------------------------------------------------------------*/
 392 /* configure so an HC device and id are always provided */
 393 /* always called with process context; sleeping is OK */
 394
 395 /**
 396  * ehci_hcd_omap_drv_probe - initialize TI-based HCDs
 397  * Context: !in_interrupt()
 398  *
 399  * Allocates basic resources for this USB host controller, and
 400  * then invokes the start() method for the HCD associated with it
 401  * through the hotplug entry's driver_data.
 402  *
 403  */
 404 static int ehci_hcd_omap_drv_probe(struct platform_device *dev)
 405 {
 406         int retval = 0;
 407         struct usb_hcd *hcd;
 408         struct ehci_hcd *ehci;
 409
 410         dev_dbg(&dev->dev, "ehci_hcd_omap_drv_probe()");
 411
 412         if (usb_disabled())
 413                 return -ENODEV;
 414
 415         if (dev->resource[1].flags != IORESOURCE_IRQ) {
 416                 dev_dbg(&dev->dev, "resource[1] is not IORESOURCE_IRQ");
 417                 retval = -ENOMEM;
 418         }
 419
 420         hcd = usb_create_hcd(&ehci_omap_hc_driver, &dev->dev, dev->dev.bus_id);
 421         if (!hcd)
 422                 return -ENOMEM;
 423
 424         retval = omap_start_ehc(dev, hcd);
 425         if (retval)
 426                 return retval;
 427
 428         hcd->rsrc_start = 0;
 429         hcd->rsrc_len = 0;
 430         hcd->rsrc_start = dev->resource[0].start;
 431         hcd->rsrc_len = dev->resource[0].end - dev->resource[0].start + 1;
 432
 433         hcd->regs = (void __iomem *) (int) IO_ADDRESS(hcd->rsrc_start);
 434
 435         ehci = hcd_to_ehci(hcd);
 436         ehci->caps = hcd->regs;
 437
 438         ehci->regs = hcd->regs + HC_LENGTH(readl(&ehci->caps->hc_capbase));
 439         /* cache this readonly data; minimize chip reads */
 440         ehci->hcs_params = readl(&ehci->caps->hcs_params);
 441
 442         /* SET 1 micro-frame Interrupt interval */
 443         writel(readl(&ehci->regs->command) | (1<<16), &ehci->regs->command);
 444
 445         retval = usb_add_hcd(hcd, dev->resource[1].start,
 446                                 IRQF_DISABLED | IRQF_SHARED);
 447         if (retval == 0)
 448                 return retval;
 449
 450         dev_dbg(hcd->self.controller, "ERR: add_hcd");
 451         omap_stop_ehc(dev, hcd);
 452
 453         usb_put_hcd(hcd);
 454         return retval;
 455 }
 456
 457 /*-------------------------------------------------------------------------*/
 458
 459 /* may be called without controller electrically present */
 460 /* may be called with controller, bus, and devices active */
 461
 462 /**
 463  * ehci_hcd_omap_drv_remove - shutdown processing for EHCI HCDs
 464  * @dev: USB Host Controller being removed
 465  * Context: !in_interrupt()
 466  *
 467  * Reverses the effect of usb_ehci_hcd_omap_probe(), first invoking
 468  * the HCD's stop() method.  It is always called from a thread
 469  * context, normally "rmmod", "apmd", or something similar.
 470  *
 471  */
 472 static int ehci_hcd_omap_drv_remove(struct platform_device *dev)
 473 {
 474         struct usb_hcd *hcd = platform_get_drvdata(dev);
 475
 476         dev_dbg(&dev->dev, "ehci_hcd_omap_drv_remove()");
 477
 478         usb_remove_hcd(hcd);
 479         usb_put_hcd(hcd);
 480         omap_stop_ehc(dev, hcd);
 481
 482         return 0;
 483 }
 484
 485 /*-------------------------------------------------------------------------*/
 486 #ifdef CONFIG_PM
 487 static int omap_ehci_bus_suspend(struct usb_hcd *hcd)
 488 {
 489         return ehci_bus_suspend(hcd);
 490 }
 491
 492 static int omap_ehci_bus_resume(struct usb_hcd *hcd)
 493 {
 494         return ehci_bus_resume(hcd);
 495 }
 496 #endif
 497 /*-------------------------------------------------------------------------*/
 498
 499 static const struct hc_driver ehci_omap_hc_driver = {
 500         .description = hcd_name,
 501         .product_desc = "OMAP-EHCI Host Controller",
 502         .hcd_priv_size = sizeof(struct ehci_hcd)
 503                                 + sizeof(struct ehci_omap_clock_defs),
 504
 505         /*
 506          * generic hardware linkage
 507          */
 508         .irq = ehci_irq,
 509         .flags = HCD_MEMORY | HCD_USB2,
 510
 511         /*
 512          * basic lifecycle operations
 513          */
 514         .reset = ehci_init,
 515         .start = ehci_run,
 516         .stop = ehci_stop,
 517         .shutdown = ehci_shutdown,
 518
 519         /*
 520          * managing i/o requests and associated device resources
 521          */
 522         .urb_enqueue = ehci_urb_enqueue,
 523         .urb_dequeue = ehci_urb_dequeue,
 524         .endpoint_disable = ehci_endpoint_disable,
 525
 526         /*
 527          * scheduling support
 528          */
 529         .get_frame_number = ehci_get_frame,
 530
 531         /*
 532          * root hub support
 533          */
 534         .hub_status_data = ehci_hub_status_data,
 535         .hub_control = ehci_hub_control,
 536 #ifdef  CONFIG_PM
 537         .bus_suspend = omap_ehci_bus_suspend,
 538         .bus_resume = omap_ehci_bus_resume,
 539 #endif
 540 };
 541
 542 /*-------------------------------------------------------------------------*/
 543 MODULE_ALIAS("omap-ehci");
 544 static struct platform_driver ehci_hcd_omap_driver = {
 545         .probe = ehci_hcd_omap_drv_probe,
 546         .remove = ehci_hcd_omap_drv_remove,
 547         .shutdown = usb_hcd_platform_shutdown,
 548         /*.suspend      = ehci_hcd_omap_drv_suspend, */
 549         /*.resume       = ehci_hcd_omap_drv_resume, */
 550         .driver = {
 551                 .name = "ehci-omap",
 552                 .bus = &platform_bus_type
 553         }
 554 };