drivers/usb/host/ehci-omap.c

   1 /*
   2  * ehci-omap.c - driver for USBHOST on OMAP 34xx processor
   3  *
   4  * Bus Glue for OMAP34xx USBHOST 3 port EHCI controller
   5  * Tested on OMAP3430 ES2.0 SDP
   6  *
   7  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   8  * Copyright (C) 2007-2008 Vikram Pandita <vikram.pandita@ti.com>
   9  * Based on "ehci-fsl.c" by David Brownell and
  10  *          "ehci-au1xxx.c" by K.Boge <karsten.boge@amd.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  25  *
  26  */
  27
  28 #include <linux/platform_device.h>
  29 #include <linux/clk.h>
  30 #include <asm/arch/gpio.h>
  31
  32 #include "ehci-omap.h"
  33
  34
  35 #ifdef CONFIG_OMAP_EHCI_PHY_MODE
  36 /* EHCI connected to External PHY */
  37
  38 /* External USB connectivity board: 750-2083-001
  39  * Connected to OMAP3430 SDP
  40  * The board has Port1 and Port2 connected to ISP1504 in 12-pin ULPI mode
  41  */
  42
  43 /* ISSUE1:
  44  *      ISP1504 for input clocking mode needs special reset handling
  45  *      Hold the PHY in reset by asserting RESET_N signal
  46  *      Then start the 60Mhz clock input to PHY
  47  *      Release the reset after a delay -
  48  *              to get the PHY state machine in working state
  49  */
  50 #define EXTERNAL_PHY_RESET
  51 #define EXT_PHY_RESET_GPIO_PORT1        (57)
  52 #define EXT_PHY_RESET_GPIO_PORT2        (61)
  53 #define EXT_PHY_RESET_DELAY             (10)
  54
  55 /* ISSUE2:
  56  * USBHOST supports External charge pump PHYs only
  57  * Use the VBUS from Port1 to power VBUS of Port2 externally
  58  * So use Port2 as the working ULPI port
  59  */
  60 #define VBUS_INTERNAL_CHARGEPUMP_HACK
  61
  62 #endif /* CONFIG_OMAP_EHCI_PHY_MODE */
  63
  64 /*-------------------------------------------------------------------------*/
  65
  66 /* Define USBHOST clocks for clock management */
  67 struct ehci_omap_clock_defs {
  68         struct clk      *usbhost_ick_clk;
  69         struct clk      *usbhost2_120m_fck_clk;
  70         struct clk      *usbhost1_48m_fck_clk;
  71         struct clk      *usbtll_fck_clk;
  72         struct clk      *usbtll_ick_clk;
  73 };
  74
  75 /* Clock names as per clock framework: May change so keep as #defs */
  76 #define USBHOST_ICKL    "usbhost_l4_ick"
  77 #define USBHOST_120M_FCLK       "usbhost_120m_fck"
  78 #define USBHOST_48M_FCLK        "usbhost_48m_fck"
  79 #define USBHOST_TLL_ICKL        "usbtll_ick"
  80 #define USBHOST_TLL_FCLK        "usbtll_fck"
  81 /*-------------------------------------------------------------------------*/
  82
  83 /* omap_start_ehc
  84  *      - Start the TI USBHOST controller
  85  */
  86 static int omap_start_ehc(struct platform_device *dev, struct usb_hcd *hcd)
  87 {
  88         struct ehci_omap_clock_defs *ehci_clocks;
  89
  90         dev_dbg(hcd->self.controller, ": starting TI EHCI USB Controller\n");
  91
  92         ehci_clocks = (struct ehci_omap_clock_defs *)(
  93                                 ((char *)hcd_to_ehci(hcd)) +
  94                                         sizeof(struct ehci_hcd));
  95
  96         /* Start DPLL5 Programming:
  97          * Clock Framework is not doing this now:
  98          * This will be done in clock framework later
  99          */
 100         /* Enable DPLL 5 : Based on Input of 13Mhz*/
 101         cm_write_mod_reg((12 << OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT)|
 102                         (120 << OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT),
 103                         PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
 104
 105         cm_write_mod_reg(1 << OMAP3430ES2_DIV_120M_SHIFT,
 106                         PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
 107
 108         cm_write_mod_reg((7 << OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT) |
 109                         (7 << OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT),
 110                         PLL_MOD, OMAP3430ES2_CM_CLKEN2);
 111
 112         while (!(cm_read_mod_reg(PLL_MOD, CM_IDLEST2) &
 113                                 OMAP3430_ST_PERIPH2_CLK))
 114                 dev_dbg(hcd->self.controller,
 115                         "idlest2 = 0x%x\n",
 116                         cm_read_mod_reg(PLL_MOD, CM_IDLEST2));
 117         /* End DPLL5 programming */
 118
 119
 120         /* PRCM settings for USBHOST:
 121          * Interface clk un-related to domain transition
 122          */
 123         cm_write_mod_reg(0 << OMAP3430ES2_AUTO_USBHOST_SHIFT,
 124                                 OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
 125
 126         /* Disable sleep dependency with MPU and IVA */
 127         cm_write_mod_reg((0 << OMAP3430ES2_EN_MPU_SHIFT) |
 128                                 (0 << OMAP3430ES2_EN_IVA2_SHIFT),
 129                                 OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
 130
 131         /* Disable Automatic transition of clock */
 132         cm_write_mod_reg(0 << OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT,
 133                                 OMAP3430ES2_USBHOST_MOD, CM_CLKSTCTRL);
 134
 135         /* Enable Clocks for USBHOST */
 136         ehci_clocks->usbhost_ick_clk = clk_get(&dev->dev,
 137                                                 USBHOST_ICKL);
 138         if (IS_ERR(ehci_clocks->usbhost_ick_clk))
 139                 return PTR_ERR(ehci_clocks->usbhost_ick_clk);
 140         clk_enable(ehci_clocks->usbhost_ick_clk);
 141
 142
 143         ehci_clocks->usbhost2_120m_fck_clk = clk_get(&dev->dev,
 144                                                         USBHOST_120M_FCLK);
 145         if (IS_ERR(ehci_clocks->usbhost2_120m_fck_clk))
 146                 return PTR_ERR(ehci_clocks->usbhost2_120m_fck_clk);
 147         clk_enable(ehci_clocks->usbhost2_120m_fck_clk);
 148
 149         ehci_clocks->usbhost1_48m_fck_clk = clk_get(&dev->dev,
 150                                                 USBHOST_48M_FCLK);
 151         if (IS_ERR(ehci_clocks->usbhost1_48m_fck_clk))
 152                 return PTR_ERR(ehci_clocks->usbhost1_48m_fck_clk);
 153         clk_enable(ehci_clocks->usbhost1_48m_fck_clk);
 154
 155
 156 #ifdef EXTERNAL_PHY_RESET
 157         /* Refer: ISSUE1 */
 158         omap_request_gpio(EXT_PHY_RESET_GPIO_PORT1);
 159         omap_set_gpio_direction(EXT_PHY_RESET_GPIO_PORT1, 0);
 160         omap_request_gpio(EXT_PHY_RESET_GPIO_PORT2);
 161         omap_set_gpio_direction(EXT_PHY_RESET_GPIO_PORT2, 0);
 162         omap_set_gpio_dataout(EXT_PHY_RESET_GPIO_PORT1, 0);
 163         omap_set_gpio_dataout(EXT_PHY_RESET_GPIO_PORT2, 0);
 164         /* Hold the PHY in RESET for enough time till DIR is high */
 165         udelay(EXT_PHY_RESET_DELAY);
 166 #endif
 167
 168         /* Configure TLL for 60Mhz clk for ULPI */
 169         ehci_clocks->usbtll_fck_clk = clk_get(&dev->dev, USBHOST_TLL_FCLK);
 170         if (IS_ERR(ehci_clocks->usbtll_fck_clk))
 171                 return PTR_ERR(ehci_clocks->usbtll_fck_clk);
 172         clk_enable(ehci_clocks->usbtll_fck_clk);
 173
 174         ehci_clocks->usbtll_ick_clk = clk_get(&dev->dev, USBHOST_TLL_ICKL);
 175         if (IS_ERR(ehci_clocks->usbtll_ick_clk))
 176                 return PTR_ERR(ehci_clocks->usbtll_ick_clk);
 177         clk_enable(ehci_clocks->usbtll_ick_clk);
 178
 179         /* Disable Auto Idle of USBTLL */
 180         cm_write_mod_reg((0 << OMAP3430_AUTO_USBTLL_SHIFT),
 181                                 CORE_MOD, OMAP3430_CM_AUTOIDLE3_CORE);
 182
 183         /* Wait for TLL to be Active */
 184         while ((cm_read_mod_reg(CORE_MOD, OMAP3430_CM_IDLEST3_CORE) &
 185                 (1 << OMAP3430_ST_USBTLL_SHIFT)));
 186
 187         /* perform TLL soft reset, and wait until reset is complete */
 188         /* (1<<3) = no idle mode only for initial debugging */
 189         omap_writel((1 << OMAP_USBTLL_SYSCONFIG_SOFTRESET_SHIFT) |
 190                         (1 << OMAP_USBTLL_SYSCONFIG_ENAWAKEUP_SHIFT) |
 191                         (1 << OMAP_USBTLL_SYSCONFIG_SIDLEMODE_SHIFT) |
 192                         (1 << OMAP_USBTLL_SYSCONFIG_CACTIVITY_SHIFT),
 193                         OMAP_USBTLL_SYSCONFIG);
 194         /* Wait for TLL reset to complete */
 195         while (!(omap_readl(OMAP_USBTLL_SYSSTATUS) &
 196                 (1 << OMAP_USBTLL_SYSSTATUS_RESETDONE_SHIFT)));
 197
 198         dev_dbg(hcd->self.controller, "\n TLL RESET DONE");
 199
 200         /* Put UHH in NoIdle/NoStandby mode */
 201         omap_writel((0 << OMAP_UHH_SYSCONFIG_AUTOIDLE_SHIFT) |
 202                         (1 << OMAP_UHH_SYSCONFIG_ENAWAKEUP_SHIFT) |
 203                         (1 << OMAP_UHH_SYSCONFIG_SIDLEMODE_SHIFT) |
 204                         (1 << OMAP_UHH_SYSCONFIG_CACTIVITY_SHIFT) |
 205                         (1 << OMAP_UHH_SYSCONFIG_MIDLEMODE_SHIFT),
 206                         OMAP_UHH_SYSCONFIG);
 207
 208 #ifdef CONFIG_OMAP_EHCI_PHY_MODE
 209         /* Bypass the TLL module for PHY mode operation */
 210         omap_writel((0 << OMAP_UHH_HOSTCONFIG_ULPI_BYPASS_SHIFT),
 211                                                 OMAP_UHH_HOSTCONFIG);
 212         /* Ensure that BYPASS is set */
 213         while (omap_readl(OMAP_UHH_HOSTCONFIG) &
 214                 (1 << OMAP_UHH_HOSTCONFIG_ULPI_BYPASS_SHIFT));
 215
 216         dev_dbg(hcd->self.controller, "Entered ULPI PHY MODE: success");
 217
 218 #else
 219         /* Use UTMI Ports of TLL */
 220         omap_writel((1 << OMAP_UHH_HOSTCONFIG_ULPI_BYPASS_SHIFT),
 221                                                 OMAP_UHH_HOSTCONFIG);
 222         /* Enusre bit is set */
 223         while (!(omap_readl(OMAP_UHH_HOSTCONFIG) &
 224                 (1 << OMAP_UHH_HOSTCONFIG_ULPI_BYPASS_SHIFT)));
 225
 226         dev_dbg(hcd->self.controller, "Entered UTMI MODE: success");
 227
 228         /* Program the 3 TLL channels upfront */
 229
 230         /* CHANNEL-1 */
 231         /* Disable AutoIdle */
 232         omap_writel(omap_readl(OMAP_TLL_CHANNEL_CONF(0)) &
 233                         ~(1<<OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE_SHIFT),
 234                         OMAP_TLL_CHANNEL_CONF(0));
 235         /* Disable BitStuffing */
 236         omap_writel(omap_readl(OMAP_TLL_CHANNEL_CONF(0)) &
 237                         ~(1<<OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF_SHIFT),
 238                         OMAP_TLL_CHANNEL_CONF(0));
 239         /* SDR Mode */
 240         omap_writel(omap_readl(OMAP_TLL_CHANNEL_CONF(0)) &
 241                         ~(1<<OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE_SHIFT),
 242                         OMAP_TLL_CHANNEL_CONF(0));
 243
 244         /* CHANNEL-2 */
 245         /* Disable AutoIdle */
 246         omap_writel(omap_readl(OMAP_TLL_CHANNEL_CONF(1)) &
 247                         ~(1<<OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE_SHIFT),
 248                         OMAP_TLL_CHANNEL_CONF(1));
 249         /* Disable BitStuffing */
 250         omap_writel(omap_readl(OMAP_TLL_CHANNEL_CONF(1)) &
 251                         ~(1<<OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF_SHIFT),
 252                         OMAP_TLL_CHANNEL_CONF(1));
 253         /* SDR Mode */
 254         omap_writel(omap_readl(OMAP_TLL_CHANNEL_CONF(1)) &
 255                         ~(1<<OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE_SHIFT),
 256                         OMAP_TLL_CHANNEL_CONF(1));
 257
 258         /* CHANNEL-3 */
 259         /* Disable AutoIdle */
 260         omap_writel(omap_readl(OMAP_TLL_CHANNEL_CONF(2)) &
 261                         ~(1<<OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE_SHIFT),
 262                         OMAP_TLL_CHANNEL_CONF(2));
 263         /* Disable BitStuffing */
 264         omap_writel(omap_readl(OMAP_TLL_CHANNEL_CONF(2)) &
 265                         ~(1<<OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF_SHIFT),
 266                         OMAP_TLL_CHANNEL_CONF(2));
 267         /* SDR Mode */
 268         omap_writel(omap_readl(OMAP_TLL_CHANNEL_CONF(2)) &
 269                         ~(1<<OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE_SHIFT),
 270                         OMAP_TLL_CHANNEL_CONF(2));
 271
 272         /* Program Common TLL register */
 273         omap_writel((1 << OMAP_TLL_SHARED_CONF_FCLK_IS_ON_SHIFT) |
 274                         (1 << OMAP_TLL_SHARED_CONF_USB_DIVRATION_SHIFT) |
 275                         (1 << OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN_SHIFT) |
 276                         (1 << OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN_SHFT),
 277                                 OMAP_TLL_SHARED_CONF);
 278
 279         /* Enable All 3 channels now */
 280         omap_writel(omap_readl(OMAP_TLL_CHANNEL_CONF(0)) |
 281                         (1<<OMAP_TLL_CHANNEL_CONF_CHANEN_SHIFT),
 282                         OMAP_TLL_CHANNEL_CONF(0));
 283
 284         omap_writel(omap_readl(OMAP_TLL_CHANNEL_CONF(1)) |
 285                         (1<<OMAP_TLL_CHANNEL_CONF_CHANEN_SHIFT),
 286                         OMAP_TLL_CHANNEL_CONF(1));
 287
 288         omap_writel(omap_readl(OMAP_TLL_CHANNEL_CONF(2)) |
 289                         (1<<OMAP_TLL_CHANNEL_CONF_CHANEN_SHIFT),
 290                         OMAP_TLL_CHANNEL_CONF(2));
 291
 292         /* test writing to ulpi scratch register */
 293         omap_writeb(0xBE, OMAP_TLL_ULPI_SCRATCH_REGISTER);
 294         dev_dbg(hcd->self.controller, "\nULPI_SCRATCH_REG 0x%02x\n",
 295                         omap_readb(OMAP_TLL_ULPI_SCRATCH_REGISTER));
 296
 297 #endif
 298
 299 #ifdef EXTERNAL_PHY_RESET
 300         /* Refer ISSUE1:
 301          * Hold the PHY in RESET for enough time till PHY is settled and ready
 302          */
 303         udelay(EXT_PHY_RESET_DELAY);
 304         omap_set_gpio_dataout(EXT_PHY_RESET_GPIO_PORT1, 1);
 305         omap_set_gpio_dataout(EXT_PHY_RESET_GPIO_PORT2, 1);
 306 #endif
 307
 308 #ifdef VBUS_INTERNAL_CHARGEPUMP_HACK
 309         /* Refer ISSUE2: LINK assumes external charge pump */
 310
 311         /* use Port1 VBUS to charge externally Port2:
 312          *      So for PHY mode operation use Port2 only
 313          */
 314         omap_writel((0xA << EHCI_INSNREG05_ULPI_REGADD_SHIFT) |/* OTG ctrl reg*/
 315                         (2 << EHCI_INSNREG05_ULPI_OPSEL_SHIFT) |/*   Write */
 316                         (1 << EHCI_INSNREG05_ULPI_PORTSEL_SHIFT) |/* Port1 */
 317                         (1 << EHCI_INSNREG05_ULPI_CONTROL_SHIFT) |/* Start */
 318                         (0x26),
 319                         EHCI_INSNREG05_ULPI);
 320
 321         while (!(omap_readl(EHCI_INSNREG05_ULPI) &
 322                 (1<<EHCI_INSNREG05_ULPI_CONTROL_SHIFT)));
 323
 324 #endif
 325
 326         return 0;
 327 }
 328
 329 /*-------------------------------------------------------------------------*/
 330
 331 static void omap_stop_ehc(struct platform_device *dev, struct usb_hcd *hcd)
 332 {
 333         struct ehci_omap_clock_defs *ehci_clocks;
 334
 335         ehci_clocks = (struct ehci_omap_clock_defs *)
 336                         (((char *)hcd_to_ehci(hcd)) + sizeof(struct ehci_hcd));
 337
 338         dev_dbg(hcd->self.controller, ": stopping TI EHCI USB Controller\n");
 339
 340         /* Reset OMAP modules for insmod/rmmod to work */
 341         omap_writel((1<<1), OMAP_UHH_SYSCONFIG);
 342         while (!(omap_readl(OMAP_UHH_SYSSTATUS) & (1<<0)));
 343         while (!(omap_readl(OMAP_UHH_SYSSTATUS) & (1<<1)));
 344         while (!(omap_readl(OMAP_UHH_SYSSTATUS) & (1<<2)));
 345         dev_dbg(hcd->self.controller,
 346                 "UHH RESET DONE OMAP_UHH_SYSSTATUS %x !!\n",
 347                         omap_readl(OMAP_UHH_SYSSTATUS));
 348
 349         omap_writel((1<<1), OMAP_USBTLL_SYSCONFIG);
 350         while (!(omap_readl(OMAP_USBTLL_SYSSTATUS) & (1<<0)));
 351         dev_dbg(hcd->self.controller, ":TLL RESEET DONE");
 352
 353         if (ehci_clocks->usbtll_fck_clk != NULL) {
 354                 clk_disable(ehci_clocks->usbtll_fck_clk);
 355                 clk_put(ehci_clocks->usbtll_fck_clk);
 356                 ehci_clocks->usbtll_fck_clk = NULL;
 357         }
 358
 359         if (ehci_clocks->usbhost_ick_clk != NULL) {
 360                 clk_disable(ehci_clocks->usbhost_ick_clk);
 361                 clk_put(ehci_clocks->usbhost_ick_clk);
 362                 ehci_clocks->usbhost_ick_clk = NULL;
 363         }
 364
 365         if (ehci_clocks->usbhost1_48m_fck_clk != NULL) {
 366                 clk_disable(ehci_clocks->usbhost1_48m_fck_clk);
 367                 clk_put(ehci_clocks->usbhost1_48m_fck_clk);
 368                 ehci_clocks->usbhost1_48m_fck_clk = NULL;
 369         }
 370
 371         if (ehci_clocks->usbhost2_120m_fck_clk != NULL) {
 372                 clk_disable(ehci_clocks->usbhost2_120m_fck_clk);
 373                 clk_put(ehci_clocks->usbhost2_120m_fck_clk);
 374                 ehci_clocks->usbhost2_120m_fck_clk = NULL;
 375         }
 376
 377         if (ehci_clocks->usbtll_ick_clk != NULL) {
 378                 clk_disable(ehci_clocks->usbtll_ick_clk);
 379                 clk_put(ehci_clocks->usbtll_ick_clk);
 380                 ehci_clocks->usbtll_ick_clk = NULL;
 381         }
 382
 383
 384 #ifdef EXTERNAL_PHY_RESET
 385         omap_free_gpio(EXT_PHY_RESET_GPIO_PORT1);
 386         omap_free_gpio(EXT_PHY_RESET_GPIO_PORT2);
 387 #endif
 388
 389         dev_dbg(hcd->self.controller,
 390                 ": Clock to USB host has been disabled\n");
 391 }
 392
 393 static const struct hc_driver ehci_omap_hc_driver;
 394
 395 /*-------------------------------------------------------------------------*/
 396 /* configure so an HC device and id are always provided */
 397 /* always called with process context; sleeping is OK */
 398
 399 /**
 400  * ehci_hcd_omap_drv_probe - initialize TI-based HCDs
 401  * Context: !in_interrupt()
 402  *
 403  * Allocates basic resources for this USB host controller, and
 404  * then invokes the start() method for the HCD associated with it
 405  * through the hotplug entry's driver_data.
 406  *
 407  */
 408 static int ehci_hcd_omap_drv_probe(struct platform_device *dev)
 409 {
 410         int retval = 0;
 411         struct usb_hcd *hcd;
 412         struct ehci_hcd *ehci;
 413
 414         dev_dbg(&dev->dev, "ehci_hcd_omap_drv_probe()");
 415
 416         if (usb_disabled())
 417                 return -ENODEV;
 418
 419         if (dev->resource[1].flags != IORESOURCE_IRQ) {
 420                 dev_dbg(&dev->dev, "resource[1] is not IORESOURCE_IRQ");
 421                 retval = -ENOMEM;
 422         }
 423
 424         hcd = usb_create_hcd(&ehci_omap_hc_driver, &dev->dev, dev->dev.bus_id);
 425         if (!hcd)
 426                 return -ENOMEM;
 427
 428         retval = omap_start_ehc(dev, hcd);
 429         if (retval)
 430                 return retval;
 431
 432         hcd->rsrc_start = 0;
 433         hcd->rsrc_len = 0;
 434         hcd->rsrc_start = dev->resource[0].start;
 435         hcd->rsrc_len = dev->resource[0].end - dev->resource[0].start + 1;
 436
 437         hcd->regs = (void __iomem *) (int) IO_ADDRESS(hcd->rsrc_start);
 438
 439         ehci = hcd_to_ehci(hcd);
 440         ehci->caps = hcd->regs;
 441
 442         ehci->regs = hcd->regs + HC_LENGTH(readl(&ehci->caps->hc_capbase));
 443         /* cache this readonly data; minimize chip reads */
 444         ehci->hcs_params = readl(&ehci->caps->hcs_params);
 445
 446         /* SET 1 micro-frame Interrupt interval */
 447         writel(readl(&ehci->regs->command) | (1<<16), &ehci->regs->command);
 448
 449         retval = usb_add_hcd(hcd, dev->resource[1].start,
 450                                 IRQF_DISABLED | IRQF_SHARED);
 451         if (retval == 0)
 452                 return retval;
 453
 454         dev_dbg(hcd->self.controller, "ERR: add_hcd");
 455         omap_stop_ehc(dev, hcd);
 456
 457         usb_put_hcd(hcd);
 458         return retval;
 459 }
 460
 461 /*-------------------------------------------------------------------------*/
 462
 463 /* may be called without controller electrically present */
 464 /* may be called with controller, bus, and devices active */
 465
 466 /**
 467  * ehci_hcd_omap_drv_remove - shutdown processing for EHCI HCDs
 468  * @dev: USB Host Controller being removed
 469  * Context: !in_interrupt()
 470  *
 471  * Reverses the effect of usb_ehci_hcd_omap_probe(), first invoking
 472  * the HCD's stop() method.  It is always called from a thread
 473  * context, normally "rmmod", "apmd", or something similar.
 474  *
 475  */
 476 static int ehci_hcd_omap_drv_remove(struct platform_device *dev)
 477 {
 478         struct usb_hcd *hcd = platform_get_drvdata(dev);
 479
 480         dev_dbg(&dev->dev, "ehci_hcd_omap_drv_remove()");
 481
 482         usb_remove_hcd(hcd);
 483         usb_put_hcd(hcd);
 484         omap_stop_ehc(dev, hcd);
 485
 486         return 0;
 487 }
 488
 489 /*-------------------------------------------------------------------------*/
 490 #ifdef CONFIG_PM
 491 static int omap_ehci_bus_suspend(struct usb_hcd *hcd)
 492 {
 493         return ehci_bus_suspend(hcd);
 494 }
 495
 496 static int omap_ehci_bus_resume(struct usb_hcd *hcd)
 497 {
 498         return ehci_bus_resume(hcd);
 499 }
 500 #endif
 501 /*-------------------------------------------------------------------------*/
 502
 503 static const struct hc_driver ehci_omap_hc_driver = {
 504         .description = hcd_name,
 505         .product_desc = "OMAP-EHCI Host Controller",
 506         .hcd_priv_size = sizeof(struct ehci_hcd)
 507                                 + sizeof(struct ehci_omap_clock_defs),
 508
 509         /*
 510          * generic hardware linkage
 511          */
 512         .irq = ehci_irq,
 513         .flags = HCD_MEMORY | HCD_USB2,
 514
 515         /*
 516          * basic lifecycle operations
 517          */
 518         .reset = ehci_init,
 519         .start = ehci_run,
 520         .stop = ehci_stop,
 521         .shutdown = ehci_shutdown,
 522
 523         /*
 524          * managing i/o requests and associated device resources
 525          */
 526         .urb_enqueue = ehci_urb_enqueue,
 527         .urb_dequeue = ehci_urb_dequeue,
 528         .endpoint_disable = ehci_endpoint_disable,
 529
 530         /*
 531          * scheduling support
 532          */
 533         .get_frame_number = ehci_get_frame,
 534
 535         /*
 536          * root hub support
 537          */
 538         .hub_status_data = ehci_hub_status_data,
 539         .hub_control = ehci_hub_control,
 540 #ifdef  CONFIG_PM
 541         .bus_suspend = omap_ehci_bus_suspend,
 542         .bus_resume = omap_ehci_bus_resume,
 543 #endif
 544 };
 545
 546 /*-------------------------------------------------------------------------*/
 547 MODULE_ALIAS("omap-ehci");
 548 static struct platform_driver ehci_hcd_omap_driver = {
 549         .probe = ehci_hcd_omap_drv_probe,
 550         .remove = ehci_hcd_omap_drv_remove,
 551         .shutdown = usb_hcd_platform_shutdown,
 552         /*.suspend      = ehci_hcd_omap_drv_suspend, */
 553         /*.resume       = ehci_hcd_omap_drv_resume, */
 554         .driver = {
 555                 .name = "ehci-omap",
 556                 .bus = &platform_bus_type
 557         }
 558 };