drivers/usb/gadget/omap_udc.c

   1 /*
   2  * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
   3  *
   4  * Copyright (C) 2004 Texas Instruments, Inc.
   5  * Copyright (C) 2004-2005 David Brownell
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 #undef  DEBUG
  23 #undef  VERBOSE
  24
  25 #include <linux/config.h>
  26 #include <linux/module.h>
  27 #include <linux/kernel.h>
  28 #include <linux/ioport.h>
  29 #include <linux/types.h>
  30 #include <linux/errno.h>
  31 #include <linux/delay.h>
  32 #include <linux/sched.h>
  33 #include <linux/slab.h>
  34 #include <linux/init.h>
  35 #include <linux/timer.h>
  36 #include <linux/list.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/proc_fs.h>
  39 #include <linux/mm.h>
  40 #include <linux/moduleparam.h>
  41 #include <linux/platform_device.h>
  42 #include <linux/usb_ch9.h>
  43 #include <linux/usb_gadget.h>
  44 #include <linux/usb_otg.h>
  45 #include <linux/dma-mapping.h>
  46
  47 #include <asm/byteorder.h>
  48 #include <asm/io.h>
  49 #include <asm/irq.h>
  50 #include <asm/system.h>
  51 #include <asm/unaligned.h>
  52 #include <asm/mach-types.h>
  53
  54 #include <asm/arch/dma.h>
  55 #include <asm/arch/usb.h>
  56
  57 #include "omap_udc.h"
  58
  59 #undef  USB_TRACE
  60
  61 /* bulk DMA seems to be behaving for both IN and OUT */
  62 #define USE_DMA
  63
  64 /* ISO too */
  65 #define USE_ISO
  66
  67 #define DRIVER_DESC     "OMAP UDC driver"
  68 #define DRIVER_VERSION  "4 October 2004"
  69
  70 #define DMA_ADDR_INVALID        (~(dma_addr_t)0)
  71
  72
  73 /*
  74  * The OMAP UDC needs _very_ early endpoint setup:  before enabling the
  75  * D+ pullup to allow enumeration.  That's too early for the gadget
  76  * framework to use from usb_endpoint_enable(), which happens after
  77  * enumeration as part of activating an interface.  (But if we add an
  78  * optional new "UDC not yet running" state to the gadget driver model,
  79  * even just during driver binding, the endpoint autoconfig logic is the
  80  * natural spot to manufacture new endpoints.)
  81  *
  82  * So instead of using endpoint enable calls to control the hardware setup,
  83  * this driver defines a "fifo mode" parameter.  It's used during driver
  84  * initialization to choose among a set of pre-defined endpoint configs.
  85  * See omap_udc_setup() for available modes, or to add others.  That code
  86  * lives in an init section, so use this driver as a module if you need
  87  * to change the fifo mode after the kernel boots.
  88  *
  89  * Gadget drivers normally ignore endpoints they don't care about, and
  90  * won't include them in configuration descriptors.  That means only
  91  * misbehaving hosts would even notice they exist.
  92  */
  93 #ifdef  USE_ISO
  94 static unsigned fifo_mode = 3;
  95 #else
  96 static unsigned fifo_mode = 0;
  97 #endif
  98
  99 /* "modprobe omap_udc fifo_mode=42", or else as a kernel
 100  * boot parameter "omap_udc:fifo_mode=42"
 101  */
 102 module_param (fifo_mode, uint, 0);
 103 MODULE_PARM_DESC (fifo_mode, "endpoint setup (0 == default)");
 104
 105 #ifdef  USE_DMA
 106 static unsigned use_dma = 1;
 107
 108 /* "modprobe omap_udc use_dma=y", or else as a kernel
 109  * boot parameter "omap_udc:use_dma=y"
 110  */
 111 module_param (use_dma, bool, 0);
 112 MODULE_PARM_DESC (use_dma, "enable/disable DMA");
 113 #else   /* !USE_DMA */
 114
 115 /* save a bit of code */
 116 #define use_dma         0
 117 #endif  /* !USE_DMA */
 118
 119
 120 static const char driver_name [] = "omap_udc";
 121 static const char driver_desc [] = DRIVER_DESC;
 122
 123 /*-------------------------------------------------------------------------*/
 124
 125 /* there's a notion of "current endpoint" for modifying endpoint
 126  * state, and PIO access to its FIFO.
 127  */
 128
 129 static void use_ep(struct omap_ep *ep, u16 select)
 130 {
 131         u16     num = ep->bEndpointAddress & 0x0f;
 132
 133         if (ep->bEndpointAddress & USB_DIR_IN)
 134                 num |= UDC_EP_DIR;
 135         UDC_EP_NUM_REG = num | select;
 136         /* when select, MUST deselect later !! */
 137 }
 138
 139 static inline void deselect_ep(void)
 140 {
 141         UDC_EP_NUM_REG &= ~UDC_EP_SEL;
 142         /* 6 wait states before TX will happen */
 143 }
 144
 145 static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
 146
 147 /*-------------------------------------------------------------------------*/
 148
 149 static int omap_ep_enable(struct usb_ep *_ep,
 150                 const struct usb_endpoint_descriptor *desc)
 151 {
 152         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 153         struct omap_udc *udc;
 154         unsigned long   flags;
 155         u16             maxp;
 156
 157         /* catch various bogus parameters */
 158         if (!_ep || !desc || ep->desc
 159                         || desc->bDescriptorType != USB_DT_ENDPOINT
 160                         || ep->bEndpointAddress != desc->bEndpointAddress
 161                         || ep->maxpacket < le16_to_cpu
 162                                                 (desc->wMaxPacketSize)) {
 163                 DBG("%s, bad ep or descriptor\n", __FUNCTION__);
 164                 return -EINVAL;
 165         }
 166         maxp = le16_to_cpu (desc->wMaxPacketSize);
 167         if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
 168                                 && maxp != ep->maxpacket)
 169                         || le16_to_cpu(desc->wMaxPacketSize) > ep->maxpacket
 170                         || !desc->wMaxPacketSize) {
 171                 DBG("%s, bad %s maxpacket\n", __FUNCTION__, _ep->name);
 172                 return -ERANGE;
 173         }
 174
 175 #ifdef  USE_ISO
 176         if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
 177                                 && desc->bInterval != 1)) {
 178                 /* hardware wants period = 1; USB allows 2^(Interval-1) */
 179                 DBG("%s, unsupported ISO period %dms\n", _ep->name,
 180                                 1 << (desc->bInterval - 1));
 181                 return -EDOM;
 182         }
 183 #else
 184         if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 185                 DBG("%s, ISO nyet\n", _ep->name);
 186                 return -EDOM;
 187         }
 188 #endif
 189
 190         /* xfer types must match, except that interrupt ~= bulk */
 191         if (ep->bmAttributes != desc->bmAttributes
 192                         && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
 193                         && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
 194                 DBG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
 195                 return -EINVAL;
 196         }
 197
 198         udc = ep->udc;
 199         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
 200                 DBG("%s, bogus device state\n", __FUNCTION__);
 201                 return -ESHUTDOWN;
 202         }
 203
 204         spin_lock_irqsave(&udc->lock, flags);
 205
 206         ep->desc = desc;
 207         ep->irqs = 0;
 208         ep->stopped = 0;
 209         ep->ep.maxpacket = maxp;
 210
 211         /* set endpoint to initial state */
 212         ep->dma_channel = 0;
 213         ep->has_dma = 0;
 214         ep->lch = -1;
 215         use_ep(ep, UDC_EP_SEL);
 216         UDC_CTRL_REG = udc->clr_halt;
 217         ep->ackwait = 0;
 218         deselect_ep();
 219
 220         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
 221                 list_add(&ep->iso, &udc->iso);
 222
 223         /* maybe assign a DMA channel to this endpoint */
 224         if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
 225                 /* FIXME ISO can dma, but prefers first channel */
 226                 dma_channel_claim(ep, 0);
 227
 228         /* PIO OUT may RX packets */
 229         if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
 230                         && !ep->has_dma
 231                         && !(ep->bEndpointAddress & USB_DIR_IN)) {
 232                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
 233                 ep->ackwait = 1 + ep->double_buf;
 234         }
 235
 236         spin_unlock_irqrestore(&udc->lock, flags);
 237         VDBG("%s enabled\n", _ep->name);
 238         return 0;
 239 }
 240
 241 static void nuke(struct omap_ep *, int status);
 242
 243 static int omap_ep_disable(struct usb_ep *_ep)
 244 {
 245         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 246         unsigned long   flags;
 247
 248         if (!_ep || !ep->desc) {
 249                 DBG("%s, %s not enabled\n", __FUNCTION__,
 250                         _ep ? ep->ep.name : NULL);
 251                 return -EINVAL;
 252         }
 253
 254         spin_lock_irqsave(&ep->udc->lock, flags);
 255         ep->desc = NULL;
 256         nuke (ep, -ESHUTDOWN);
 257         ep->ep.maxpacket = ep->maxpacket;
 258         ep->has_dma = 0;
 259         UDC_CTRL_REG = UDC_SET_HALT;
 260         list_del_init(&ep->iso);
 261         del_timer(&ep->timer);
 262
 263         spin_unlock_irqrestore(&ep->udc->lock, flags);
 264
 265         VDBG("%s disabled\n", _ep->name);
 266         return 0;
 267 }
 268
 269 /*-------------------------------------------------------------------------*/
 270
 271 static struct usb_request *
 272 omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
 273 {
 274         struct omap_req *req;
 275
 276         req = kmalloc(sizeof *req, gfp_flags);
 277         if (req) {
 278                 memset (req, 0, sizeof *req);
 279                 req->req.dma = DMA_ADDR_INVALID;
 280                 INIT_LIST_HEAD (&req->queue);
 281         }
 282         return &req->req;
 283 }
 284
 285 static void
 286 omap_free_request(struct usb_ep *ep, struct usb_request *_req)
 287 {
 288         struct omap_req *req = container_of(_req, struct omap_req, req);
 289
 290         if (_req)
 291                 kfree (req);
 292 }
 293
 294 /*-------------------------------------------------------------------------*/
 295
 296 static void *
 297 omap_alloc_buffer(
 298         struct usb_ep   *_ep,
 299         unsigned        bytes,
 300         dma_addr_t      *dma,
 301         gfp_t           gfp_flags
 302 )
 303 {
 304         void            *retval;
 305         struct omap_ep  *ep;
 306
 307         ep = container_of(_ep, struct omap_ep, ep);
 308         if (use_dma && ep->has_dma) {
 309                 static int      warned;
 310                 if (!warned && bytes < PAGE_SIZE) {
 311                         dev_warn(ep->udc->gadget.dev.parent,
 312                                 "using dma_alloc_coherent for "
 313                                 "small allocations wastes memory\n");
 314                         warned++;
 315                 }
 316                 return dma_alloc_coherent(ep->udc->gadget.dev.parent,
 317                                 bytes, dma, gfp_flags);
 318         }
 319
 320         retval = kmalloc(bytes, gfp_flags);
 321         if (retval)
 322                 *dma = virt_to_phys(retval);
 323         return retval;
 324 }
 325
 326 static void omap_free_buffer(
 327         struct usb_ep   *_ep,
 328         void            *buf,
 329         dma_addr_t      dma,
 330         unsigned        bytes
 331 )
 332 {
 333         struct omap_ep  *ep;
 334
 335         ep = container_of(_ep, struct omap_ep, ep);
 336         if (use_dma && _ep && ep->has_dma)
 337                 dma_free_coherent(ep->udc->gadget.dev.parent, bytes, buf, dma);
 338         else
 339                 kfree (buf);
 340 }
 341
 342 /*-------------------------------------------------------------------------*/
 343
 344 static void
 345 done(struct omap_ep *ep, struct omap_req *req, int status)
 346 {
 347         unsigned                stopped = ep->stopped;
 348
 349         list_del_init(&req->queue);
 350
 351         if (req->req.status == -EINPROGRESS)
 352                 req->req.status = status;
 353         else
 354                 status = req->req.status;
 355
 356         if (use_dma && ep->has_dma) {
 357                 if (req->mapped) {
 358                         dma_unmap_single(ep->udc->gadget.dev.parent,
 359                                 req->req.dma, req->req.length,
 360                                 (ep->bEndpointAddress & USB_DIR_IN)
 361                                         ? DMA_TO_DEVICE
 362                                         : DMA_FROM_DEVICE);
 363                         req->req.dma = DMA_ADDR_INVALID;
 364                         req->mapped = 0;
 365                 } else
 366                         dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
 367                                 req->req.dma, req->req.length,
 368                                 (ep->bEndpointAddress & USB_DIR_IN)
 369                                         ? DMA_TO_DEVICE
 370                                         : DMA_FROM_DEVICE);
 371         }
 372
 373 #ifndef USB_TRACE
 374         if (status && status != -ESHUTDOWN)
 375 #endif
 376                 VDBG("complete %s req %p stat %d len %u/%u\n",
 377                         ep->ep.name, &req->req, status,
 378                         req->req.actual, req->req.length);
 379
 380         /* don't modify queue heads during completion callback */
 381         ep->stopped = 1;
 382         spin_unlock(&ep->udc->lock);
 383         req->req.complete(&ep->ep, &req->req);
 384         spin_lock(&ep->udc->lock);
 385         ep->stopped = stopped;
 386 }
 387
 388 /*-------------------------------------------------------------------------*/
 389
 390 #define UDC_FIFO_FULL           (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
 391 #define UDC_FIFO_UNWRITABLE     (UDC_EP_HALTED | UDC_FIFO_FULL)
 392
 393 #define FIFO_EMPTY      (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
 394 #define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
 395
 396 static inline int
 397 write_packet(u8 *buf, struct omap_req *req, unsigned max)
 398 {
 399         unsigned        len;
 400         u16             *wp;
 401
 402         len = min(req->req.length - req->req.actual, max);
 403         req->req.actual += len;
 404
 405         max = len;
 406         if (likely((((int)buf) & 1) == 0)) {
 407                 wp = (u16 *)buf;
 408                 while (max >= 2) {
 409                         UDC_DATA_REG = *wp++;
 410                         max -= 2;
 411                 }
 412                 buf = (u8 *)wp;
 413         }
 414         while (max--)
 415                 *(volatile u8 *)&UDC_DATA_REG = *buf++;
 416         return len;
 417 }
 418
 419 // FIXME change r/w fifo calling convention
 420
 421
 422 // return:  0 = still running, 1 = completed, negative = errno
 423 static int write_fifo(struct omap_ep *ep, struct omap_req *req)
 424 {
 425         u8              *buf;
 426         unsigned        count;
 427         int             is_last;
 428         u16             ep_stat;
 429
 430         buf = req->req.buf + req->req.actual;
 431         prefetch(buf);
 432
 433         /* PIO-IN isn't double buffered except for iso */
 434         ep_stat = UDC_STAT_FLG_REG;
 435         if (ep_stat & UDC_FIFO_UNWRITABLE)
 436                 return 0;
 437
 438         count = ep->ep.maxpacket;
 439         count = write_packet(buf, req, count);
 440         UDC_CTRL_REG = UDC_SET_FIFO_EN;
 441         ep->ackwait = 1;
 442
 443         /* last packet is often short (sometimes a zlp) */
 444         if (count != ep->ep.maxpacket)
 445                 is_last = 1;
 446         else if (req->req.length == req->req.actual
 447                         && !req->req.zero)
 448                 is_last = 1;
 449         else
 450                 is_last = 0;
 451
 452         /* NOTE:  requests complete when all IN data is in a
 453          * FIFO (or sometimes later, if a zlp was needed).
 454          * Use usb_ep_fifo_status() where needed.
 455          */
 456         if (is_last)
 457                 done(ep, req, 0);
 458         return is_last;
 459 }
 460
 461 static inline int
 462 read_packet(u8 *buf, struct omap_req *req, unsigned avail)
 463 {
 464         unsigned        len;
 465         u16             *wp;
 466
 467         len = min(req->req.length - req->req.actual, avail);
 468         req->req.actual += len;
 469         avail = len;
 470
 471         if (likely((((int)buf) & 1) == 0)) {
 472                 wp = (u16 *)buf;
 473                 while (avail >= 2) {
 474                         *wp++ = UDC_DATA_REG;
 475                         avail -= 2;
 476                 }
 477                 buf = (u8 *)wp;
 478         }
 479         while (avail--)
 480                 *buf++ = *(volatile u8 *)&UDC_DATA_REG;
 481         return len;
 482 }
 483
 484 // return:  0 = still running, 1 = queue empty, negative = errno
 485 static int read_fifo(struct omap_ep *ep, struct omap_req *req)
 486 {
 487         u8              *buf;
 488         unsigned        count, avail;
 489         int             is_last;
 490
 491         buf = req->req.buf + req->req.actual;
 492         prefetchw(buf);
 493
 494         for (;;) {
 495                 u16     ep_stat = UDC_STAT_FLG_REG;
 496
 497                 is_last = 0;
 498                 if (ep_stat & FIFO_EMPTY) {
 499                         if (!ep->double_buf)
 500                                 break;
 501                         ep->fnf = 1;
 502                 }
 503                 if (ep_stat & UDC_EP_HALTED)
 504                         break;
 505
 506                 if (ep_stat & UDC_FIFO_FULL)
 507                         avail = ep->ep.maxpacket;
 508                 else  {
 509                         avail = UDC_RXFSTAT_REG;
 510                         ep->fnf = ep->double_buf;
 511                 }
 512                 count = read_packet(buf, req, avail);
 513
 514                 /* partial packet reads may not be errors */
 515                 if (count < ep->ep.maxpacket) {
 516                         is_last = 1;
 517                         /* overflowed this request?  flush extra data */
 518                         if (count != avail) {
 519                                 req->req.status = -EOVERFLOW;
 520                                 avail -= count;
 521                                 while (avail--)
 522                                         (void) *(volatile u8 *)&UDC_DATA_REG;
 523                         }
 524                 } else if (req->req.length == req->req.actual)
 525                         is_last = 1;
 526                 else
 527                         is_last = 0;
 528
 529                 if (!ep->bEndpointAddress)
 530                         break;
 531                 if (is_last)
 532                         done(ep, req, 0);
 533                 break;
 534         }
 535         return is_last;
 536 }
 537
 538 /*-------------------------------------------------------------------------*/
 539
 540 static inline dma_addr_t dma_csac(unsigned lch)
 541 {
 542         dma_addr_t      csac;
 543
 544         /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
 545          * read before the DMA controller finished disabling the channel.
 546          */
 547         csac = OMAP_DMA_CSAC_REG(lch);
 548         if (csac == 0)
 549                 csac = OMAP_DMA_CSAC_REG(lch);
 550         return csac;
 551 }
 552
 553 static inline dma_addr_t dma_cdac(unsigned lch)
 554 {
 555         dma_addr_t      cdac;
 556
 557         /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
 558          * read before the DMA controller finished disabling the channel.
 559          */
 560         cdac = OMAP_DMA_CDAC_REG(lch);
 561         if (cdac == 0)
 562                 cdac = OMAP_DMA_CDAC_REG(lch);
 563         return cdac;
 564 }
 565
 566 static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
 567 {
 568         dma_addr_t      end;
 569
 570         /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
 571          * the last transfer's bytecount by more than a FIFO's worth.
 572          */
 573         if (cpu_is_omap15xx())
 574                 return 0;
 575
 576         end = dma_csac(ep->lch);
 577         if (end == ep->dma_counter)
 578                 return 0;
 579
 580         end |= start & (0xffff << 16);
 581         if (end < start)
 582                 end += 0x10000;
 583         return end - start;
 584 }
 585
 586 #define DMA_DEST_LAST(x) (cpu_is_omap15xx() \
 587                 ? OMAP_DMA_CSAC_REG(x) /* really: CPC */ \
 588                 : dma_cdac(x))
 589
 590 static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
 591 {
 592         dma_addr_t      end;
 593
 594         end = DMA_DEST_LAST(ep->lch);
 595         if (end == ep->dma_counter)
 596                 return 0;
 597
 598         end |= start & (0xffff << 16);
 599         if (cpu_is_omap15xx())
 600                 end++;
 601         if (end < start)
 602                 end += 0x10000;
 603         return end - start;
 604 }
 605
 606
 607 /* Each USB transfer request using DMA maps to one or more DMA transfers.
 608  * When DMA completion isn't request completion, the UDC continues with
 609  * the next DMA transfer for that USB transfer.
 610  */
 611
 612 static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
 613 {
 614         u16             txdma_ctrl;
 615         unsigned        length = req->req.length - req->req.actual;
 616         const int       sync_mode = cpu_is_omap15xx()
 617                                 ? OMAP_DMA_SYNC_FRAME
 618                                 : OMAP_DMA_SYNC_ELEMENT;
 619
 620         /* measure length in either bytes or packets */
 621         if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
 622                         || (cpu_is_omap15xx() && length < ep->maxpacket)) {
 623                 txdma_ctrl = UDC_TXN_EOT | length;
 624                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
 625                                 length, 1, sync_mode, 0, 0);
 626         } else {
 627                 length = min(length / ep->maxpacket,
 628                                 (unsigned) UDC_TXN_TSC + 1);
 629                 txdma_ctrl = length;
 630                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
 631                                 ep->ep.maxpacket >> 1, length, sync_mode,
 632                                 0, 0);
 633                 length *= ep->maxpacket;
 634         }
 635         omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
 636                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
 637                 0, 0);
 638
 639         omap_start_dma(ep->lch);
 640         ep->dma_counter = dma_csac(ep->lch);
 641         UDC_DMA_IRQ_EN_REG |= UDC_TX_DONE_IE(ep->dma_channel);
 642         UDC_TXDMA_REG(ep->dma_channel) = UDC_TXN_START | txdma_ctrl;
 643         req->dma_bytes = length;
 644 }
 645
 646 static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
 647 {
 648         if (status == 0) {
 649                 req->req.actual += req->dma_bytes;
 650
 651                 /* return if this request needs to send data or zlp */
 652                 if (req->req.actual < req->req.length)
 653                         return;
 654                 if (req->req.zero
 655                                 && req->dma_bytes != 0
 656                                 && (req->req.actual % ep->maxpacket) == 0)
 657                         return;
 658         } else
 659                 req->req.actual += dma_src_len(ep, req->req.dma
 660                                                         + req->req.actual);
 661
 662         /* tx completion */
 663         omap_stop_dma(ep->lch);
 664         UDC_DMA_IRQ_EN_REG &= ~UDC_TX_DONE_IE(ep->dma_channel);
 665         done(ep, req, status);
 666 }
 667
 668 static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
 669 {
 670         unsigned packets;
 671
 672         /* NOTE:  we filtered out "short reads" before, so we know
 673          * the buffer has only whole numbers of packets.
 674          */
 675
 676         /* set up this DMA transfer, enable the fifo, start */
 677         packets = (req->req.length - req->req.actual) / ep->ep.maxpacket;
 678         packets = min(packets, (unsigned)UDC_RXN_TC + 1);
 679         req->dma_bytes = packets * ep->ep.maxpacket;
 680         omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
 681                         ep->ep.maxpacket >> 1, packets,
 682                         OMAP_DMA_SYNC_ELEMENT,
 683                         0, 0);
 684         omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
 685                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
 686                 0, 0);
 687         ep->dma_counter = DMA_DEST_LAST(ep->lch);
 688
 689         UDC_RXDMA_REG(ep->dma_channel) = UDC_RXN_STOP | (packets - 1);
 690         UDC_DMA_IRQ_EN_REG |= UDC_RX_EOT_IE(ep->dma_channel);
 691         UDC_EP_NUM_REG = (ep->bEndpointAddress & 0xf);
 692         UDC_CTRL_REG = UDC_SET_FIFO_EN;
 693
 694         omap_start_dma(ep->lch);
 695 }
 696
 697 static void
 698 finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
 699 {
 700         u16     count;
 701
 702         if (status == 0)
 703                 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
 704         count = dma_dest_len(ep, req->req.dma + req->req.actual);
 705         count += req->req.actual;
 706         if (one)
 707                 count--;
 708         if (count <= req->req.length)
 709                 req->req.actual = count;
 710
 711         if (count != req->dma_bytes || status)
 712                 omap_stop_dma(ep->lch);
 713
 714         /* if this wasn't short, request may need another transfer */
 715         else if (req->req.actual < req->req.length)
 716                 return;
 717
 718         /* rx completion */
 719         UDC_DMA_IRQ_EN_REG &= ~UDC_RX_EOT_IE(ep->dma_channel);
 720         done(ep, req, status);
 721 }
 722
 723 static void dma_irq(struct omap_udc *udc, u16 irq_src)
 724 {
 725         u16             dman_stat = UDC_DMAN_STAT_REG;
 726         struct omap_ep  *ep;
 727         struct omap_req *req;
 728
 729         /* IN dma: tx to host */
 730         if (irq_src & UDC_TXN_DONE) {
 731                 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
 732                 ep->irqs++;
 733                 /* can see TXN_DONE after dma abort */
 734                 if (!list_empty(&ep->queue)) {
 735                         req = container_of(ep->queue.next,
 736                                                 struct omap_req, queue);
 737                         finish_in_dma(ep, req, 0);
 738                 }
 739                 UDC_IRQ_SRC_REG = UDC_TXN_DONE;
 740
 741                 if (!list_empty (&ep->queue)) {
 742                         req = container_of(ep->queue.next,
 743                                         struct omap_req, queue);
 744                         next_in_dma(ep, req);
 745                 }
 746         }
 747
 748         /* OUT dma: rx from host */
 749         if (irq_src & UDC_RXN_EOT) {
 750                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
 751                 ep->irqs++;
 752                 /* can see RXN_EOT after dma abort */
 753                 if (!list_empty(&ep->queue)) {
 754                         req = container_of(ep->queue.next,
 755                                         struct omap_req, queue);
 756                         finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
 757                 }
 758                 UDC_IRQ_SRC_REG = UDC_RXN_EOT;
 759
 760                 if (!list_empty (&ep->queue)) {
 761                         req = container_of(ep->queue.next,
 762                                         struct omap_req, queue);
 763                         next_out_dma(ep, req);
 764                 }
 765         }
 766
 767         if (irq_src & UDC_RXN_CNT) {
 768                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
 769                 ep->irqs++;
 770                 /* omap15xx does this unasked... */
 771                 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
 772                 UDC_IRQ_SRC_REG = UDC_RXN_CNT;
 773         }
 774 }
 775
 776 static void dma_error(int lch, u16 ch_status, void *data)
 777 {
 778         struct omap_ep  *ep = data;
 779
 780         /* if ch_status & OMAP_DMA_DROP_IRQ ... */
 781         /* if ch_status & OMAP_DMA_TOUT_IRQ ... */
 782         ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
 783
 784         /* complete current transfer ... */
 785 }
 786
 787 static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
 788 {
 789         u16     reg;
 790         int     status, restart, is_in;
 791
 792         is_in = ep->bEndpointAddress & USB_DIR_IN;
 793         if (is_in)
 794                 reg = UDC_TXDMA_CFG_REG;
 795         else
 796                 reg = UDC_RXDMA_CFG_REG;
 797         reg |= UDC_DMA_REQ;             /* "pulse" activated */
 798
 799         ep->dma_channel = 0;
 800         ep->lch = -1;
 801         if (channel == 0 || channel > 3) {
 802                 if ((reg & 0x0f00) == 0)
 803                         channel = 3;
 804                 else if ((reg & 0x00f0) == 0)
 805                         channel = 2;
 806                 else if ((reg & 0x000f) == 0)   /* preferred for ISO */
 807                         channel = 1;
 808                 else {
 809                         status = -EMLINK;
 810                         goto just_restart;
 811                 }
 812         }
 813         reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
 814         ep->dma_channel = channel;
 815
 816         if (is_in) {
 817                 status = omap_request_dma(OMAP_DMA_USB_W2FC_TX0 - 1 + channel,
 818                         ep->ep.name, dma_error, ep, &ep->lch);
 819                 if (status == 0) {
 820                         UDC_TXDMA_CFG_REG = reg;
 821                         /* EMIFF */
 822                         omap_set_dma_src_burst_mode(ep->lch,
 823                                                 OMAP_DMA_DATA_BURST_4);
 824                         omap_set_dma_src_data_pack(ep->lch, 1);
 825                         /* TIPB */
 826                         omap_set_dma_dest_params(ep->lch,
 827                                 OMAP_DMA_PORT_TIPB,
 828                                 OMAP_DMA_AMODE_CONSTANT,
 829                                 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG),
 830                                 0, 0);
 831                 }
 832         } else {
 833                 status = omap_request_dma(OMAP_DMA_USB_W2FC_RX0 - 1 + channel,
 834                         ep->ep.name, dma_error, ep, &ep->lch);
 835                 if (status == 0) {
 836                         UDC_RXDMA_CFG_REG = reg;
 837                         /* TIPB */
 838                         omap_set_dma_src_params(ep->lch,
 839                                 OMAP_DMA_PORT_TIPB,
 840                                 OMAP_DMA_AMODE_CONSTANT,
 841                                 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG),
 842                                 0, 0);
 843                         /* EMIFF */
 844                         omap_set_dma_dest_burst_mode(ep->lch,
 845                                                 OMAP_DMA_DATA_BURST_4);
 846                         omap_set_dma_dest_data_pack(ep->lch, 1);
 847                 }
 848         }
 849         if (status)
 850                 ep->dma_channel = 0;
 851         else {
 852                 ep->has_dma = 1;
 853                 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
 854
 855                 /* channel type P: hw synch (fifo) */
 856                 if (!cpu_is_omap15xx())
 857                         OMAP1_DMA_LCH_CTRL_REG(ep->lch) = 2;
 858         }
 859
 860 just_restart:
 861         /* restart any queue, even if the claim failed  */
 862         restart = !ep->stopped && !list_empty(&ep->queue);
 863
 864         if (status)
 865                 DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
 866                         restart ? " (restart)" : "");
 867         else
 868                 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
 869                         is_in ? 't' : 'r',
 870                         ep->dma_channel - 1, ep->lch,
 871                         restart ? " (restart)" : "");
 872
 873         if (restart) {
 874                 struct omap_req *req;
 875                 req = container_of(ep->queue.next, struct omap_req, queue);
 876                 if (ep->has_dma)
 877                         (is_in ? next_in_dma : next_out_dma)(ep, req);
 878                 else {
 879                         use_ep(ep, UDC_EP_SEL);
 880                         (is_in ? write_fifo : read_fifo)(ep, req);
 881                         deselect_ep();
 882                         if (!is_in) {
 883                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
 884                                 ep->ackwait = 1 + ep->double_buf;
 885                         }
 886                         /* IN: 6 wait states before it'll tx */
 887                 }
 888         }
 889 }
 890
 891 static void dma_channel_release(struct omap_ep *ep)
 892 {
 893         int             shift = 4 * (ep->dma_channel - 1);
 894         u16             mask = 0x0f << shift;
 895         struct omap_req *req;
 896         int             active;
 897
 898         /* abort any active usb transfer request */
 899         if (!list_empty(&ep->queue))
 900                 req = container_of(ep->queue.next, struct omap_req, queue);
 901         else
 902                 req = NULL;
 903
 904         active = ((1 << 7) & OMAP_DMA_CCR_REG(ep->lch)) != 0;
 905
 906         DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
 907                         active ? "active" : "idle",
 908                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
 909                         ep->dma_channel - 1, req);
 910
 911         /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
 912          * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
 913          */
 914
 915         /* wait till current packet DMA finishes, and fifo empties */
 916         if (ep->bEndpointAddress & USB_DIR_IN) {
 917                 UDC_TXDMA_CFG_REG = (UDC_TXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
 918
 919                 if (req) {
 920                         finish_in_dma(ep, req, -ECONNRESET);
 921
 922                         /* clear FIFO; hosts probably won't empty it */
 923                         use_ep(ep, UDC_EP_SEL);
 924                         UDC_CTRL_REG = UDC_CLR_EP;
 925                         deselect_ep();
 926                 }
 927                 while (UDC_TXDMA_CFG_REG & mask)
 928                         udelay(10);
 929         } else {
 930                 UDC_RXDMA_CFG_REG = (UDC_RXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
 931
 932                 /* dma empties the fifo */
 933                 while (UDC_RXDMA_CFG_REG & mask)
 934                         udelay(10);
 935                 if (req)
 936                         finish_out_dma(ep, req, -ECONNRESET, 0);
 937         }
 938         omap_free_dma(ep->lch);
 939         ep->dma_channel = 0;
 940         ep->lch = -1;
 941         /* has_dma still set, till endpoint is fully quiesced */
 942 }
 943
 944
 945 /*-------------------------------------------------------------------------*/
 946
 947 static int
 948 omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 949 {
 950         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 951         struct omap_req *req = container_of(_req, struct omap_req, req);
 952         struct omap_udc *udc;
 953         unsigned long   flags;
 954         int             is_iso = 0;
 955
 956         /* catch various bogus parameters */
 957         if (!_req || !req->req.complete || !req->req.buf
 958                         || !list_empty(&req->queue)) {
 959                 DBG("%s, bad params\n", __FUNCTION__);
 960                 return -EINVAL;
 961         }
 962         if (!_ep || (!ep->desc && ep->bEndpointAddress)) {
 963                 DBG("%s, bad ep\n", __FUNCTION__);
 964                 return -EINVAL;
 965         }
 966         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 967                 if (req->req.length > ep->ep.maxpacket)
 968                         return -EMSGSIZE;
 969                 is_iso = 1;
 970         }
 971
 972         /* this isn't bogus, but OMAP DMA isn't the only hardware to
 973          * have a hard time with partial packet reads...  reject it.
 974          */
 975         if (use_dma
 976                         && ep->has_dma
 977                         && ep->bEndpointAddress != 0
 978                         && (ep->bEndpointAddress & USB_DIR_IN) == 0
 979                         && (req->req.length % ep->ep.maxpacket) != 0) {
 980                 DBG("%s, no partial packet OUT reads\n", __FUNCTION__);
 981                 return -EMSGSIZE;
 982         }
 983
 984         udc = ep->udc;
 985         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
 986                 return -ESHUTDOWN;
 987
 988         if (use_dma && ep->has_dma) {
 989                 if (req->req.dma == DMA_ADDR_INVALID) {
 990                         req->req.dma = dma_map_single(
 991                                 ep->udc->gadget.dev.parent,
 992                                 req->req.buf,
 993                                 req->req.length,
 994                                 (ep->bEndpointAddress & USB_DIR_IN)
 995                                         ? DMA_TO_DEVICE
 996                                         : DMA_FROM_DEVICE);
 997                         req->mapped = 1;
 998                 } else {
 999                         dma_sync_single_for_device(
1000                                 ep->udc->gadget.dev.parent,
1001                                 req->req.dma, req->req.length,
1002                                 (ep->bEndpointAddress & USB_DIR_IN)
1003                                         ? DMA_TO_DEVICE
1004                                         : DMA_FROM_DEVICE);
1005                         req->mapped = 0;
1006                 }
1007         }
1008
1009         VDBG("%s queue req %p, len %d buf %p\n",
1010                 ep->ep.name, _req, _req->length, _req->buf);
1011
1012         spin_lock_irqsave(&udc->lock, flags);
1013
1014         req->req.status = -EINPROGRESS;
1015         req->req.actual = 0;
1016
1017         /* maybe kickstart non-iso i/o queues */
1018         if (is_iso)
1019                 UDC_IRQ_EN_REG |= UDC_SOF_IE;
1020         else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
1021                 int     is_in;
1022
1023                 if (ep->bEndpointAddress == 0) {
1024                         if (!udc->ep0_pending || !list_empty (&ep->queue)) {
1025                                 spin_unlock_irqrestore(&udc->lock, flags);
1026                                 return -EL2HLT;
1027                         }
1028
1029                         /* empty DATA stage? */
1030                         is_in = udc->ep0_in;
1031                         if (!req->req.length) {
1032
1033                                 /* chip became CONFIGURED or ADDRESSED
1034                                  * earlier; drivers may already have queued
1035                                  * requests to non-control endpoints
1036                                  */
1037                                 if (udc->ep0_set_config) {
1038                                         u16     irq_en = UDC_IRQ_EN_REG;
1039
1040                                         irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
1041                                         if (!udc->ep0_reset_config)
1042                                                 irq_en |= UDC_EPN_RX_IE
1043                                                         | UDC_EPN_TX_IE;
1044                                         UDC_IRQ_EN_REG = irq_en;
1045                                 }
1046
1047                                 /* STATUS for zero length DATA stages is
1048                                  * always an IN ... even for IN transfers,
1049                                  * a wierd case which seem to stall OMAP.
1050                                  */
1051                                 UDC_EP_NUM_REG = (UDC_EP_SEL|UDC_EP_DIR);
1052                                 UDC_CTRL_REG = UDC_CLR_EP;
1053                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1054                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1055
1056                                 /* cleanup */
1057                                 udc->ep0_pending = 0;
1058                                 done(ep, req, 0);
1059                                 req = NULL;
1060
1061                         /* non-empty DATA stage */
1062                         } else if (is_in) {
1063                                 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1064                         } else {
1065                                 if (udc->ep0_setup)
1066                                         goto irq_wait;
1067                                 UDC_EP_NUM_REG = UDC_EP_SEL;
1068                         }
1069                 } else {
1070                         is_in = ep->bEndpointAddress & USB_DIR_IN;
1071                         if (!ep->has_dma)
1072                                 use_ep(ep, UDC_EP_SEL);
1073                         /* if ISO: SOF IRQs must be enabled/disabled! */
1074                 }
1075
1076                 if (ep->has_dma)
1077                         (is_in ? next_in_dma : next_out_dma)(ep, req);
1078                 else if (req) {
1079                         if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
1080                                 req = NULL;
1081                         deselect_ep();
1082                         if (!is_in) {
1083                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1084                                 ep->ackwait = 1 + ep->double_buf;
1085                         }
1086                         /* IN: 6 wait states before it'll tx */
1087                 }
1088         }
1089
1090 irq_wait:
1091         /* irq handler advances the queue */
1092         if (req != NULL)
1093                 list_add_tail(&req->queue, &ep->queue);
1094         spin_unlock_irqrestore(&udc->lock, flags);
1095
1096         return 0;
1097 }
1098
1099 static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1100 {
1101         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1102         struct omap_req *req;
1103         unsigned long   flags;
1104
1105         if (!_ep || !_req)
1106                 return -EINVAL;
1107
1108         spin_lock_irqsave(&ep->udc->lock, flags);
1109
1110         /* make sure it's actually queued on this endpoint */
1111         list_for_each_entry (req, &ep->queue, queue) {
1112                 if (&req->req == _req)
1113                         break;
1114         }
1115         if (&req->req != _req) {
1116                 spin_unlock_irqrestore(&ep->udc->lock, flags);
1117                 return -EINVAL;
1118         }
1119
1120         if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1121                 int channel = ep->dma_channel;
1122
1123                 /* releasing the channel cancels the request,
1124                  * reclaiming the channel restarts the queue
1125                  */
1126                 dma_channel_release(ep);
1127                 dma_channel_claim(ep, channel);
1128         } else
1129                 done(ep, req, -ECONNRESET);
1130         spin_unlock_irqrestore(&ep->udc->lock, flags);
1131         return 0;
1132 }
1133
1134 /*-------------------------------------------------------------------------*/
1135
1136 static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1137 {
1138         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1139         unsigned long   flags;
1140         int             status = -EOPNOTSUPP;
1141
1142         spin_lock_irqsave(&ep->udc->lock, flags);
1143
1144         /* just use protocol stalls for ep0; real halts are annoying */
1145         if (ep->bEndpointAddress == 0) {
1146                 if (!ep->udc->ep0_pending)
1147                         status = -EINVAL;
1148                 else if (value) {
1149                         if (ep->udc->ep0_set_config) {
1150                                 WARN("error changing config?\n");
1151                                 UDC_SYSCON2_REG = UDC_CLR_CFG;
1152                         }
1153                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1154                         ep->udc->ep0_pending = 0;
1155                         status = 0;
1156                 } else /* NOP */
1157                         status = 0;
1158
1159         /* otherwise, all active non-ISO endpoints can halt */
1160         } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->desc) {
1161
1162                 /* IN endpoints must already be idle */
1163                 if ((ep->bEndpointAddress & USB_DIR_IN)
1164                                 && !list_empty(&ep->queue)) {
1165                         status = -EAGAIN;
1166                         goto done;
1167                 }
1168
1169                 if (value) {
1170                         int     channel;
1171
1172                         if (use_dma && ep->dma_channel
1173                                         && !list_empty(&ep->queue)) {
1174                                 channel = ep->dma_channel;
1175                                 dma_channel_release(ep);
1176                         } else
1177                                 channel = 0;
1178
1179                         use_ep(ep, UDC_EP_SEL);
1180                         if (UDC_STAT_FLG_REG & UDC_NON_ISO_FIFO_EMPTY) {
1181                                 UDC_CTRL_REG = UDC_SET_HALT;
1182                                 status = 0;
1183                         } else
1184                                 status = -EAGAIN;
1185                         deselect_ep();
1186
1187                         if (channel)
1188                                 dma_channel_claim(ep, channel);
1189                 } else {
1190                         use_ep(ep, 0);
1191                         UDC_CTRL_REG = ep->udc->clr_halt;
1192                         ep->ackwait = 0;
1193                         if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1194                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1195                                 ep->ackwait = 1 + ep->double_buf;
1196                         }
1197                 }
1198         }
1199 done:
1200         VDBG("%s %s halt stat %d\n", ep->ep.name,
1201                 value ? "set" : "clear", status);
1202
1203         spin_unlock_irqrestore(&ep->udc->lock, flags);
1204         return status;
1205 }
1206
1207 static struct usb_ep_ops omap_ep_ops = {
1208         .enable         = omap_ep_enable,
1209         .disable        = omap_ep_disable,
1210
1211         .alloc_request  = omap_alloc_request,
1212         .free_request   = omap_free_request,
1213
1214         .alloc_buffer   = omap_alloc_buffer,
1215         .free_buffer    = omap_free_buffer,
1216
1217         .queue          = omap_ep_queue,
1218         .dequeue        = omap_ep_dequeue,
1219
1220         .set_halt       = omap_ep_set_halt,
1221         // fifo_status ... report bytes in fifo
1222         // fifo_flush ... flush fifo
1223 };
1224
1225 /*-------------------------------------------------------------------------*/
1226
1227 static int omap_get_frame(struct usb_gadget *gadget)
1228 {
1229         u16     sof = UDC_SOF_REG;
1230         return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1231 }
1232
1233 static int omap_wakeup(struct usb_gadget *gadget)
1234 {
1235         struct omap_udc *udc;
1236         unsigned long   flags;
1237         int             retval = -EHOSTUNREACH;
1238
1239         udc = container_of(gadget, struct omap_udc, gadget);
1240
1241         spin_lock_irqsave(&udc->lock, flags);
1242         if (udc->devstat & UDC_SUS) {
1243                 /* NOTE:  OTG spec erratum says that OTG devices may
1244                  * issue wakeups without host enable.
1245                  */
1246                 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1247                         DBG("remote wakeup...\n");
1248                         UDC_SYSCON2_REG = UDC_RMT_WKP;
1249                         retval = 0;
1250                 }
1251
1252         /* NOTE:  non-OTG systems may use SRP TOO... */
1253         } else if (!(udc->devstat & UDC_ATT)) {
1254                 if (udc->transceiver)
1255                         retval = otg_start_srp(udc->transceiver);
1256         }
1257         spin_unlock_irqrestore(&udc->lock, flags);
1258
1259         return retval;
1260 }
1261
1262 static int
1263 omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1264 {
1265         struct omap_udc *udc;
1266         unsigned long   flags;
1267         u16             syscon1;
1268
1269         udc = container_of(gadget, struct omap_udc, gadget);
1270         spin_lock_irqsave(&udc->lock, flags);
1271         syscon1 = UDC_SYSCON1_REG;
1272         if (is_selfpowered)
1273                 syscon1 |= UDC_SELF_PWR;
1274         else
1275                 syscon1 &= ~UDC_SELF_PWR;
1276         UDC_SYSCON1_REG = syscon1;
1277         spin_unlock_irqrestore(&udc->lock, flags);
1278
1279         return 0;
1280 }
1281
1282 static int can_pullup(struct omap_udc *udc)
1283 {
1284         return udc->driver && udc->softconnect && udc->vbus_active;
1285 }
1286
1287 static void pullup_enable(struct omap_udc *udc)
1288 {
1289         udc->gadget.dev.parent->power.power_state = PMSG_ON;
1290         udc->gadget.dev.power.power_state = PMSG_ON;
1291         UDC_SYSCON1_REG |= UDC_PULLUP_EN;
1292 #ifndef CONFIG_USB_OTG
1293         if (!cpu_is_omap15xx())
1294                 OTG_CTRL_REG |= OTG_BSESSVLD;
1295 #endif
1296         UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
1297 }
1298
1299 static void pullup_disable(struct omap_udc *udc)
1300 {
1301 #ifndef CONFIG_USB_OTG
1302         if (!cpu_is_omap15xx())
1303                 OTG_CTRL_REG &= ~OTG_BSESSVLD;
1304 #endif
1305         UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
1306         UDC_SYSCON1_REG &= ~UDC_PULLUP_EN;
1307 }
1308
1309 /*
1310  * Called by whatever detects VBUS sessions:  external transceiver
1311  * driver, or maybe GPIO0 VBUS IRQ.  May request 48 MHz clock.
1312  */
1313 static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1314 {
1315         struct omap_udc *udc;
1316         unsigned long   flags;
1317
1318         udc = container_of(gadget, struct omap_udc, gadget);
1319         spin_lock_irqsave(&udc->lock, flags);
1320         VDBG("VBUS %s\n", is_active ? "on" : "off");
1321         udc->vbus_active = (is_active != 0);
1322         if (cpu_is_omap15xx()) {
1323                 /* "software" detect, ignored if !VBUS_MODE_1510 */
1324                 if (is_active)
1325                         FUNC_MUX_CTRL_0_REG |= VBUS_CTRL_1510;
1326                 else
1327                         FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
1328         }
1329         if (can_pullup(udc))
1330                 pullup_enable(udc);
1331         else
1332                 pullup_disable(udc);
1333         spin_unlock_irqrestore(&udc->lock, flags);
1334         return 0;
1335 }
1336
1337 static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1338 {
1339         struct omap_udc *udc;
1340
1341         udc = container_of(gadget, struct omap_udc, gadget);
1342         if (udc->transceiver)
1343                 return otg_set_power(udc->transceiver, mA);
1344         return -EOPNOTSUPP;
1345 }
1346
1347 static int omap_pullup(struct usb_gadget *gadget, int is_on)
1348 {
1349         struct omap_udc *udc;
1350         unsigned long   flags;
1351
1352         udc = container_of(gadget, struct omap_udc, gadget);
1353         spin_lock_irqsave(&udc->lock, flags);
1354         udc->softconnect = (is_on != 0);
1355         if (can_pullup(udc))
1356                 pullup_enable(udc);
1357         else
1358                 pullup_disable(udc);
1359         spin_unlock_irqrestore(&udc->lock, flags);
1360         return 0;
1361 }
1362
1363 static struct usb_gadget_ops omap_gadget_ops = {
1364         .get_frame              = omap_get_frame,
1365         .wakeup                 = omap_wakeup,
1366         .set_selfpowered        = omap_set_selfpowered,
1367         .vbus_session           = omap_vbus_session,
1368         .vbus_draw              = omap_vbus_draw,
1369         .pullup                 = omap_pullup,
1370 };
1371
1372 /*-------------------------------------------------------------------------*/
1373
1374 /* dequeue ALL requests; caller holds udc->lock */
1375 static void nuke(struct omap_ep *ep, int status)
1376 {
1377         struct omap_req *req;
1378
1379         ep->stopped = 1;
1380
1381         if (use_dma && ep->dma_channel)
1382                 dma_channel_release(ep);
1383
1384         use_ep(ep, 0);
1385         UDC_CTRL_REG = UDC_CLR_EP;
1386         if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
1387                 UDC_CTRL_REG = UDC_SET_HALT;
1388
1389         while (!list_empty(&ep->queue)) {
1390                 req = list_entry(ep->queue.next, struct omap_req, queue);
1391                 done(ep, req, status);
1392         }
1393 }
1394
1395 /* caller holds udc->lock */
1396 static void udc_quiesce(struct omap_udc *udc)
1397 {
1398         struct omap_ep  *ep;
1399
1400         udc->gadget.speed = USB_SPEED_UNKNOWN;
1401         nuke(&udc->ep[0], -ESHUTDOWN);
1402         list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list)
1403                 nuke(ep, -ESHUTDOWN);
1404 }
1405
1406 /*-------------------------------------------------------------------------*/
1407
1408 static void update_otg(struct omap_udc *udc)
1409 {
1410         u16     devstat;
1411
1412         if (!udc->gadget.is_otg)
1413                 return;
1414
1415         if (OTG_CTRL_REG & OTG_ID)
1416                 devstat = UDC_DEVSTAT_REG;
1417         else
1418                 devstat = 0;
1419
1420         udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1421         udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1422         udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1423
1424         /* Enable HNP early, avoiding races on suspend irq path.
1425          * ASSUMES OTG state machine B_BUS_REQ input is true.
1426          */
1427         if (udc->gadget.b_hnp_enable)
1428                 OTG_CTRL_REG = (OTG_CTRL_REG | OTG_B_HNPEN | OTG_B_BUSREQ)
1429                                 & ~OTG_PULLUP;
1430 }
1431
1432 static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1433 {
1434         struct omap_ep  *ep0 = &udc->ep[0];
1435         struct omap_req *req = NULL;
1436
1437         ep0->irqs++;
1438
1439         /* Clear any pending requests and then scrub any rx/tx state
1440          * before starting to handle the SETUP request.
1441          */
1442         if (irq_src & UDC_SETUP) {
1443                 u16     ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1444
1445                 nuke(ep0, 0);
1446                 if (ack) {
1447                         UDC_IRQ_SRC_REG = ack;
1448                         irq_src = UDC_SETUP;
1449                 }
1450         }
1451
1452         /* IN/OUT packets mean we're in the DATA or STATUS stage.
1453          * This driver uses only uses protocol stalls (ep0 never halts),
1454          * and if we got this far the gadget driver already had a
1455          * chance to stall.  Tries to be forgiving of host oddities.
1456          *
1457          * NOTE:  the last chance gadget drivers have to stall control
1458          * requests is during their request completion callback.
1459          */
1460         if (!list_empty(&ep0->queue))
1461                 req = container_of(ep0->queue.next, struct omap_req, queue);
1462
1463         /* IN == TX to host */
1464         if (irq_src & UDC_EP0_TX) {
1465                 int     stat;
1466
1467                 UDC_IRQ_SRC_REG = UDC_EP0_TX;
1468                 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1469                 stat = UDC_STAT_FLG_REG;
1470                 if (stat & UDC_ACK) {
1471                         if (udc->ep0_in) {
1472                                 /* write next IN packet from response,
1473                                  * or set up the status stage.
1474                                  */
1475                                 if (req)
1476                                         stat = write_fifo(ep0, req);
1477                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1478                                 if (!req && udc->ep0_pending) {
1479                                         UDC_EP_NUM_REG = UDC_EP_SEL;
1480                                         UDC_CTRL_REG = UDC_CLR_EP;
1481                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1482                                         UDC_EP_NUM_REG = 0;
1483                                         udc->ep0_pending = 0;
1484                                 } /* else:  6 wait states before it'll tx */
1485                         } else {
1486                                 /* ack status stage of OUT transfer */
1487                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1488                                 if (req)
1489                                         done(ep0, req, 0);
1490                         }
1491                         req = NULL;
1492                 } else if (stat & UDC_STALL) {
1493                         UDC_CTRL_REG = UDC_CLR_HALT;
1494                         UDC_EP_NUM_REG = UDC_EP_DIR;
1495                 } else {
1496                         UDC_EP_NUM_REG = UDC_EP_DIR;
1497                 }
1498         }
1499
1500         /* OUT == RX from host */
1501         if (irq_src & UDC_EP0_RX) {
1502                 int     stat;
1503
1504                 UDC_IRQ_SRC_REG = UDC_EP0_RX;
1505                 UDC_EP_NUM_REG = UDC_EP_SEL;
1506                 stat = UDC_STAT_FLG_REG;
1507                 if (stat & UDC_ACK) {
1508                         if (!udc->ep0_in) {
1509                                 stat = 0;
1510                                 /* read next OUT packet of request, maybe
1511                                  * reactiviting the fifo; stall on errors.
1512                                  */
1513                                 if (!req || (stat = read_fifo(ep0, req)) < 0) {
1514                                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1515                                         udc->ep0_pending = 0;
1516                                         stat = 0;
1517                                 } else if (stat == 0)
1518                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1519                                 UDC_EP_NUM_REG = 0;
1520
1521                                 /* activate status stage */
1522                                 if (stat == 1) {
1523                                         done(ep0, req, 0);
1524                                         /* that may have STALLed ep0... */
1525                                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1526                                         UDC_CTRL_REG = UDC_CLR_EP;
1527                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1528                                         UDC_EP_NUM_REG = UDC_EP_DIR;
1529                                         udc->ep0_pending = 0;
1530                                 }
1531                         } else {
1532                                 /* ack status stage of IN transfer */
1533                                 UDC_EP_NUM_REG = 0;
1534                                 if (req)
1535                                         done(ep0, req, 0);
1536                         }
1537                 } else if (stat & UDC_STALL) {
1538                         UDC_CTRL_REG = UDC_CLR_HALT;
1539                         UDC_EP_NUM_REG = 0;
1540                 } else {
1541                         UDC_EP_NUM_REG = 0;
1542                 }
1543         }
1544
1545         /* SETUP starts all control transfers */
1546         if (irq_src & UDC_SETUP) {
1547                 union u {
1548                         u16                     word[4];
1549                         struct usb_ctrlrequest  r;
1550                 } u;
1551                 int                     status = -EINVAL;
1552                 struct omap_ep          *ep;
1553
1554                 /* read the (latest) SETUP message */
1555                 do {
1556                         UDC_EP_NUM_REG = UDC_SETUP_SEL;
1557                         /* two bytes at a time */
1558                         u.word[0] = UDC_DATA_REG;
1559                         u.word[1] = UDC_DATA_REG;
1560                         u.word[2] = UDC_DATA_REG;
1561                         u.word[3] = UDC_DATA_REG;
1562                         UDC_EP_NUM_REG = 0;
1563                 } while (UDC_IRQ_SRC_REG & UDC_SETUP);
1564
1565 #define w_value         le16_to_cpup (&u.r.wValue)
1566 #define w_index         le16_to_cpup (&u.r.wIndex)
1567 #define w_length        le16_to_cpup (&u.r.wLength)
1568
1569                 /* Delegate almost all control requests to the gadget driver,
1570                  * except for a handful of ch9 status/feature requests that
1571                  * hardware doesn't autodecode _and_ the gadget API hides.
1572                  */
1573                 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1574                 udc->ep0_set_config = 0;
1575                 udc->ep0_pending = 1;
1576                 ep0->stopped = 0;
1577                 ep0->ackwait = 0;
1578                 switch (u.r.bRequest) {
1579                 case USB_REQ_SET_CONFIGURATION:
1580                         /* udc needs to know when ep != 0 is valid */
1581                         if (u.r.bRequestType != USB_RECIP_DEVICE)
1582                                 goto delegate;
1583                         if (w_length != 0)
1584                                 goto do_stall;
1585                         udc->ep0_set_config = 1;
1586                         udc->ep0_reset_config = (w_value == 0);
1587                         VDBG("set config %d\n", w_value);
1588
1589                         /* update udc NOW since gadget driver may start
1590                          * queueing requests immediately; clear config
1591                          * later if it fails the request.
1592                          */
1593                         if (udc->ep0_reset_config)
1594                                 UDC_SYSCON2_REG = UDC_CLR_CFG;
1595                         else
1596                                 UDC_SYSCON2_REG = UDC_DEV_CFG;
1597                         update_otg(udc);
1598                         goto delegate;
1599                 case USB_REQ_CLEAR_FEATURE:
1600                         /* clear endpoint halt */
1601                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1602                                 goto delegate;
1603                         if (w_value != USB_ENDPOINT_HALT
1604                                         || w_length != 0)
1605                                 goto do_stall;
1606                         ep = &udc->ep[w_index & 0xf];
1607                         if (ep != ep0) {
1608                                 if (w_index & USB_DIR_IN)
1609                                         ep += 16;
1610                                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1611                                                 || !ep->desc)
1612                                         goto do_stall;
1613                                 use_ep(ep, 0);
1614                                 UDC_CTRL_REG = udc->clr_halt;
1615                                 ep->ackwait = 0;
1616                                 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1617                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1618                                         ep->ackwait = 1 + ep->double_buf;
1619                                 }
1620                                 /* NOTE:  assumes the host behaves sanely,
1621                                  * only clearing real halts.  Else we may
1622                                  * need to kill pending transfers and then
1623                                  * restart the queue... very messy for DMA!
1624                                  */
1625                         }
1626                         VDBG("%s halt cleared by host\n", ep->name);
1627                         goto ep0out_status_stage;
1628                 case USB_REQ_SET_FEATURE:
1629                         /* set endpoint halt */
1630                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1631                                 goto delegate;
1632                         if (w_value != USB_ENDPOINT_HALT
1633                                         || w_length != 0)
1634                                 goto do_stall;
1635                         ep = &udc->ep[w_index & 0xf];
1636                         if (w_index & USB_DIR_IN)
1637                                 ep += 16;
1638                         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1639                                         || ep == ep0 || !ep->desc)
1640                                 goto do_stall;
1641                         if (use_dma && ep->has_dma) {
1642                                 /* this has rude side-effects (aborts) and
1643                                  * can't really work if DMA-IN is active
1644                                  */
1645                                 DBG("%s host set_halt, NYET \n", ep->name);
1646                                 goto do_stall;
1647                         }
1648                         use_ep(ep, 0);
1649                         /* can't halt if fifo isn't empty... */
1650                         UDC_CTRL_REG = UDC_CLR_EP;
1651                         UDC_CTRL_REG = UDC_SET_HALT;
1652                         VDBG("%s halted by host\n", ep->name);
1653 ep0out_status_stage:
1654                         status = 0;
1655                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1656                         UDC_CTRL_REG = UDC_CLR_EP;
1657                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1658                         UDC_EP_NUM_REG = UDC_EP_DIR;
1659                         udc->ep0_pending = 0;
1660                         break;
1661                 case USB_REQ_GET_STATUS:
1662                         /* return interface status.  if we were pedantic,
1663                          * we'd detect non-existent interfaces, and stall.
1664                          */
1665                         if (u.r.bRequestType
1666                                         != (USB_DIR_IN|USB_RECIP_INTERFACE))
1667                                 goto delegate;
1668                         /* return two zero bytes */
1669                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1670                         UDC_DATA_REG = 0;
1671                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1672                         UDC_EP_NUM_REG = UDC_EP_DIR;
1673                         status = 0;
1674                         VDBG("GET_STATUS, interface %d\n", w_index);
1675                         /* next, status stage */
1676                         break;
1677                 default:
1678 delegate:
1679                         /* activate the ep0out fifo right away */
1680                         if (!udc->ep0_in && w_length) {
1681                                 UDC_EP_NUM_REG = 0;
1682                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1683                         }
1684
1685                         /* gadget drivers see class/vendor specific requests,
1686                          * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1687                          * and more
1688                          */
1689                         VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1690                                 u.r.bRequestType, u.r.bRequest,
1691                                 w_value, w_index, w_length);
1692
1693 #undef  w_value
1694 #undef  w_index
1695 #undef  w_length
1696
1697                         /* The gadget driver may return an error here,
1698                          * causing an immediate protocol stall.
1699                          *
1700                          * Else it must issue a response, either queueing a
1701                          * response buffer for the DATA stage, or halting ep0
1702                          * (causing a protocol stall, not a real halt).  A
1703                          * zero length buffer means no DATA stage.
1704                          *
1705                          * It's fine to issue that response after the setup()
1706                          * call returns, and this IRQ was handled.
1707                          */
1708                         udc->ep0_setup = 1;
1709                         spin_unlock(&udc->lock);
1710                         status = udc->driver->setup (&udc->gadget, &u.r);
1711                         spin_lock(&udc->lock);
1712                         udc->ep0_setup = 0;
1713                 }
1714
1715                 if (status < 0) {
1716 do_stall:
1717                         VDBG("req %02x.%02x protocol STALL; stat %d\n",
1718                                         u.r.bRequestType, u.r.bRequest, status);
1719                         if (udc->ep0_set_config) {
1720                                 if (udc->ep0_reset_config)
1721                                         WARN("error resetting config?\n");
1722                                 else
1723                                         UDC_SYSCON2_REG = UDC_CLR_CFG;
1724                         }
1725                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1726                         udc->ep0_pending = 0;
1727                 }
1728         }
1729 }
1730
1731 /*-------------------------------------------------------------------------*/
1732
1733 #define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1734
1735 static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1736 {
1737         u16     devstat, change;
1738
1739         devstat = UDC_DEVSTAT_REG;
1740         change = devstat ^ udc->devstat;
1741         udc->devstat = devstat;
1742
1743         if (change & (UDC_USB_RESET|UDC_ATT)) {
1744                 udc_quiesce(udc);
1745
1746                 if (change & UDC_ATT) {
1747                         /* driver for any external transceiver will
1748                          * have called omap_vbus_session() already
1749                          */
1750                         if (devstat & UDC_ATT) {
1751                                 udc->gadget.speed = USB_SPEED_FULL;
1752                                 VDBG("connect\n");
1753                                 if (!udc->transceiver)
1754                                         pullup_enable(udc);
1755                                 // if (driver->connect) call it
1756                         } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1757                                 udc->gadget.speed = USB_SPEED_UNKNOWN;
1758                                 if (!udc->transceiver)
1759                                         pullup_disable(udc);
1760                                 DBG("disconnect, gadget %s\n",
1761                                         udc->driver->driver.name);
1762                                 if (udc->driver->disconnect) {
1763                                         spin_unlock(&udc->lock);
1764                                         udc->driver->disconnect(&udc->gadget);
1765                                         spin_lock(&udc->lock);
1766                                 }
1767                         }
1768                         change &= ~UDC_ATT;
1769                 }
1770
1771                 if (change & UDC_USB_RESET) {
1772                         if (devstat & UDC_USB_RESET) {
1773                                 VDBG("RESET=1\n");
1774                         } else {
1775                                 udc->gadget.speed = USB_SPEED_FULL;
1776                                 INFO("USB reset done, gadget %s\n",
1777                                         udc->driver->driver.name);
1778                                 /* ep0 traffic is legal from now on */
1779                                 UDC_IRQ_EN_REG = UDC_DS_CHG_IE | UDC_EP0_IE;
1780                         }
1781                         change &= ~UDC_USB_RESET;
1782                 }
1783         }
1784         if (change & UDC_SUS) {
1785                 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1786                         // FIXME tell isp1301 to suspend/resume (?)
1787                         if (devstat & UDC_SUS) {
1788                                 VDBG("suspend\n");
1789                                 update_otg(udc);
1790                                 /* HNP could be under way already */
1791                                 if (udc->gadget.speed == USB_SPEED_FULL
1792                                                 && udc->driver->suspend) {
1793                                         spin_unlock(&udc->lock);
1794                                         udc->driver->suspend(&udc->gadget);
1795                                         spin_lock(&udc->lock);
1796                                 }
1797                                 if (udc->transceiver)
1798                                         otg_set_suspend(udc->transceiver, 1);
1799                         } else {
1800                                 VDBG("resume\n");
1801                                 if (udc->transceiver)
1802                                         otg_set_suspend(udc->transceiver, 0);
1803                                 if (udc->gadget.speed == USB_SPEED_FULL
1804                                                 && udc->driver->resume) {
1805                                         spin_unlock(&udc->lock);
1806                                         udc->driver->resume(&udc->gadget);
1807                                         spin_lock(&udc->lock);
1808                                 }
1809                         }
1810                 }
1811                 change &= ~UDC_SUS;
1812         }
1813         if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1814                 update_otg(udc);
1815                 change &= ~OTG_FLAGS;
1816         }
1817
1818         change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1819         if (change)
1820                 VDBG("devstat %03x, ignore change %03x\n",
1821                         devstat,  change);
1822
1823         UDC_IRQ_SRC_REG = UDC_DS_CHG;
1824 }
1825
1826 static irqreturn_t
1827 omap_udc_irq(int irq, void *_udc, struct pt_regs *r)
1828 {
1829         struct omap_udc *udc = _udc;
1830         u16             irq_src;
1831         irqreturn_t     status = IRQ_NONE;
1832         unsigned long   flags;
1833
1834         spin_lock_irqsave(&udc->lock, flags);
1835         irq_src = UDC_IRQ_SRC_REG;
1836
1837         /* Device state change (usb ch9 stuff) */
1838         if (irq_src & UDC_DS_CHG) {
1839                 devstate_irq(_udc, irq_src);
1840                 status = IRQ_HANDLED;
1841                 irq_src &= ~UDC_DS_CHG;
1842         }
1843
1844         /* EP0 control transfers */
1845         if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1846                 ep0_irq(_udc, irq_src);
1847                 status = IRQ_HANDLED;
1848                 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1849         }
1850
1851         /* DMA transfer completion */
1852         if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1853                 dma_irq(_udc, irq_src);
1854                 status = IRQ_HANDLED;
1855                 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1856         }
1857
1858         irq_src &= ~(UDC_SOF|UDC_EPN_TX|UDC_EPN_RX);
1859         if (irq_src)
1860                 DBG("udc_irq, unhandled %03x\n", irq_src);
1861         spin_unlock_irqrestore(&udc->lock, flags);
1862
1863         return status;
1864 }
1865
1866 /* workaround for seemingly-lost IRQs for RX ACKs... */
1867 #define PIO_OUT_TIMEOUT (jiffies + HZ/3)
1868 #define HALF_FULL(f)    (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1869
1870 static void pio_out_timer(unsigned long _ep)
1871 {
1872         struct omap_ep  *ep = (void *) _ep;
1873         unsigned long   flags;
1874         u16             stat_flg;
1875
1876         spin_lock_irqsave(&ep->udc->lock, flags);
1877         if (!list_empty(&ep->queue) && ep->ackwait) {
1878                 use_ep(ep, 0);
1879                 stat_flg = UDC_STAT_FLG_REG;
1880
1881                 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1882                                 || (ep->double_buf && HALF_FULL(stat_flg)))) {
1883                         struct omap_req *req;
1884
1885                         VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
1886                         req = container_of(ep->queue.next,
1887                                         struct omap_req, queue);
1888                         UDC_EP_NUM_REG = ep->bEndpointAddress | UDC_EP_SEL;
1889                         (void) read_fifo(ep, req);
1890                         UDC_EP_NUM_REG = ep->bEndpointAddress;
1891                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1892                         ep->ackwait = 1 + ep->double_buf;
1893                 }
1894         }
1895         mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1896         spin_unlock_irqrestore(&ep->udc->lock, flags);
1897 }
1898
1899 static irqreturn_t
1900 omap_udc_pio_irq(int irq, void *_dev, struct pt_regs *r)
1901 {
1902         u16             epn_stat, irq_src;
1903         irqreturn_t     status = IRQ_NONE;
1904         struct omap_ep  *ep;
1905         int             epnum;
1906         struct omap_udc *udc = _dev;
1907         struct omap_req *req;
1908         unsigned long   flags;
1909
1910         spin_lock_irqsave(&udc->lock, flags);
1911         epn_stat = UDC_EPN_STAT_REG;
1912         irq_src = UDC_IRQ_SRC_REG;
1913
1914         /* handle OUT first, to avoid some wasteful NAKs */
1915         if (irq_src & UDC_EPN_RX) {
1916                 epnum = (epn_stat >> 8) & 0x0f;
1917                 UDC_IRQ_SRC_REG = UDC_EPN_RX;
1918                 status = IRQ_HANDLED;
1919                 ep = &udc->ep[epnum];
1920                 ep->irqs++;
1921
1922                 UDC_EP_NUM_REG = epnum | UDC_EP_SEL;
1923                 ep->fnf = 0;
1924                 if ((UDC_STAT_FLG_REG & UDC_ACK)) {
1925                         ep->ackwait--;
1926                         if (!list_empty(&ep->queue)) {
1927                                 int stat;
1928                                 req = container_of(ep->queue.next,
1929                                                 struct omap_req, queue);
1930                                 stat = read_fifo(ep, req);
1931                                 if (!ep->double_buf)
1932                                         ep->fnf = 1;
1933                         }
1934                 }
1935                 /* min 6 clock delay before clearing EP_SEL ... */
1936                 epn_stat = UDC_EPN_STAT_REG;
1937                 epn_stat = UDC_EPN_STAT_REG;
1938                 UDC_EP_NUM_REG = epnum;
1939
1940                 /* enabling fifo _after_ clearing ACK, contrary to docs,
1941                  * reduces lossage; timer still needed though (sigh).
1942                  */
1943                 if (ep->fnf) {
1944                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1945                         ep->ackwait = 1 + ep->double_buf;
1946                 }
1947                 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1948         }
1949
1950         /* then IN transfers */
1951         else if (irq_src & UDC_EPN_TX) {
1952                 epnum = epn_stat & 0x0f;
1953                 UDC_IRQ_SRC_REG = UDC_EPN_TX;
1954                 status = IRQ_HANDLED;
1955                 ep = &udc->ep[16 + epnum];
1956                 ep->irqs++;
1957
1958                 UDC_EP_NUM_REG = epnum | UDC_EP_DIR | UDC_EP_SEL;
1959                 if ((UDC_STAT_FLG_REG & UDC_ACK)) {
1960                         ep->ackwait = 0;
1961                         if (!list_empty(&ep->queue)) {
1962                                 req = container_of(ep->queue.next,
1963                                                 struct omap_req, queue);
1964                                 (void) write_fifo(ep, req);
1965                         }
1966                 }
1967                 /* min 6 clock delay before clearing EP_SEL ... */
1968                 epn_stat = UDC_EPN_STAT_REG;
1969                 epn_stat = UDC_EPN_STAT_REG;
1970                 UDC_EP_NUM_REG = epnum | UDC_EP_DIR;
1971                 /* then 6 clocks before it'd tx */
1972         }
1973
1974         spin_unlock_irqrestore(&udc->lock, flags);
1975         return status;
1976 }
1977
1978 #ifdef  USE_ISO
1979 static irqreturn_t
1980 omap_udc_iso_irq(int irq, void *_dev, struct pt_regs *r)
1981 {
1982         struct omap_udc *udc = _dev;
1983         struct omap_ep  *ep;
1984         int             pending = 0;
1985         unsigned long   flags;
1986
1987         spin_lock_irqsave(&udc->lock, flags);
1988
1989         /* handle all non-DMA ISO transfers */
1990         list_for_each_entry (ep, &udc->iso, iso) {
1991                 u16             stat;
1992                 struct omap_req *req;
1993
1994                 if (ep->has_dma || list_empty(&ep->queue))
1995                         continue;
1996                 req = list_entry(ep->queue.next, struct omap_req, queue);
1997
1998                 use_ep(ep, UDC_EP_SEL);
1999                 stat = UDC_STAT_FLG_REG;
2000
2001                 /* NOTE: like the other controller drivers, this isn't
2002                  * currently reporting lost or damaged frames.
2003                  */
2004                 if (ep->bEndpointAddress & USB_DIR_IN) {
2005                         if (stat & UDC_MISS_IN)
2006                                 /* done(ep, req, -EPROTO) */;
2007                         else
2008                                 write_fifo(ep, req);
2009                 } else {
2010                         int     status = 0;
2011
2012                         if (stat & UDC_NO_RXPACKET)
2013                                 status = -EREMOTEIO;
2014                         else if (stat & UDC_ISO_ERR)
2015                                 status = -EILSEQ;
2016                         else if (stat & UDC_DATA_FLUSH)
2017                                 status = -ENOSR;
2018
2019                         if (status)
2020                                 /* done(ep, req, status) */;
2021                         else
2022                                 read_fifo(ep, req);
2023                 }
2024                 deselect_ep();
2025                 /* 6 wait states before next EP */
2026
2027                 ep->irqs++;
2028                 if (!list_empty(&ep->queue))
2029                         pending = 1;
2030         }
2031         if (!pending)
2032                 UDC_IRQ_EN_REG &= ~UDC_SOF_IE;
2033         UDC_IRQ_SRC_REG = UDC_SOF;
2034
2035         spin_unlock_irqrestore(&udc->lock, flags);
2036         return IRQ_HANDLED;
2037 }
2038 #endif
2039
2040 /*-------------------------------------------------------------------------*/
2041
2042 static struct omap_udc *udc;
2043
2044 int usb_gadget_register_driver (struct usb_gadget_driver *driver)
2045 {
2046         int             status = -ENODEV;
2047         struct omap_ep  *ep;
2048         unsigned long   flags;
2049
2050         /* basic sanity tests */
2051         if (!udc)
2052                 return -ENODEV;
2053         if (!driver
2054                         // FIXME if otg, check:  driver->is_otg
2055                         || driver->speed < USB_SPEED_FULL
2056                         || !driver->bind
2057                         || !driver->unbind
2058                         || !driver->setup)
2059                 return -EINVAL;
2060
2061         spin_lock_irqsave(&udc->lock, flags);
2062         if (udc->driver) {
2063                 spin_unlock_irqrestore(&udc->lock, flags);
2064                 return -EBUSY;
2065         }
2066
2067         /* reset state */
2068         list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
2069                 ep->irqs = 0;
2070                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2071                         continue;
2072                 use_ep(ep, 0);
2073                 UDC_CTRL_REG = UDC_SET_HALT;
2074         }
2075         udc->ep0_pending = 0;
2076         udc->ep[0].irqs = 0;
2077         udc->softconnect = 1;
2078
2079         /* hook up the driver */
2080         driver->driver.bus = NULL;
2081         udc->driver = driver;
2082         udc->gadget.dev.driver = &driver->driver;
2083         spin_unlock_irqrestore(&udc->lock, flags);
2084
2085         status = driver->bind (&udc->gadget);
2086         if (status) {
2087                 DBG("bind to %s --> %d\n", driver->driver.name, status);
2088                 udc->gadget.dev.driver = NULL;
2089                 udc->driver = NULL;
2090                 goto done;
2091         }
2092         DBG("bound to driver %s\n", driver->driver.name);
2093
2094         UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
2095
2096         /* connect to bus through transceiver */
2097         if (udc->transceiver) {
2098                 status = otg_set_peripheral(udc->transceiver, &udc->gadget);
2099                 if (status < 0) {
2100                         ERR("can't bind to transceiver\n");
2101                         driver->unbind (&udc->gadget);
2102                         udc->gadget.dev.driver = NULL;
2103                         udc->driver = NULL;
2104                         goto done;
2105                 }
2106         } else {
2107                 if (can_pullup(udc))
2108                         pullup_enable (udc);
2109                 else
2110                         pullup_disable (udc);
2111         }
2112
2113         /* boards that don't have VBUS sensing can't autogate 48MHz;
2114          * can't enter deep sleep while a gadget driver is active.
2115          */
2116         if (machine_is_omap_innovator() || machine_is_omap_osk())
2117                 omap_vbus_session(&udc->gadget, 1);
2118
2119 done:
2120         return status;
2121 }
2122 EXPORT_SYMBOL(usb_gadget_register_driver);
2123
2124 int usb_gadget_unregister_driver (struct usb_gadget_driver *driver)
2125 {
2126         unsigned long   flags;
2127         int             status = -ENODEV;
2128
2129         if (!udc)
2130                 return -ENODEV;
2131         if (!driver || driver != udc->driver)
2132                 return -EINVAL;
2133
2134         if (machine_is_omap_innovator() || machine_is_omap_osk())
2135                 omap_vbus_session(&udc->gadget, 0);
2136
2137         if (udc->transceiver)
2138                 (void) otg_set_peripheral(udc->transceiver, NULL);
2139         else
2140                 pullup_disable(udc);
2141
2142         spin_lock_irqsave(&udc->lock, flags);
2143         udc_quiesce(udc);
2144         spin_unlock_irqrestore(&udc->lock, flags);
2145
2146         driver->unbind(&udc->gadget);
2147         udc->gadget.dev.driver = NULL;
2148         udc->driver = NULL;
2149
2150         DBG("unregistered driver '%s'\n", driver->driver.name);
2151         return status;
2152 }
2153 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2154
2155
2156 /*-------------------------------------------------------------------------*/
2157
2158 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2159
2160 #include <linux/seq_file.h>
2161
2162 static const char proc_filename[] = "driver/udc";
2163
2164 #define FOURBITS "%s%s%s%s"
2165 #define EIGHTBITS FOURBITS FOURBITS
2166
2167 static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2168 {
2169         u16             stat_flg;
2170         struct omap_req *req;
2171         char            buf[20];
2172
2173         use_ep(ep, 0);
2174
2175         if (use_dma && ep->has_dma)
2176                 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2177                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2178                         ep->dma_channel - 1, ep->lch);
2179         else
2180                 buf[0] = 0;
2181
2182         stat_flg = UDC_STAT_FLG_REG;
2183         seq_printf(s,
2184                 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2185                 ep->name, buf,
2186                 ep->double_buf ? "dbuf " : "",
2187                 ({char *s; switch(ep->ackwait){
2188                 case 0: s = ""; break;
2189                 case 1: s = "(ackw) "; break;
2190                 case 2: s = "(ackw2) "; break;
2191                 default: s = "(?) "; break;
2192                 } s;}),
2193                 ep->irqs, stat_flg,
2194                 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2195                 (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2196                 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2197                 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2198                 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2199                 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2200                 (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2201                 (stat_flg & UDC_STALL) ? "STALL " : "",
2202                 (stat_flg & UDC_NAK) ? "NAK " : "",
2203                 (stat_flg & UDC_ACK) ? "ACK " : "",
2204                 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2205                 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2206                 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2207
2208         if (list_empty (&ep->queue))
2209                 seq_printf(s, "\t(queue empty)\n");
2210         else
2211                 list_for_each_entry (req, &ep->queue, queue) {
2212                         unsigned        length = req->req.actual;
2213
2214                         if (use_dma && buf[0]) {
2215                                 length += ((ep->bEndpointAddress & USB_DIR_IN)
2216                                                 ? dma_src_len : dma_dest_len)
2217                                         (ep, req->req.dma + length);
2218                                 buf[0] = 0;
2219                         }
2220                         seq_printf(s, "\treq %p len %d/%d buf %p\n",
2221                                         &req->req, length,
2222                                         req->req.length, req->req.buf);
2223                 }
2224 }
2225
2226 static char *trx_mode(unsigned m, int enabled)
2227 {
2228         switch (m) {
2229         case 0:         return enabled ? "*6wire" : "unused";
2230         case 1:         return "4wire";
2231         case 2:         return "3wire";
2232         case 3:         return "6wire";
2233         default:        return "unknown";
2234         }
2235 }
2236
2237 static int proc_otg_show(struct seq_file *s)
2238 {
2239         u32             tmp;
2240         u32             trans;
2241
2242         tmp = OTG_REV_REG;
2243         trans = USB_TRANSCEIVER_CTRL_REG;
2244         seq_printf(s, "\nOTG rev %d.%d, transceiver_ctrl %05x\n",
2245                 tmp >> 4, tmp & 0xf, trans);
2246         tmp = OTG_SYSCON_1_REG;
2247         seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2248                         FOURBITS "\n", tmp,
2249                 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2250                 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
2251                 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
2252                         ? "internal"
2253                         : trx_mode(USB0_TRX_MODE(tmp), 1),
2254                 (tmp & OTG_IDLE_EN) ? " !otg" : "",
2255                 (tmp & HST_IDLE_EN) ? " !host" : "",
2256                 (tmp & DEV_IDLE_EN) ? " !dev" : "",
2257                 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
2258         tmp = OTG_SYSCON_2_REG;
2259         seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2260                         " b_ase_brst=%d hmc=%d\n", tmp,
2261                 (tmp & OTG_EN) ? " otg_en" : "",
2262                 (tmp & USBX_SYNCHRO) ? " synchro" : "",
2263                 // much more SRP stuff
2264                 (tmp & SRP_DATA) ? " srp_data" : "",
2265                 (tmp & SRP_VBUS) ? " srp_vbus" : "",
2266                 (tmp & OTG_PADEN) ? " otg_paden" : "",
2267                 (tmp & HMC_PADEN) ? " hmc_paden" : "",
2268                 (tmp & UHOST_EN) ? " uhost_en" : "",
2269                 (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2270                 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
2271                 B_ASE_BRST(tmp),
2272                 OTG_HMC(tmp));
2273         tmp = OTG_CTRL_REG;
2274         seq_printf(s, "otg_ctrl    %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2275                 (tmp & OTG_ASESSVLD) ? " asess" : "",
2276                 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
2277                 (tmp & OTG_BSESSVLD) ? " bsess" : "",
2278                 (tmp & OTG_VBUSVLD) ? " vbus" : "",
2279                 (tmp & OTG_ID) ? " id" : "",
2280                 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2281                 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2282                 (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2283                 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2284                 (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2285                 (tmp & OTG_BUSDROP) ? " busdrop" : "",
2286                 (tmp & OTG_PULLDOWN) ? " down" : "",
2287                 (tmp & OTG_PULLUP) ? " up" : "",
2288                 (tmp & OTG_DRV_VBUS) ? " drv" : "",
2289                 (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2290                 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2291                 (tmp & OTG_PU_ID) ? " pu_id" : ""
2292                 );
2293         tmp = OTG_IRQ_EN_REG;
2294         seq_printf(s, "otg_irq_en  %04x" "\n", tmp);
2295         tmp = OTG_IRQ_SRC_REG;
2296         seq_printf(s, "otg_irq_src %04x" "\n", tmp);
2297         tmp = OTG_OUTCTRL_REG;
2298         seq_printf(s, "otg_outctrl %04x" "\n", tmp);
2299         tmp = OTG_TEST_REG;
2300         seq_printf(s, "otg_test    %04x" "\n", tmp);
2301         return 0;
2302 }
2303
2304 static int proc_udc_show(struct seq_file *s, void *_)
2305 {
2306         u32             tmp;
2307         struct omap_ep  *ep;
2308         unsigned long   flags;
2309
2310         spin_lock_irqsave(&udc->lock, flags);
2311
2312         seq_printf(s, "%s, version: " DRIVER_VERSION
2313 #ifdef  USE_ISO
2314                 " (iso)"
2315 #endif
2316                 "%s\n",
2317                 driver_desc,
2318                 use_dma ?  " (dma)" : "");
2319
2320         tmp = UDC_REV_REG & 0xff;
2321         seq_printf(s,
2322                 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2323                 "hmc %d, transceiver %s\n",
2324                 tmp >> 4, tmp & 0xf,
2325                 fifo_mode,
2326                 udc->driver ? udc->driver->driver.name : "(none)",
2327                 HMC,
2328                 udc->transceiver ? udc->transceiver->label : "(none)");
2329         seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2330                 __REG16(ULPD_CLOCK_CTRL),
2331                 __REG16(ULPD_SOFT_REQ),
2332                 __REG16(ULPD_STATUS_REQ));
2333
2334         /* OTG controller registers */
2335         if (!cpu_is_omap15xx())
2336                 proc_otg_show(s);
2337
2338         tmp = UDC_SYSCON1_REG;
2339         seq_printf(s, "\nsyscon1     %04x" EIGHTBITS "\n", tmp,
2340                 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2341                 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2342                 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2343                 (tmp & UDC_NAK_EN) ? " nak" : "",
2344                 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2345                 (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2346                 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2347                 (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
2348         // syscon2 is write-only
2349
2350         /* UDC controller registers */
2351         if (!(tmp & UDC_PULLUP_EN)) {
2352                 seq_printf(s, "(suspended)\n");
2353                 spin_unlock_irqrestore(&udc->lock, flags);
2354                 return 0;
2355         }
2356
2357         tmp = UDC_DEVSTAT_REG;
2358         seq_printf(s, "devstat     %04x" EIGHTBITS "%s%s\n", tmp,
2359                 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2360                 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2361                 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2362                 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2363                 (tmp & UDC_USB_RESET) ? " usb_reset" : "",
2364                 (tmp & UDC_SUS) ? " SUS" : "",
2365                 (tmp & UDC_CFG) ? " CFG" : "",
2366                 (tmp & UDC_ADD) ? " ADD" : "",
2367                 (tmp & UDC_DEF) ? " DEF" : "",
2368                 (tmp & UDC_ATT) ? " ATT" : "");
2369         seq_printf(s, "sof         %04x\n", UDC_SOF_REG);
2370         tmp = UDC_IRQ_EN_REG;
2371         seq_printf(s, "irq_en      %04x" FOURBITS "%s\n", tmp,
2372                 (tmp & UDC_SOF_IE) ? " sof" : "",
2373                 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2374                 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2375                 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2376                 (tmp & UDC_EP0_IE) ? " ep0" : "");
2377         tmp = UDC_IRQ_SRC_REG;
2378         seq_printf(s, "irq_src     %04x" EIGHTBITS "%s%s\n", tmp,
2379                 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
2380                 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2381                 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
2382                 (tmp & UDC_SOF) ? " sof" : "",
2383                 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
2384                 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
2385                 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
2386                 (tmp & UDC_SETUP) ? " setup" : "",
2387                 (tmp & UDC_EP0_RX) ? " ep0out" : "",
2388                 (tmp & UDC_EP0_TX) ? " ep0in" : "");
2389         if (use_dma) {
2390                 unsigned i;
2391
2392                 tmp = UDC_DMA_IRQ_EN_REG;
2393                 seq_printf(s, "dma_irq_en  %04x%s" EIGHTBITS "\n", tmp,
2394                         (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2395                         (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2396                         (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2397
2398                         (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2399                         (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2400                         (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2401
2402                         (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2403                         (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2404                         (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2405
2406                 tmp = UDC_RXDMA_CFG_REG;
2407                 seq_printf(s, "rxdma_cfg   %04x\n", tmp);
2408                 if (tmp) {
2409                         for (i = 0; i < 3; i++) {
2410                                 if ((tmp & (0x0f << (i * 4))) == 0)
2411                                         continue;
2412                                 seq_printf(s, "rxdma[%d]    %04x\n", i,
2413                                                 UDC_RXDMA_REG(i + 1));
2414                         }
2415                 }
2416                 tmp = UDC_TXDMA_CFG_REG;
2417                 seq_printf(s, "txdma_cfg   %04x\n", tmp);
2418                 if (tmp) {
2419                         for (i = 0; i < 3; i++) {
2420                                 if (!(tmp & (0x0f << (i * 4))))
2421                                         continue;
2422                                 seq_printf(s, "txdma[%d]    %04x\n", i,
2423                                                 UDC_TXDMA_REG(i + 1));
2424                         }
2425                 }
2426         }
2427
2428         tmp = UDC_DEVSTAT_REG;
2429         if (tmp & UDC_ATT) {
2430                 proc_ep_show(s, &udc->ep[0]);
2431                 if (tmp & UDC_ADD) {
2432                         list_for_each_entry (ep, &udc->gadget.ep_list,
2433                                         ep.ep_list) {
2434                                 if (ep->desc)
2435                                         proc_ep_show(s, ep);
2436                         }
2437                 }
2438         }
2439         spin_unlock_irqrestore(&udc->lock, flags);
2440         return 0;
2441 }
2442
2443 static int proc_udc_open(struct inode *inode, struct file *file)
2444 {
2445         return single_open(file, proc_udc_show, NULL);
2446 }
2447
2448 static struct file_operations proc_ops = {
2449         .open           = proc_udc_open,
2450         .read           = seq_read,
2451         .llseek         = seq_lseek,
2452         .release        = single_release,
2453 };
2454
2455 static void create_proc_file(void)
2456 {
2457         struct proc_dir_entry *pde;
2458
2459         pde = create_proc_entry (proc_filename, 0, NULL);
2460         if (pde)
2461                 pde->proc_fops = &proc_ops;
2462 }
2463
2464 static void remove_proc_file(void)
2465 {
2466         remove_proc_entry(proc_filename, NULL);
2467 }
2468
2469 #else
2470
2471 static inline void create_proc_file(void) {}
2472 static inline void remove_proc_file(void) {}
2473
2474 #endif
2475
2476 /*-------------------------------------------------------------------------*/
2477
2478 /* Before this controller can enumerate, we need to pick an endpoint
2479  * configuration, or "fifo_mode"  That involves allocating 2KB of packet
2480  * buffer space among the endpoints we'll be operating.
2481  *
2482  * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
2483  * UDC_SYSCON_1_REG.CFG_LOCK is set can now work.  We won't use that
2484  * capability yet though.
2485  */
2486 static unsigned __init
2487 omap_ep_setup(char *name, u8 addr, u8 type,
2488                 unsigned buf, unsigned maxp, int dbuf)
2489 {
2490         struct omap_ep  *ep;
2491         u16             epn_rxtx = 0;
2492
2493         /* OUT endpoints first, then IN */
2494         ep = &udc->ep[addr & 0xf];
2495         if (addr & USB_DIR_IN)
2496                 ep += 16;
2497
2498         /* in case of ep init table bugs */
2499         BUG_ON(ep->name[0]);
2500
2501         /* chip setup ... bit values are same for IN, OUT */
2502         if (type == USB_ENDPOINT_XFER_ISOC) {
2503                 switch (maxp) {
2504                 case 8:         epn_rxtx = 0 << 12; break;
2505                 case 16:        epn_rxtx = 1 << 12; break;
2506                 case 32:        epn_rxtx = 2 << 12; break;
2507                 case 64:        epn_rxtx = 3 << 12; break;
2508                 case 128:       epn_rxtx = 4 << 12; break;
2509                 case 256:       epn_rxtx = 5 << 12; break;
2510                 case 512:       epn_rxtx = 6 << 12; break;
2511                 default:        BUG();
2512                 }
2513                 epn_rxtx |= UDC_EPN_RX_ISO;
2514                 dbuf = 1;
2515         } else {
2516                 /* double-buffering "not supported" on 15xx,
2517                  * and ignored for PIO-IN on 16xx
2518                  */
2519                 if (!use_dma || cpu_is_omap15xx())
2520                         dbuf = 0;
2521
2522                 switch (maxp) {
2523                 case 8:         epn_rxtx = 0 << 12; break;
2524                 case 16:        epn_rxtx = 1 << 12; break;
2525                 case 32:        epn_rxtx = 2 << 12; break;
2526                 case 64:        epn_rxtx = 3 << 12; break;
2527                 default:        BUG();
2528                 }
2529                 if (dbuf && addr)
2530                         epn_rxtx |= UDC_EPN_RX_DB;
2531                 init_timer(&ep->timer);
2532                 ep->timer.function = pio_out_timer;
2533                 ep->timer.data = (unsigned long) ep;
2534         }
2535         if (addr)
2536                 epn_rxtx |= UDC_EPN_RX_VALID;
2537         BUG_ON(buf & 0x07);
2538         epn_rxtx |= buf >> 3;
2539
2540         DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2541                 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2542
2543         if (addr & USB_DIR_IN)
2544                 UDC_EP_TX_REG(addr & 0xf) = epn_rxtx;
2545         else
2546                 UDC_EP_RX_REG(addr) = epn_rxtx;
2547
2548         /* next endpoint's buffer starts after this one's */
2549         buf += maxp;
2550         if (dbuf)
2551                 buf += maxp;
2552         BUG_ON(buf > 2048);
2553
2554         /* set up driver data structures */
2555         BUG_ON(strlen(name) >= sizeof ep->name);
2556         strlcpy(ep->name, name, sizeof ep->name);
2557         INIT_LIST_HEAD(&ep->queue);
2558         INIT_LIST_HEAD(&ep->iso);
2559         ep->bEndpointAddress = addr;
2560         ep->bmAttributes = type;
2561         ep->double_buf = dbuf;
2562         ep->udc = udc;
2563
2564         ep->ep.name = ep->name;
2565         ep->ep.ops = &omap_ep_ops;
2566         ep->ep.maxpacket = ep->maxpacket = maxp;
2567         list_add_tail (&ep->ep.ep_list, &udc->gadget.ep_list);
2568
2569         return buf;
2570 }
2571
2572 static void omap_udc_release(struct device *dev)
2573 {
2574         complete(udc->done);
2575         kfree (udc);
2576         udc = NULL;
2577 }
2578
2579 static int __init
2580 omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv)
2581 {
2582         unsigned        tmp, buf;
2583
2584         /* abolish any previous hardware state */
2585         UDC_SYSCON1_REG = 0;
2586         UDC_IRQ_EN_REG = 0;
2587         UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
2588         UDC_DMA_IRQ_EN_REG = 0;
2589         UDC_RXDMA_CFG_REG = 0;
2590         UDC_TXDMA_CFG_REG = 0;
2591
2592         /* UDC_PULLUP_EN gates the chip clock */
2593         // OTG_SYSCON_1_REG |= DEV_IDLE_EN;
2594
2595         udc = kmalloc (sizeof *udc, SLAB_KERNEL);
2596         if (!udc)
2597                 return -ENOMEM;
2598
2599         memset(udc, 0, sizeof *udc);
2600         spin_lock_init (&udc->lock);
2601
2602         udc->gadget.ops = &omap_gadget_ops;
2603         udc->gadget.ep0 = &udc->ep[0].ep;
2604         INIT_LIST_HEAD(&udc->gadget.ep_list);
2605         INIT_LIST_HEAD(&udc->iso);
2606         udc->gadget.speed = USB_SPEED_UNKNOWN;
2607         udc->gadget.name = driver_name;
2608
2609         device_initialize(&udc->gadget.dev);
2610         strcpy (udc->gadget.dev.bus_id, "gadget");
2611         udc->gadget.dev.release = omap_udc_release;
2612         udc->gadget.dev.parent = &odev->dev;
2613         if (use_dma)
2614                 udc->gadget.dev.dma_mask = odev->dev.dma_mask;
2615
2616         udc->transceiver = xceiv;
2617
2618         /* ep0 is special; put it right after the SETUP buffer */
2619         buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2620                         8 /* after SETUP */, 64 /* maxpacket */, 0);
2621         list_del_init(&udc->ep[0].ep.ep_list);
2622
2623         /* initially disable all non-ep0 endpoints */
2624         for (tmp = 1; tmp < 15; tmp++) {
2625                 UDC_EP_RX_REG(tmp) = 0;
2626                 UDC_EP_TX_REG(tmp) = 0;
2627         }
2628
2629 #define OMAP_BULK_EP(name,addr) \
2630         buf = omap_ep_setup(name "-bulk", addr, \
2631                         USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2632 #define OMAP_INT_EP(name,addr, maxp) \
2633         buf = omap_ep_setup(name "-int", addr, \
2634                         USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2635 #define OMAP_ISO_EP(name,addr, maxp) \
2636         buf = omap_ep_setup(name "-iso", addr, \
2637                         USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2638
2639         switch (fifo_mode) {
2640         case 0:
2641                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2642                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2643                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2644                 break;
2645         case 1:
2646                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2647                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2648                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2649
2650                 OMAP_BULK_EP("ep3in",  USB_DIR_IN  | 3);
2651                 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
2652                 OMAP_INT_EP("ep10in",  USB_DIR_IN  | 10, 16);
2653
2654                 OMAP_BULK_EP("ep5in",  USB_DIR_IN  | 5);
2655                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2656                 OMAP_INT_EP("ep11in",  USB_DIR_IN  | 11, 16);
2657
2658                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2659                 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
2660                 OMAP_INT_EP("ep12in",  USB_DIR_IN  | 12, 16);
2661
2662                 OMAP_BULK_EP("ep7in",  USB_DIR_IN  | 7);
2663                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2664                 OMAP_INT_EP("ep13in",  USB_DIR_IN  | 13, 16);
2665                 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2666
2667                 OMAP_BULK_EP("ep8in",  USB_DIR_IN  | 8);
2668                 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
2669                 OMAP_INT_EP("ep14in",  USB_DIR_IN  | 14, 16);
2670                 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2671
2672                 OMAP_BULK_EP("ep15in",  USB_DIR_IN  | 15);
2673                 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
2674
2675                 break;
2676
2677 #ifdef  USE_ISO
2678         case 2:                 /* mixed iso/bulk */
2679                 OMAP_ISO_EP("ep1in",   USB_DIR_IN  | 1, 256);
2680                 OMAP_ISO_EP("ep2out",  USB_DIR_OUT | 2, 256);
2681                 OMAP_ISO_EP("ep3in",   USB_DIR_IN  | 3, 128);
2682                 OMAP_ISO_EP("ep4out",  USB_DIR_OUT | 4, 128);
2683
2684                 OMAP_INT_EP("ep5in",   USB_DIR_IN  | 5, 16);
2685
2686                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2687                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2688                 OMAP_INT_EP("ep8in",   USB_DIR_IN  | 8, 16);
2689                 break;
2690         case 3:                 /* mixed bulk/iso */
2691                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2692                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2693                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2694
2695                 OMAP_BULK_EP("ep4in",  USB_DIR_IN  | 4);
2696                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2697                 OMAP_INT_EP("ep6in",   USB_DIR_IN  | 6, 16);
2698
2699                 OMAP_ISO_EP("ep7in",   USB_DIR_IN  | 7, 256);
2700                 OMAP_ISO_EP("ep8out",  USB_DIR_OUT | 8, 256);
2701                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2702                 break;
2703 #endif
2704
2705         /* add more modes as needed */
2706
2707         default:
2708                 ERR("unsupported fifo_mode #%d\n", fifo_mode);
2709                 return -ENODEV;
2710         }
2711         UDC_SYSCON1_REG = UDC_CFG_LOCK|UDC_SELF_PWR;
2712         INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2713         return 0;
2714 }
2715
2716 static int __init omap_udc_probe(struct device *dev)
2717 {
2718         struct platform_device  *odev = to_platform_device(dev);
2719         int                     status = -ENODEV;
2720         int                     hmc;
2721         struct otg_transceiver  *xceiv = NULL;
2722         const char              *type = NULL;
2723         struct omap_usb_config  *config = dev->platform_data;
2724
2725         /* NOTE:  "knows" the order of the resources! */
2726         if (!request_mem_region(odev->resource[0].start,
2727                         odev->resource[0].end - odev->resource[0].start + 1,
2728                         driver_name)) {
2729                 DBG("request_mem_region failed\n");
2730                 return -EBUSY;
2731         }
2732
2733         INFO("OMAP UDC rev %d.%d%s\n",
2734                 UDC_REV_REG >> 4, UDC_REV_REG & 0xf,
2735                 config->otg ? ", Mini-AB" : "");
2736
2737         /* use the mode given to us by board init code */
2738         if (cpu_is_omap15xx()) {
2739                 hmc = HMC_1510;
2740                 type = "(unknown)";
2741
2742                 if (machine_is_omap_innovator()) {
2743                         /* just set up software VBUS detect, and then
2744                          * later rig it so we always report VBUS.
2745                          * FIXME without really sensing VBUS, we can't
2746                          * know when to turn PULLUP_EN on/off; and that
2747                          * means we always "need" the 48MHz clock.
2748                          */
2749                         u32 tmp = FUNC_MUX_CTRL_0_REG;
2750
2751                         FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
2752                         tmp |= VBUS_MODE_1510;
2753                         tmp &= ~VBUS_CTRL_1510;
2754                         FUNC_MUX_CTRL_0_REG = tmp;
2755                 }
2756         } else {
2757                 /* The transceiver may package some GPIO logic or handle
2758                  * loopback and/or transceiverless setup; if we find one,
2759                  * use it.  Except for OTG, we don't _need_ to talk to one;
2760                  * but not having one probably means no VBUS detection.
2761                  */
2762                 xceiv = otg_get_transceiver();
2763                 if (xceiv)
2764                         type = xceiv->label;
2765                 else if (config->otg) {
2766                         DBG("OTG requires external transceiver!\n");
2767                         goto cleanup0;
2768                 }
2769
2770                 hmc = HMC_1610;
2771                 switch (hmc) {
2772                 case 0:                 /* POWERUP DEFAULT == 0 */
2773                 case 4:
2774                 case 12:
2775                 case 20:
2776                         if (!cpu_is_omap1710()) {
2777                                 type = "integrated";
2778                                 break;
2779                         }
2780                         /* FALL THROUGH */
2781                 case 3:
2782                 case 11:
2783                 case 16:
2784                 case 19:
2785                 case 25:
2786                         if (!xceiv) {
2787                                 DBG("external transceiver not registered!\n");
2788                                 type = "unknown";
2789                         }
2790                         break;
2791                 case 21:                        /* internal loopback */
2792                         type = "loopback";
2793                         break;
2794                 case 14:                        /* transceiverless */
2795                         if (cpu_is_omap1710())
2796                                 goto bad_on_1710;
2797                         /* FALL THROUGH */
2798                 case 13:
2799                 case 15:
2800                         type = "no";
2801                         break;
2802
2803                 default:
2804 bad_on_1710:
2805                         ERR("unrecognized UDC HMC mode %d\n", hmc);
2806                         goto cleanup0;
2807                 }
2808         }
2809         INFO("hmc mode %d, %s transceiver\n", hmc, type);
2810
2811         /* a "gadget" abstracts/virtualizes the controller */
2812         status = omap_udc_setup(odev, xceiv);
2813         if (status) {
2814                 goto cleanup0;
2815         }
2816         xceiv = NULL;
2817         // "udc" is now valid
2818         pullup_disable(udc);
2819 #if     defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2820         udc->gadget.is_otg = (config->otg != 0);
2821 #endif
2822
2823         /* starting with omap1710 es2.0, clear toggle is a separate bit */
2824         if (UDC_REV_REG >= 0x61)
2825                 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2826         else
2827                 udc->clr_halt = UDC_RESET_EP;
2828
2829         /* USB general purpose IRQ:  ep0, state changes, dma, etc */
2830         status = request_irq(odev->resource[1].start, omap_udc_irq,
2831                         SA_SAMPLE_RANDOM, driver_name, udc);
2832         if (status != 0) {
2833                 ERR( "can't get irq %ld, err %d\n",
2834                         odev->resource[1].start, status);
2835                 goto cleanup1;
2836         }
2837
2838         /* USB "non-iso" IRQ (PIO for all but ep0) */
2839         status = request_irq(odev->resource[2].start, omap_udc_pio_irq,
2840                         SA_SAMPLE_RANDOM, "omap_udc pio", udc);
2841         if (status != 0) {
2842                 ERR( "can't get irq %ld, err %d\n",
2843                         odev->resource[2].start, status);
2844                 goto cleanup2;
2845         }
2846 #ifdef  USE_ISO
2847         status = request_irq(odev->resource[3].start, omap_udc_iso_irq,
2848                         SA_INTERRUPT, "omap_udc iso", udc);
2849         if (status != 0) {
2850                 ERR("can't get irq %ld, err %d\n",
2851                         odev->resource[3].start, status);
2852                 goto cleanup3;
2853         }
2854 #endif
2855
2856         create_proc_file();
2857         device_add(&udc->gadget.dev);
2858         return 0;
2859
2860 #ifdef  USE_ISO
2861 cleanup3:
2862         free_irq(odev->resource[2].start, udc);
2863 #endif
2864
2865 cleanup2:
2866         free_irq(odev->resource[1].start, udc);
2867
2868 cleanup1:
2869         kfree (udc);
2870         udc = NULL;
2871
2872 cleanup0:
2873         if (xceiv)
2874                 put_device(xceiv->dev);
2875         release_mem_region(odev->resource[0].start,
2876                         odev->resource[0].end - odev->resource[0].start + 1);
2877         return status;
2878 }
2879
2880 static int __exit omap_udc_remove(struct device *dev)
2881 {
2882         struct platform_device  *odev = to_platform_device(dev);
2883         DECLARE_COMPLETION(done);
2884
2885         if (!udc)
2886                 return -ENODEV;
2887
2888         udc->done = &done;
2889
2890         pullup_disable(udc);
2891         if (udc->transceiver) {
2892                 put_device(udc->transceiver->dev);
2893                 udc->transceiver = NULL;
2894         }
2895         UDC_SYSCON1_REG = 0;
2896
2897         remove_proc_file();
2898
2899 #ifdef  USE_ISO
2900         free_irq(odev->resource[3].start, udc);
2901 #endif
2902         free_irq(odev->resource[2].start, udc);
2903         free_irq(odev->resource[1].start, udc);
2904
2905         release_mem_region(odev->resource[0].start,
2906                         odev->resource[0].end - odev->resource[0].start + 1);
2907
2908         device_unregister(&udc->gadget.dev);
2909         wait_for_completion(&done);
2910
2911         return 0;
2912 }
2913
2914 /* suspend/resume/wakeup from sysfs (echo > power/state) or when the
2915  * system is forced into deep sleep
2916  *
2917  * REVISIT we should probably reject suspend requests when there's a host
2918  * session active, rather than disconnecting, at least on boards that can
2919  * report VBUS irqs (UDC_DEVSTAT_REG.UDC_ATT).  And in any case, we need to
2920  * make host resumes and VBUS detection trigger OMAP wakeup events; that
2921  * may involve talking to an external transceiver (e.g. isp1301).
2922  */
2923
2924 static int omap_udc_suspend(struct device *dev, pm_message_t message)
2925 {
2926         u32     devstat;
2927
2928         devstat = UDC_DEVSTAT_REG;
2929
2930         /* we're requesting 48 MHz clock if the pullup is enabled
2931          * (== we're attached to the host) and we're not suspended,
2932          * which would prevent entry to deep sleep...
2933          */
2934         if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
2935                 WARN("session active; suspend requires disconnect\n");
2936                 omap_pullup(&udc->gadget, 0);
2937         }
2938
2939         udc->gadget.dev.power.power_state = PMSG_SUSPEND;
2940         udc->gadget.dev.parent->power.power_state = PMSG_SUSPEND;
2941         return 0;
2942 }
2943
2944 static int omap_udc_resume(struct device *dev)
2945 {
2946         DBG("resume + wakeup/SRP\n");
2947         omap_pullup(&udc->gadget, 1);
2948
2949         /* maybe the host would enumerate us if we nudged it */
2950         msleep(100);
2951         return omap_wakeup(&udc->gadget);
2952 }
2953
2954 /*-------------------------------------------------------------------------*/
2955
2956 static struct device_driver udc_driver = {
2957         .name           = (char *) driver_name,
2958         .owner          = THIS_MODULE,
2959         .bus            = &platform_bus_type,
2960         .probe          = omap_udc_probe,
2961         .remove         = __exit_p(omap_udc_remove),
2962         .suspend        = omap_udc_suspend,
2963         .resume         = omap_udc_resume,
2964 };
2965
2966 static int __init udc_init(void)
2967 {
2968         INFO("%s, version: " DRIVER_VERSION
2969 #ifdef  USE_ISO
2970                 " (iso)"
2971 #endif
2972                 "%s\n", driver_desc,
2973                 use_dma ?  " (dma)" : "");
2974         return driver_register(&udc_driver);
2975 }
2976 module_init(udc_init);
2977
2978 static void __exit udc_exit(void)
2979 {
2980         driver_unregister(&udc_driver);
2981 }
2982 module_exit(udc_exit);
2983
2984 MODULE_DESCRIPTION(DRIVER_DESC);
2985 MODULE_LICENSE("GPL");
2986