drivers/usb/gadget/omap_udc.c

   1 /*
   2  * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
   3  *
   4  * Copyright (C) 2004 Texas Instruments, Inc.
   5  * Copyright (C) 2004-2005 David Brownell
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 #undef  DEBUG
  23 #undef  VERBOSE
  24
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/ioport.h>
  28 #include <linux/types.h>
  29 #include <linux/errno.h>
  30 #include <linux/delay.h>
  31 #include <linux/slab.h>
  32 #include <linux/init.h>
  33 #include <linux/timer.h>
  34 #include <linux/list.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/proc_fs.h>
  37 #include <linux/mm.h>
  38 #include <linux/moduleparam.h>
  39 #include <linux/platform_device.h>
  40 #include <linux/usb/ch9.h>
  41 #include <linux/usb_gadget.h>
  42 #include <linux/usb/otg.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/clk.h>
  45
  46 #include <asm/byteorder.h>
  47 #include <asm/io.h>
  48 #include <asm/irq.h>
  49 #include <asm/system.h>
  50 #include <asm/unaligned.h>
  51 #include <asm/mach-types.h>
  52
  53 #include <asm/arch/dma.h>
  54 #include <asm/arch/usb.h>
  55
  56 #include "omap_udc.h"
  57
  58 #undef  USB_TRACE
  59
  60 /* bulk DMA seems to be behaving for both IN and OUT */
  61 #define USE_DMA
  62
  63 /* FIXME: OMAP2 currently has some problem in DMA mode */
  64 #ifdef CONFIG_ARCH_OMAP2
  65 #undef USE_DMA
  66 #endif
  67
  68 /* ISO too */
  69 #define USE_ISO
  70
  71 #define DRIVER_DESC     "OMAP UDC driver"
  72 #define DRIVER_VERSION  "4 October 2004"
  73
  74 #define DMA_ADDR_INVALID        (~(dma_addr_t)0)
  75
  76
  77 /*
  78  * The OMAP UDC needs _very_ early endpoint setup:  before enabling the
  79  * D+ pullup to allow enumeration.  That's too early for the gadget
  80  * framework to use from usb_endpoint_enable(), which happens after
  81  * enumeration as part of activating an interface.  (But if we add an
  82  * optional new "UDC not yet running" state to the gadget driver model,
  83  * even just during driver binding, the endpoint autoconfig logic is the
  84  * natural spot to manufacture new endpoints.)
  85  *
  86  * So instead of using endpoint enable calls to control the hardware setup,
  87  * this driver defines a "fifo mode" parameter.  It's used during driver
  88  * initialization to choose among a set of pre-defined endpoint configs.
  89  * See omap_udc_setup() for available modes, or to add others.  That code
  90  * lives in an init section, so use this driver as a module if you need
  91  * to change the fifo mode after the kernel boots.
  92  *
  93  * Gadget drivers normally ignore endpoints they don't care about, and
  94  * won't include them in configuration descriptors.  That means only
  95  * misbehaving hosts would even notice they exist.
  96  */
  97 #ifdef  USE_ISO
  98 static unsigned fifo_mode = 3;
  99 #else
 100 static unsigned fifo_mode = 0;
 101 #endif
 102
 103 /* "modprobe omap_udc fifo_mode=42", or else as a kernel
 104  * boot parameter "omap_udc:fifo_mode=42"
 105  */
 106 module_param (fifo_mode, uint, 0);
 107 MODULE_PARM_DESC (fifo_mode, "endpoint configuration");
 108
 109 #ifdef  USE_DMA
 110 static unsigned use_dma = 1;
 111
 112 /* "modprobe omap_udc use_dma=y", or else as a kernel
 113  * boot parameter "omap_udc:use_dma=y"
 114  */
 115 module_param (use_dma, bool, 0);
 116 MODULE_PARM_DESC (use_dma, "enable/disable DMA");
 117 #else   /* !USE_DMA */
 118
 119 /* save a bit of code */
 120 #define use_dma         0
 121 #endif  /* !USE_DMA */
 122
 123
 124 static const char driver_name [] = "omap_udc";
 125 static const char driver_desc [] = DRIVER_DESC;
 126
 127 /*-------------------------------------------------------------------------*/
 128
 129 /* there's a notion of "current endpoint" for modifying endpoint
 130  * state, and PIO access to its FIFO.
 131  */
 132
 133 static void use_ep(struct omap_ep *ep, u16 select)
 134 {
 135         u16     num = ep->bEndpointAddress & 0x0f;
 136
 137         if (ep->bEndpointAddress & USB_DIR_IN)
 138                 num |= UDC_EP_DIR;
 139         UDC_EP_NUM_REG = num | select;
 140         /* when select, MUST deselect later !! */
 141 }
 142
 143 static inline void deselect_ep(void)
 144 {
 145         UDC_EP_NUM_REG &= ~UDC_EP_SEL;
 146         /* 6 wait states before TX will happen */
 147 }
 148
 149 static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
 150
 151 /*-------------------------------------------------------------------------*/
 152
 153 static int omap_ep_enable(struct usb_ep *_ep,
 154                 const struct usb_endpoint_descriptor *desc)
 155 {
 156         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 157         struct omap_udc *udc;
 158         unsigned long   flags;
 159         u16             maxp;
 160
 161         /* catch various bogus parameters */
 162         if (!_ep || !desc || ep->desc
 163                         || desc->bDescriptorType != USB_DT_ENDPOINT
 164                         || ep->bEndpointAddress != desc->bEndpointAddress
 165                         || ep->maxpacket < le16_to_cpu
 166                                                 (desc->wMaxPacketSize)) {
 167                 DBG("%s, bad ep or descriptor\n", __FUNCTION__);
 168                 return -EINVAL;
 169         }
 170         maxp = le16_to_cpu (desc->wMaxPacketSize);
 171         if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
 172                                 && maxp != ep->maxpacket)
 173                         || le16_to_cpu(desc->wMaxPacketSize) > ep->maxpacket
 174                         || !desc->wMaxPacketSize) {
 175                 DBG("%s, bad %s maxpacket\n", __FUNCTION__, _ep->name);
 176                 return -ERANGE;
 177         }
 178
 179 #ifdef  USE_ISO
 180         if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
 181                                 && desc->bInterval != 1)) {
 182                 /* hardware wants period = 1; USB allows 2^(Interval-1) */
 183                 DBG("%s, unsupported ISO period %dms\n", _ep->name,
 184                                 1 << (desc->bInterval - 1));
 185                 return -EDOM;
 186         }
 187 #else
 188         if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 189                 DBG("%s, ISO nyet\n", _ep->name);
 190                 return -EDOM;
 191         }
 192 #endif
 193
 194         /* xfer types must match, except that interrupt ~= bulk */
 195         if (ep->bmAttributes != desc->bmAttributes
 196                         && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
 197                         && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
 198                 DBG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
 199                 return -EINVAL;
 200         }
 201
 202         udc = ep->udc;
 203         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
 204                 DBG("%s, bogus device state\n", __FUNCTION__);
 205                 return -ESHUTDOWN;
 206         }
 207
 208         spin_lock_irqsave(&udc->lock, flags);
 209
 210         ep->desc = desc;
 211         ep->irqs = 0;
 212         ep->stopped = 0;
 213         ep->ep.maxpacket = maxp;
 214
 215         /* set endpoint to initial state */
 216         ep->dma_channel = 0;
 217         ep->has_dma = 0;
 218         ep->lch = -1;
 219         use_ep(ep, UDC_EP_SEL);
 220         UDC_CTRL_REG = udc->clr_halt;
 221         ep->ackwait = 0;
 222         deselect_ep();
 223
 224         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
 225                 list_add(&ep->iso, &udc->iso);
 226
 227         /* maybe assign a DMA channel to this endpoint */
 228         if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
 229                 /* FIXME ISO can dma, but prefers first channel */
 230                 dma_channel_claim(ep, 0);
 231
 232         /* PIO OUT may RX packets */
 233         if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
 234                         && !ep->has_dma
 235                         && !(ep->bEndpointAddress & USB_DIR_IN)) {
 236                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
 237                 ep->ackwait = 1 + ep->double_buf;
 238         }
 239
 240         spin_unlock_irqrestore(&udc->lock, flags);
 241         VDBG("%s enabled\n", _ep->name);
 242         return 0;
 243 }
 244
 245 static void nuke(struct omap_ep *, int status);
 246
 247 static int omap_ep_disable(struct usb_ep *_ep)
 248 {
 249         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
 250         unsigned long   flags;
 251
 252         if (!_ep || !ep->desc) {
 253                 DBG("%s, %s not enabled\n", __FUNCTION__,
 254                         _ep ? ep->ep.name : NULL);
 255                 return -EINVAL;
 256         }
 257
 258         spin_lock_irqsave(&ep->udc->lock, flags);
 259         ep->desc = NULL;
 260         nuke (ep, -ESHUTDOWN);
 261         ep->ep.maxpacket = ep->maxpacket;
 262         ep->has_dma = 0;
 263         UDC_CTRL_REG = UDC_SET_HALT;
 264         list_del_init(&ep->iso);
 265         del_timer(&ep->timer);
 266
 267         spin_unlock_irqrestore(&ep->udc->lock, flags);
 268
 269         VDBG("%s disabled\n", _ep->name);
 270         return 0;
 271 }
 272
 273 /*-------------------------------------------------------------------------*/
 274
 275 static struct usb_request *
 276 omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
 277 {
 278         struct omap_req *req;
 279
 280         req = kzalloc(sizeof(*req), gfp_flags);
 281         if (req) {
 282                 req->req.dma = DMA_ADDR_INVALID;
 283                 INIT_LIST_HEAD (&req->queue);
 284         }
 285         return &req->req;
 286 }
 287
 288 static void
 289 omap_free_request(struct usb_ep *ep, struct usb_request *_req)
 290 {
 291         struct omap_req *req = container_of(_req, struct omap_req, req);
 292
 293         if (_req)
 294                 kfree (req);
 295 }
 296
 297 /*-------------------------------------------------------------------------*/
 298
 299 /*
 300  * dma-coherent memory allocation (for dma-capable endpoints)
 301  *
 302  * NOTE: the dma_*_coherent() API calls suck.  Most implementations are
 303  * (a) page-oriented, so small buffers lose big; and (b) asymmetric with
 304  * respect to calls with irqs disabled:  alloc is safe, free is not.
 305  * We currently work around (b), but not (a).
 306  */
 307
 308 static void *
 309 omap_alloc_buffer(
 310         struct usb_ep   *_ep,
 311         unsigned        bytes,
 312         dma_addr_t      *dma,
 313         gfp_t           gfp_flags
 314 )
 315 {
 316         void            *retval;
 317         struct omap_ep  *ep;
 318
 319         if (!_ep)
 320                 return NULL;
 321
 322         ep = container_of(_ep, struct omap_ep, ep);
 323         if (use_dma && ep->has_dma) {
 324                 static int      warned;
 325                 if (!warned && bytes < PAGE_SIZE) {
 326                         dev_warn(ep->udc->gadget.dev.parent,
 327                                 "using dma_alloc_coherent for "
 328                                 "small allocations wastes memory\n");
 329                         warned++;
 330                 }
 331                 return dma_alloc_coherent(ep->udc->gadget.dev.parent,
 332                                 bytes, dma, gfp_flags);
 333         }
 334
 335         retval = kmalloc(bytes, gfp_flags);
 336         if (retval)
 337                 *dma = virt_to_phys(retval);
 338         return retval;
 339 }
 340
 341 static DEFINE_SPINLOCK(buflock);
 342 static LIST_HEAD(buffers);
 343
 344 struct free_record {
 345         struct list_head        list;
 346         struct device           *dev;
 347         unsigned                bytes;
 348         dma_addr_t              dma;
 349 };
 350
 351 static void do_free(unsigned long ignored)
 352 {
 353         spin_lock_irq(&buflock);
 354         while (!list_empty(&buffers)) {
 355                 struct free_record      *buf;
 356
 357                 buf = list_entry(buffers.next, struct free_record, list);
 358                 list_del(&buf->list);
 359                 spin_unlock_irq(&buflock);
 360
 361                 dma_free_coherent(buf->dev, buf->bytes, buf, buf->dma);
 362
 363                 spin_lock_irq(&buflock);
 364         }
 365         spin_unlock_irq(&buflock);
 366 }
 367
 368 static DECLARE_TASKLET(deferred_free, do_free, 0);
 369
 370 static void omap_free_buffer(
 371         struct usb_ep   *_ep,
 372         void            *buf,
 373         dma_addr_t      dma,
 374         unsigned        bytes
 375 )
 376 {
 377         if (!_ep) {
 378                 WARN_ON(1);
 379                 return;
 380         }
 381
 382         /* free memory into the right allocator */
 383         if (dma != DMA_ADDR_INVALID) {
 384                 struct omap_ep          *ep;
 385                 struct free_record      *rec = buf;
 386                 unsigned long           flags;
 387
 388                 ep = container_of(_ep, struct omap_ep, ep);
 389
 390                 rec->dev = ep->udc->gadget.dev.parent;
 391                 rec->bytes = bytes;
 392                 rec->dma = dma;
 393
 394                 spin_lock_irqsave(&buflock, flags);
 395                 list_add_tail(&rec->list, &buffers);
 396                 tasklet_schedule(&deferred_free);
 397                 spin_unlock_irqrestore(&buflock, flags);
 398         } else
 399                 kfree(buf);
 400 }
 401
 402 /*-------------------------------------------------------------------------*/
 403
 404 static void
 405 done(struct omap_ep *ep, struct omap_req *req, int status)
 406 {
 407         unsigned                stopped = ep->stopped;
 408
 409         list_del_init(&req->queue);
 410
 411         if (req->req.status == -EINPROGRESS)
 412                 req->req.status = status;
 413         else
 414                 status = req->req.status;
 415
 416         if (use_dma && ep->has_dma) {
 417                 if (req->mapped) {
 418                         dma_unmap_single(ep->udc->gadget.dev.parent,
 419                                 req->req.dma, req->req.length,
 420                                 (ep->bEndpointAddress & USB_DIR_IN)
 421                                         ? DMA_TO_DEVICE
 422                                         : DMA_FROM_DEVICE);
 423                         req->req.dma = DMA_ADDR_INVALID;
 424                         req->mapped = 0;
 425                 } else
 426                         dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
 427                                 req->req.dma, req->req.length,
 428                                 (ep->bEndpointAddress & USB_DIR_IN)
 429                                         ? DMA_TO_DEVICE
 430                                         : DMA_FROM_DEVICE);
 431         }
 432
 433 #ifndef USB_TRACE
 434         if (status && status != -ESHUTDOWN)
 435 #endif
 436                 VDBG("complete %s req %p stat %d len %u/%u\n",
 437                         ep->ep.name, &req->req, status,
 438                         req->req.actual, req->req.length);
 439
 440         /* don't modify queue heads during completion callback */
 441         ep->stopped = 1;
 442         spin_unlock(&ep->udc->lock);
 443         req->req.complete(&ep->ep, &req->req);
 444         spin_lock(&ep->udc->lock);
 445         ep->stopped = stopped;
 446 }
 447
 448 /*-------------------------------------------------------------------------*/
 449
 450 #define UDC_FIFO_FULL           (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
 451 #define UDC_FIFO_UNWRITABLE     (UDC_EP_HALTED | UDC_FIFO_FULL)
 452
 453 #define FIFO_EMPTY      (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
 454 #define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
 455
 456 static inline int
 457 write_packet(u8 *buf, struct omap_req *req, unsigned max)
 458 {
 459         unsigned        len;
 460         u16             *wp;
 461
 462         len = min(req->req.length - req->req.actual, max);
 463         req->req.actual += len;
 464
 465         max = len;
 466         if (likely((((int)buf) & 1) == 0)) {
 467                 wp = (u16 *)buf;
 468                 while (max >= 2) {
 469                         UDC_DATA_REG = *wp++;
 470                         max -= 2;
 471                 }
 472                 buf = (u8 *)wp;
 473         }
 474         while (max--)
 475                 *(volatile u8 *)&UDC_DATA_REG = *buf++;
 476         return len;
 477 }
 478
 479 // FIXME change r/w fifo calling convention
 480
 481
 482 // return:  0 = still running, 1 = completed, negative = errno
 483 static int write_fifo(struct omap_ep *ep, struct omap_req *req)
 484 {
 485         u8              *buf;
 486         unsigned        count;
 487         int             is_last;
 488         u16             ep_stat;
 489
 490         buf = req->req.buf + req->req.actual;
 491         prefetch(buf);
 492
 493         /* PIO-IN isn't double buffered except for iso */
 494         ep_stat = UDC_STAT_FLG_REG;
 495         if (ep_stat & UDC_FIFO_UNWRITABLE)
 496                 return 0;
 497
 498         count = ep->ep.maxpacket;
 499         count = write_packet(buf, req, count);
 500         UDC_CTRL_REG = UDC_SET_FIFO_EN;
 501         ep->ackwait = 1;
 502
 503         /* last packet is often short (sometimes a zlp) */
 504         if (count != ep->ep.maxpacket)
 505                 is_last = 1;
 506         else if (req->req.length == req->req.actual
 507                         && !req->req.zero)
 508                 is_last = 1;
 509         else
 510                 is_last = 0;
 511
 512         /* NOTE:  requests complete when all IN data is in a
 513          * FIFO (or sometimes later, if a zlp was needed).
 514          * Use usb_ep_fifo_status() where needed.
 515          */
 516         if (is_last)
 517                 done(ep, req, 0);
 518         return is_last;
 519 }
 520
 521 static inline int
 522 read_packet(u8 *buf, struct omap_req *req, unsigned avail)
 523 {
 524         unsigned        len;
 525         u16             *wp;
 526
 527         len = min(req->req.length - req->req.actual, avail);
 528         req->req.actual += len;
 529         avail = len;
 530
 531         if (likely((((int)buf) & 1) == 0)) {
 532                 wp = (u16 *)buf;
 533                 while (avail >= 2) {
 534                         *wp++ = UDC_DATA_REG;
 535                         avail -= 2;
 536                 }
 537                 buf = (u8 *)wp;
 538         }
 539         while (avail--)
 540                 *buf++ = *(volatile u8 *)&UDC_DATA_REG;
 541         return len;
 542 }
 543
 544 // return:  0 = still running, 1 = queue empty, negative = errno
 545 static int read_fifo(struct omap_ep *ep, struct omap_req *req)
 546 {
 547         u8              *buf;
 548         unsigned        count, avail;
 549         int             is_last;
 550
 551         buf = req->req.buf + req->req.actual;
 552         prefetchw(buf);
 553
 554         for (;;) {
 555                 u16     ep_stat = UDC_STAT_FLG_REG;
 556
 557                 is_last = 0;
 558                 if (ep_stat & FIFO_EMPTY) {
 559                         if (!ep->double_buf)
 560                                 break;
 561                         ep->fnf = 1;
 562                 }
 563                 if (ep_stat & UDC_EP_HALTED)
 564                         break;
 565
 566                 if (ep_stat & UDC_FIFO_FULL)
 567                         avail = ep->ep.maxpacket;
 568                 else  {
 569                         avail = UDC_RXFSTAT_REG;
 570                         ep->fnf = ep->double_buf;
 571                 }
 572                 count = read_packet(buf, req, avail);
 573
 574                 /* partial packet reads may not be errors */
 575                 if (count < ep->ep.maxpacket) {
 576                         is_last = 1;
 577                         /* overflowed this request?  flush extra data */
 578                         if (count != avail) {
 579                                 req->req.status = -EOVERFLOW;
 580                                 avail -= count;
 581                                 while (avail--)
 582                                         (void) *(volatile u8 *)&UDC_DATA_REG;
 583                         }
 584                 } else if (req->req.length == req->req.actual)
 585                         is_last = 1;
 586                 else
 587                         is_last = 0;
 588
 589                 if (!ep->bEndpointAddress)
 590                         break;
 591                 if (is_last)
 592                         done(ep, req, 0);
 593                 break;
 594         }
 595         return is_last;
 596 }
 597
 598 /*-------------------------------------------------------------------------*/
 599
 600 static inline dma_addr_t dma_csac(unsigned lch)
 601 {
 602         dma_addr_t      csac;
 603
 604         /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
 605          * read before the DMA controller finished disabling the channel.
 606          */
 607         csac = OMAP_DMA_CSAC_REG(lch);
 608         if (csac == 0)
 609                 csac = OMAP_DMA_CSAC_REG(lch);
 610         return csac;
 611 }
 612
 613 static inline dma_addr_t dma_cdac(unsigned lch)
 614 {
 615         dma_addr_t      cdac;
 616
 617         /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
 618          * read before the DMA controller finished disabling the channel.
 619          */
 620         cdac = OMAP_DMA_CDAC_REG(lch);
 621         if (cdac == 0)
 622                 cdac = OMAP_DMA_CDAC_REG(lch);
 623         return cdac;
 624 }
 625
 626 static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
 627 {
 628         dma_addr_t      end;
 629
 630         /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
 631          * the last transfer's bytecount by more than a FIFO's worth.
 632          */
 633         if (cpu_is_omap15xx())
 634                 return 0;
 635
 636         end = dma_csac(ep->lch);
 637         if (end == ep->dma_counter)
 638                 return 0;
 639
 640         end |= start & (0xffff << 16);
 641         if (end < start)
 642                 end += 0x10000;
 643         return end - start;
 644 }
 645
 646 #define DMA_DEST_LAST(x) (cpu_is_omap15xx() \
 647                 ? OMAP_DMA_CSAC_REG(x) /* really: CPC */ \
 648                 : dma_cdac(x))
 649
 650 static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
 651 {
 652         dma_addr_t      end;
 653
 654         end = DMA_DEST_LAST(ep->lch);
 655         if (end == ep->dma_counter)
 656                 return 0;
 657
 658         end |= start & (0xffff << 16);
 659         if (cpu_is_omap15xx())
 660                 end++;
 661         if (end < start)
 662                 end += 0x10000;
 663         return end - start;
 664 }
 665
 666
 667 /* Each USB transfer request using DMA maps to one or more DMA transfers.
 668  * When DMA completion isn't request completion, the UDC continues with
 669  * the next DMA transfer for that USB transfer.
 670  */
 671
 672 static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
 673 {
 674         u16             txdma_ctrl;
 675         unsigned        length = req->req.length - req->req.actual;
 676         const int       sync_mode = cpu_is_omap15xx()
 677                                 ? OMAP_DMA_SYNC_FRAME
 678                                 : OMAP_DMA_SYNC_ELEMENT;
 679
 680         /* measure length in either bytes or packets */
 681         if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
 682                         || (cpu_is_omap15xx() && length < ep->maxpacket)) {
 683                 txdma_ctrl = UDC_TXN_EOT | length;
 684                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
 685                                 length, 1, sync_mode, 0, 0);
 686         } else {
 687                 length = min(length / ep->maxpacket,
 688                                 (unsigned) UDC_TXN_TSC + 1);
 689                 txdma_ctrl = length;
 690                 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
 691                                 ep->ep.maxpacket >> 1, length, sync_mode,
 692                                 0, 0);
 693                 length *= ep->maxpacket;
 694         }
 695         omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
 696                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
 697                 0, 0);
 698
 699         omap_start_dma(ep->lch);
 700         ep->dma_counter = dma_csac(ep->lch);
 701         UDC_DMA_IRQ_EN_REG |= UDC_TX_DONE_IE(ep->dma_channel);
 702         UDC_TXDMA_REG(ep->dma_channel) = UDC_TXN_START | txdma_ctrl;
 703         req->dma_bytes = length;
 704 }
 705
 706 static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
 707 {
 708         if (status == 0) {
 709                 req->req.actual += req->dma_bytes;
 710
 711                 /* return if this request needs to send data or zlp */
 712                 if (req->req.actual < req->req.length)
 713                         return;
 714                 if (req->req.zero
 715                                 && req->dma_bytes != 0
 716                                 && (req->req.actual % ep->maxpacket) == 0)
 717                         return;
 718         } else
 719                 req->req.actual += dma_src_len(ep, req->req.dma
 720                                                         + req->req.actual);
 721
 722         /* tx completion */
 723         omap_stop_dma(ep->lch);
 724         UDC_DMA_IRQ_EN_REG &= ~UDC_TX_DONE_IE(ep->dma_channel);
 725         done(ep, req, status);
 726 }
 727
 728 static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
 729 {
 730         unsigned packets;
 731
 732         /* NOTE:  we filtered out "short reads" before, so we know
 733          * the buffer has only whole numbers of packets.
 734          */
 735
 736         /* set up this DMA transfer, enable the fifo, start */
 737         packets = (req->req.length - req->req.actual) / ep->ep.maxpacket;
 738         packets = min(packets, (unsigned)UDC_RXN_TC + 1);
 739         req->dma_bytes = packets * ep->ep.maxpacket;
 740         omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
 741                         ep->ep.maxpacket >> 1, packets,
 742                         OMAP_DMA_SYNC_ELEMENT,
 743                         0, 0);
 744         omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
 745                 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
 746                 0, 0);
 747         ep->dma_counter = DMA_DEST_LAST(ep->lch);
 748
 749         UDC_RXDMA_REG(ep->dma_channel) = UDC_RXN_STOP | (packets - 1);
 750         UDC_DMA_IRQ_EN_REG |= UDC_RX_EOT_IE(ep->dma_channel);
 751         UDC_EP_NUM_REG = (ep->bEndpointAddress & 0xf);
 752         UDC_CTRL_REG = UDC_SET_FIFO_EN;
 753
 754         omap_start_dma(ep->lch);
 755 }
 756
 757 static void
 758 finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
 759 {
 760         u16     count;
 761
 762         if (status == 0)
 763                 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
 764         count = dma_dest_len(ep, req->req.dma + req->req.actual);
 765         count += req->req.actual;
 766         if (one)
 767                 count--;
 768         if (count <= req->req.length)
 769                 req->req.actual = count;
 770
 771         if (count != req->dma_bytes || status)
 772                 omap_stop_dma(ep->lch);
 773
 774         /* if this wasn't short, request may need another transfer */
 775         else if (req->req.actual < req->req.length)
 776                 return;
 777
 778         /* rx completion */
 779         UDC_DMA_IRQ_EN_REG &= ~UDC_RX_EOT_IE(ep->dma_channel);
 780         done(ep, req, status);
 781 }
 782
 783 static void dma_irq(struct omap_udc *udc, u16 irq_src)
 784 {
 785         u16             dman_stat = UDC_DMAN_STAT_REG;
 786         struct omap_ep  *ep;
 787         struct omap_req *req;
 788
 789         /* IN dma: tx to host */
 790         if (irq_src & UDC_TXN_DONE) {
 791                 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
 792                 ep->irqs++;
 793                 /* can see TXN_DONE after dma abort */
 794                 if (!list_empty(&ep->queue)) {
 795                         req = container_of(ep->queue.next,
 796                                                 struct omap_req, queue);
 797                         finish_in_dma(ep, req, 0);
 798                 }
 799                 UDC_IRQ_SRC_REG = UDC_TXN_DONE;
 800
 801                 if (!list_empty (&ep->queue)) {
 802                         req = container_of(ep->queue.next,
 803                                         struct omap_req, queue);
 804                         next_in_dma(ep, req);
 805                 }
 806         }
 807
 808         /* OUT dma: rx from host */
 809         if (irq_src & UDC_RXN_EOT) {
 810                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
 811                 ep->irqs++;
 812                 /* can see RXN_EOT after dma abort */
 813                 if (!list_empty(&ep->queue)) {
 814                         req = container_of(ep->queue.next,
 815                                         struct omap_req, queue);
 816                         finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
 817                 }
 818                 UDC_IRQ_SRC_REG = UDC_RXN_EOT;
 819
 820                 if (!list_empty (&ep->queue)) {
 821                         req = container_of(ep->queue.next,
 822                                         struct omap_req, queue);
 823                         next_out_dma(ep, req);
 824                 }
 825         }
 826
 827         if (irq_src & UDC_RXN_CNT) {
 828                 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
 829                 ep->irqs++;
 830                 /* omap15xx does this unasked... */
 831                 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
 832                 UDC_IRQ_SRC_REG = UDC_RXN_CNT;
 833         }
 834 }
 835
 836 static void dma_error(int lch, u16 ch_status, void *data)
 837 {
 838         struct omap_ep  *ep = data;
 839
 840         /* if ch_status & OMAP_DMA_DROP_IRQ ... */
 841         /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
 842         ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
 843
 844         /* complete current transfer ... */
 845 }
 846
 847 static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
 848 {
 849         u16     reg;
 850         int     status, restart, is_in;
 851
 852         is_in = ep->bEndpointAddress & USB_DIR_IN;
 853         if (is_in)
 854                 reg = UDC_TXDMA_CFG_REG;
 855         else
 856                 reg = UDC_RXDMA_CFG_REG;
 857         reg |= UDC_DMA_REQ;             /* "pulse" activated */
 858
 859         ep->dma_channel = 0;
 860         ep->lch = -1;
 861         if (channel == 0 || channel > 3) {
 862                 if ((reg & 0x0f00) == 0)
 863                         channel = 3;
 864                 else if ((reg & 0x00f0) == 0)
 865                         channel = 2;
 866                 else if ((reg & 0x000f) == 0)   /* preferred for ISO */
 867                         channel = 1;
 868                 else {
 869                         status = -EMLINK;
 870                         goto just_restart;
 871                 }
 872         }
 873         reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
 874         ep->dma_channel = channel;
 875
 876         if (is_in) {
 877                 status = omap_request_dma(OMAP_DMA_USB_W2FC_TX0 - 1 + channel,
 878                         ep->ep.name, dma_error, ep, &ep->lch);
 879                 if (status == 0) {
 880                         UDC_TXDMA_CFG_REG = reg;
 881                         /* EMIFF */
 882                         omap_set_dma_src_burst_mode(ep->lch,
 883                                                 OMAP_DMA_DATA_BURST_4);
 884                         omap_set_dma_src_data_pack(ep->lch, 1);
 885                         /* TIPB */
 886                         omap_set_dma_dest_params(ep->lch,
 887                                 OMAP_DMA_PORT_TIPB,
 888                                 OMAP_DMA_AMODE_CONSTANT,
 889                                 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG),
 890                                 0, 0);
 891                 }
 892         } else {
 893                 status = omap_request_dma(OMAP_DMA_USB_W2FC_RX0 - 1 + channel,
 894                         ep->ep.name, dma_error, ep, &ep->lch);
 895                 if (status == 0) {
 896                         UDC_RXDMA_CFG_REG = reg;
 897                         /* TIPB */
 898                         omap_set_dma_src_params(ep->lch,
 899                                 OMAP_DMA_PORT_TIPB,
 900                                 OMAP_DMA_AMODE_CONSTANT,
 901                                 (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG),
 902                                 0, 0);
 903                         /* EMIFF */
 904                         omap_set_dma_dest_burst_mode(ep->lch,
 905                                                 OMAP_DMA_DATA_BURST_4);
 906                         omap_set_dma_dest_data_pack(ep->lch, 1);
 907                 }
 908         }
 909         if (status)
 910                 ep->dma_channel = 0;
 911         else {
 912                 ep->has_dma = 1;
 913                 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
 914
 915                 /* channel type P: hw synch (fifo) */
 916                 if (!cpu_is_omap15xx())
 917                         OMAP1_DMA_LCH_CTRL_REG(ep->lch) = 2;
 918         }
 919
 920 just_restart:
 921         /* restart any queue, even if the claim failed  */
 922         restart = !ep->stopped && !list_empty(&ep->queue);
 923
 924         if (status)
 925                 DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
 926                         restart ? " (restart)" : "");
 927         else
 928                 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
 929                         is_in ? 't' : 'r',
 930                         ep->dma_channel - 1, ep->lch,
 931                         restart ? " (restart)" : "");
 932
 933         if (restart) {
 934                 struct omap_req *req;
 935                 req = container_of(ep->queue.next, struct omap_req, queue);
 936                 if (ep->has_dma)
 937                         (is_in ? next_in_dma : next_out_dma)(ep, req);
 938                 else {
 939                         use_ep(ep, UDC_EP_SEL);
 940                         (is_in ? write_fifo : read_fifo)(ep, req);
 941                         deselect_ep();
 942                         if (!is_in) {
 943                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
 944                                 ep->ackwait = 1 + ep->double_buf;
 945                         }
 946                         /* IN: 6 wait states before it'll tx */
 947                 }
 948         }
 949 }
 950
 951 static void dma_channel_release(struct omap_ep *ep)
 952 {
 953         int             shift = 4 * (ep->dma_channel - 1);
 954         u16             mask = 0x0f << shift;
 955         struct omap_req *req;
 956         int             active;
 957
 958         /* abort any active usb transfer request */
 959         if (!list_empty(&ep->queue))
 960                 req = container_of(ep->queue.next, struct omap_req, queue);
 961         else
 962                 req = NULL;
 963
 964         active = ((1 << 7) & OMAP_DMA_CCR_REG(ep->lch)) != 0;
 965
 966         DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
 967                         active ? "active" : "idle",
 968                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
 969                         ep->dma_channel - 1, req);
 970
 971         /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
 972          * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
 973          */
 974
 975         /* wait till current packet DMA finishes, and fifo empties */
 976         if (ep->bEndpointAddress & USB_DIR_IN) {
 977                 UDC_TXDMA_CFG_REG = (UDC_TXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
 978
 979                 if (req) {
 980                         finish_in_dma(ep, req, -ECONNRESET);
 981
 982                         /* clear FIFO; hosts probably won't empty it */
 983                         use_ep(ep, UDC_EP_SEL);
 984                         UDC_CTRL_REG = UDC_CLR_EP;
 985                         deselect_ep();
 986                 }
 987                 while (UDC_TXDMA_CFG_REG & mask)
 988                         udelay(10);
 989         } else {
 990                 UDC_RXDMA_CFG_REG = (UDC_RXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
 991
 992                 /* dma empties the fifo */
 993                 while (UDC_RXDMA_CFG_REG & mask)
 994                         udelay(10);
 995                 if (req)
 996                         finish_out_dma(ep, req, -ECONNRESET, 0);
 997         }
 998         omap_free_dma(ep->lch);
 999         ep->dma_channel = 0;
1000         ep->lch = -1;
1001         /* has_dma still set, till endpoint is fully quiesced */
1002 }
1003
1004
1005 /*-------------------------------------------------------------------------*/
1006
1007 static int
1008 omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
1009 {
1010         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1011         struct omap_req *req = container_of(_req, struct omap_req, req);
1012         struct omap_udc *udc;
1013         unsigned long   flags;
1014         int             is_iso = 0;
1015
1016         /* catch various bogus parameters */
1017         if (!_req || !req->req.complete || !req->req.buf
1018                         || !list_empty(&req->queue)) {
1019                 DBG("%s, bad params\n", __FUNCTION__);
1020                 return -EINVAL;
1021         }
1022         if (!_ep || (!ep->desc && ep->bEndpointAddress)) {
1023                 DBG("%s, bad ep\n", __FUNCTION__);
1024                 return -EINVAL;
1025         }
1026         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
1027                 if (req->req.length > ep->ep.maxpacket)
1028                         return -EMSGSIZE;
1029                 is_iso = 1;
1030         }
1031
1032         /* this isn't bogus, but OMAP DMA isn't the only hardware to
1033          * have a hard time with partial packet reads...  reject it.
1034          */
1035         if (use_dma
1036                         && ep->has_dma
1037                         && ep->bEndpointAddress != 0
1038                         && (ep->bEndpointAddress & USB_DIR_IN) == 0
1039                         && (req->req.length % ep->ep.maxpacket) != 0) {
1040                 DBG("%s, no partial packet OUT reads\n", __FUNCTION__);
1041                 return -EMSGSIZE;
1042         }
1043
1044         udc = ep->udc;
1045         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
1046                 return -ESHUTDOWN;
1047
1048         if (use_dma && ep->has_dma) {
1049                 if (req->req.dma == DMA_ADDR_INVALID) {
1050                         req->req.dma = dma_map_single(
1051                                 ep->udc->gadget.dev.parent,
1052                                 req->req.buf,
1053                                 req->req.length,
1054                                 (ep->bEndpointAddress & USB_DIR_IN)
1055                                         ? DMA_TO_DEVICE
1056                                         : DMA_FROM_DEVICE);
1057                         req->mapped = 1;
1058                 } else {
1059                         dma_sync_single_for_device(
1060                                 ep->udc->gadget.dev.parent,
1061                                 req->req.dma, req->req.length,
1062                                 (ep->bEndpointAddress & USB_DIR_IN)
1063                                         ? DMA_TO_DEVICE
1064                                         : DMA_FROM_DEVICE);
1065                         req->mapped = 0;
1066                 }
1067         }
1068
1069         VDBG("%s queue req %p, len %d buf %p\n",
1070                 ep->ep.name, _req, _req->length, _req->buf);
1071
1072         spin_lock_irqsave(&udc->lock, flags);
1073
1074         req->req.status = -EINPROGRESS;
1075         req->req.actual = 0;
1076
1077         /* maybe kickstart non-iso i/o queues */
1078         if (is_iso)
1079                 UDC_IRQ_EN_REG |= UDC_SOF_IE;
1080         else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
1081                 int     is_in;
1082
1083                 if (ep->bEndpointAddress == 0) {
1084                         if (!udc->ep0_pending || !list_empty (&ep->queue)) {
1085                                 spin_unlock_irqrestore(&udc->lock, flags);
1086                                 return -EL2HLT;
1087                         }
1088
1089                         /* empty DATA stage? */
1090                         is_in = udc->ep0_in;
1091                         if (!req->req.length) {
1092
1093                                 /* chip became CONFIGURED or ADDRESSED
1094                                  * earlier; drivers may already have queued
1095                                  * requests to non-control endpoints
1096                                  */
1097                                 if (udc->ep0_set_config) {
1098                                         u16     irq_en = UDC_IRQ_EN_REG;
1099
1100                                         irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
1101                                         if (!udc->ep0_reset_config)
1102                                                 irq_en |= UDC_EPN_RX_IE
1103                                                         | UDC_EPN_TX_IE;
1104                                         UDC_IRQ_EN_REG = irq_en;
1105                                 }
1106
1107                                 /* STATUS for zero length DATA stages is
1108                                  * always an IN ... even for IN transfers,
1109                                  * a wierd case which seem to stall OMAP.
1110                                  */
1111                                 UDC_EP_NUM_REG = (UDC_EP_SEL|UDC_EP_DIR);
1112                                 UDC_CTRL_REG = UDC_CLR_EP;
1113                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1114                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1115
1116                                 /* cleanup */
1117                                 udc->ep0_pending = 0;
1118                                 done(ep, req, 0);
1119                                 req = NULL;
1120
1121                         /* non-empty DATA stage */
1122                         } else if (is_in) {
1123                                 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1124                         } else {
1125                                 if (udc->ep0_setup)
1126                                         goto irq_wait;
1127                                 UDC_EP_NUM_REG = UDC_EP_SEL;
1128                         }
1129                 } else {
1130                         is_in = ep->bEndpointAddress & USB_DIR_IN;
1131                         if (!ep->has_dma)
1132                                 use_ep(ep, UDC_EP_SEL);
1133                         /* if ISO: SOF IRQs must be enabled/disabled! */
1134                 }
1135
1136                 if (ep->has_dma)
1137                         (is_in ? next_in_dma : next_out_dma)(ep, req);
1138                 else if (req) {
1139                         if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
1140                                 req = NULL;
1141                         deselect_ep();
1142                         if (!is_in) {
1143                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1144                                 ep->ackwait = 1 + ep->double_buf;
1145                         }
1146                         /* IN: 6 wait states before it'll tx */
1147                 }
1148         }
1149
1150 irq_wait:
1151         /* irq handler advances the queue */
1152         if (req != NULL)
1153                 list_add_tail(&req->queue, &ep->queue);
1154         spin_unlock_irqrestore(&udc->lock, flags);
1155
1156         return 0;
1157 }
1158
1159 static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1160 {
1161         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1162         struct omap_req *req;
1163         unsigned long   flags;
1164
1165         if (!_ep || !_req)
1166                 return -EINVAL;
1167
1168         spin_lock_irqsave(&ep->udc->lock, flags);
1169
1170         /* make sure it's actually queued on this endpoint */
1171         list_for_each_entry (req, &ep->queue, queue) {
1172                 if (&req->req == _req)
1173                         break;
1174         }
1175         if (&req->req != _req) {
1176                 spin_unlock_irqrestore(&ep->udc->lock, flags);
1177                 return -EINVAL;
1178         }
1179
1180         if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1181                 int channel = ep->dma_channel;
1182
1183                 /* releasing the channel cancels the request,
1184                  * reclaiming the channel restarts the queue
1185                  */
1186                 dma_channel_release(ep);
1187                 dma_channel_claim(ep, channel);
1188         } else
1189                 done(ep, req, -ECONNRESET);
1190         spin_unlock_irqrestore(&ep->udc->lock, flags);
1191         return 0;
1192 }
1193
1194 /*-------------------------------------------------------------------------*/
1195
1196 static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1197 {
1198         struct omap_ep  *ep = container_of(_ep, struct omap_ep, ep);
1199         unsigned long   flags;
1200         int             status = -EOPNOTSUPP;
1201
1202         spin_lock_irqsave(&ep->udc->lock, flags);
1203
1204         /* just use protocol stalls for ep0; real halts are annoying */
1205         if (ep->bEndpointAddress == 0) {
1206                 if (!ep->udc->ep0_pending)
1207                         status = -EINVAL;
1208                 else if (value) {
1209                         if (ep->udc->ep0_set_config) {
1210                                 WARN("error changing config?\n");
1211                                 UDC_SYSCON2_REG = UDC_CLR_CFG;
1212                         }
1213                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1214                         ep->udc->ep0_pending = 0;
1215                         status = 0;
1216                 } else /* NOP */
1217                         status = 0;
1218
1219         /* otherwise, all active non-ISO endpoints can halt */
1220         } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->desc) {
1221
1222                 /* IN endpoints must already be idle */
1223                 if ((ep->bEndpointAddress & USB_DIR_IN)
1224                                 && !list_empty(&ep->queue)) {
1225                         status = -EAGAIN;
1226                         goto done;
1227                 }
1228
1229                 if (value) {
1230                         int     channel;
1231
1232                         if (use_dma && ep->dma_channel
1233                                         && !list_empty(&ep->queue)) {
1234                                 channel = ep->dma_channel;
1235                                 dma_channel_release(ep);
1236                         } else
1237                                 channel = 0;
1238
1239                         use_ep(ep, UDC_EP_SEL);
1240                         if (UDC_STAT_FLG_REG & UDC_NON_ISO_FIFO_EMPTY) {
1241                                 UDC_CTRL_REG = UDC_SET_HALT;
1242                                 status = 0;
1243                         } else
1244                                 status = -EAGAIN;
1245                         deselect_ep();
1246
1247                         if (channel)
1248                                 dma_channel_claim(ep, channel);
1249                 } else {
1250                         use_ep(ep, 0);
1251                         UDC_CTRL_REG = ep->udc->clr_halt;
1252                         ep->ackwait = 0;
1253                         if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1254                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1255                                 ep->ackwait = 1 + ep->double_buf;
1256                         }
1257                 }
1258         }
1259 done:
1260         VDBG("%s %s halt stat %d\n", ep->ep.name,
1261                 value ? "set" : "clear", status);
1262
1263         spin_unlock_irqrestore(&ep->udc->lock, flags);
1264         return status;
1265 }
1266
1267 static struct usb_ep_ops omap_ep_ops = {
1268         .enable         = omap_ep_enable,
1269         .disable        = omap_ep_disable,
1270
1271         .alloc_request  = omap_alloc_request,
1272         .free_request   = omap_free_request,
1273
1274         .alloc_buffer   = omap_alloc_buffer,
1275         .free_buffer    = omap_free_buffer,
1276
1277         .queue          = omap_ep_queue,
1278         .dequeue        = omap_ep_dequeue,
1279
1280         .set_halt       = omap_ep_set_halt,
1281         // fifo_status ... report bytes in fifo
1282         // fifo_flush ... flush fifo
1283 };
1284
1285 /*-------------------------------------------------------------------------*/
1286
1287 static int omap_get_frame(struct usb_gadget *gadget)
1288 {
1289         u16     sof = UDC_SOF_REG;
1290         return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1291 }
1292
1293 static int omap_wakeup(struct usb_gadget *gadget)
1294 {
1295         struct omap_udc *udc;
1296         unsigned long   flags;
1297         int             retval = -EHOSTUNREACH;
1298
1299         udc = container_of(gadget, struct omap_udc, gadget);
1300
1301         spin_lock_irqsave(&udc->lock, flags);
1302         if (udc->devstat & UDC_SUS) {
1303                 /* NOTE:  OTG spec erratum says that OTG devices may
1304                  * issue wakeups without host enable.
1305                  */
1306                 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1307                         DBG("remote wakeup...\n");
1308                         UDC_SYSCON2_REG = UDC_RMT_WKP;
1309                         retval = 0;
1310                 }
1311
1312         /* NOTE:  non-OTG systems may use SRP TOO... */
1313         } else if (!(udc->devstat & UDC_ATT)) {
1314                 if (udc->transceiver)
1315                         retval = otg_start_srp(udc->transceiver);
1316         }
1317         spin_unlock_irqrestore(&udc->lock, flags);
1318
1319         return retval;
1320 }
1321
1322 static int
1323 omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1324 {
1325         struct omap_udc *udc;
1326         unsigned long   flags;
1327         u16             syscon1;
1328
1329         udc = container_of(gadget, struct omap_udc, gadget);
1330         spin_lock_irqsave(&udc->lock, flags);
1331         syscon1 = UDC_SYSCON1_REG;
1332         if (is_selfpowered)
1333                 syscon1 |= UDC_SELF_PWR;
1334         else
1335                 syscon1 &= ~UDC_SELF_PWR;
1336         UDC_SYSCON1_REG = syscon1;
1337         spin_unlock_irqrestore(&udc->lock, flags);
1338
1339         return 0;
1340 }
1341
1342 static int can_pullup(struct omap_udc *udc)
1343 {
1344         return udc->driver && udc->softconnect && udc->vbus_active;
1345 }
1346
1347 static void pullup_enable(struct omap_udc *udc)
1348 {
1349         udc->gadget.dev.parent->power.power_state = PMSG_ON;
1350         udc->gadget.dev.power.power_state = PMSG_ON;
1351         UDC_SYSCON1_REG |= UDC_PULLUP_EN;
1352 #ifndef CONFIG_USB_OTG
1353         if (!cpu_is_omap15xx())
1354                 OTG_CTRL_REG |= OTG_BSESSVLD;
1355 #endif
1356         UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
1357 }
1358
1359 static void pullup_disable(struct omap_udc *udc)
1360 {
1361 #ifndef CONFIG_USB_OTG
1362         if (!cpu_is_omap15xx())
1363                 OTG_CTRL_REG &= ~OTG_BSESSVLD;
1364 #endif
1365         UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
1366         UDC_SYSCON1_REG &= ~UDC_PULLUP_EN;
1367 }
1368
1369 static struct omap_udc *udc;
1370
1371 static void omap_udc_enable_clock(int enable)
1372 {
1373         if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL)
1374                 return;
1375
1376         if (enable) {
1377                 clk_enable(udc->dc_clk);
1378                 clk_enable(udc->hhc_clk);
1379                 udelay(100);
1380         } else {
1381                 clk_disable(udc->hhc_clk);
1382                 clk_disable(udc->dc_clk);
1383         }
1384 }
1385
1386 /*
1387  * Called by whatever detects VBUS sessions:  external transceiver
1388  * driver, or maybe GPIO0 VBUS IRQ.  May request 48 MHz clock.
1389  */
1390 static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1391 {
1392         struct omap_udc *udc;
1393         unsigned long   flags;
1394
1395         udc = container_of(gadget, struct omap_udc, gadget);
1396         spin_lock_irqsave(&udc->lock, flags);
1397         VDBG("VBUS %s\n", is_active ? "on" : "off");
1398         udc->vbus_active = (is_active != 0);
1399         if (cpu_is_omap15xx()) {
1400                 /* "software" detect, ignored if !VBUS_MODE_1510 */
1401                 if (is_active)
1402                         FUNC_MUX_CTRL_0_REG |= VBUS_CTRL_1510;
1403                 else
1404                         FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
1405         }
1406         if (udc->dc_clk != NULL && is_active) {
1407                 if (!udc->clk_requested) {
1408                         omap_udc_enable_clock(1);
1409                         udc->clk_requested = 1;
1410                 }
1411         }
1412         if (can_pullup(udc))
1413                 pullup_enable(udc);
1414         else
1415                 pullup_disable(udc);
1416         if (udc->dc_clk != NULL && !is_active) {
1417                 if (udc->clk_requested) {
1418                         omap_udc_enable_clock(0);
1419                         udc->clk_requested = 0;
1420                 }
1421         }
1422         spin_unlock_irqrestore(&udc->lock, flags);
1423         return 0;
1424 }
1425
1426 static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1427 {
1428         struct omap_udc *udc;
1429
1430         udc = container_of(gadget, struct omap_udc, gadget);
1431         if (udc->transceiver)
1432                 return otg_set_power(udc->transceiver, mA);
1433         return -EOPNOTSUPP;
1434 }
1435
1436 static int omap_pullup(struct usb_gadget *gadget, int is_on)
1437 {
1438         struct omap_udc *udc;
1439         unsigned long   flags;
1440
1441         udc = container_of(gadget, struct omap_udc, gadget);
1442         spin_lock_irqsave(&udc->lock, flags);
1443         udc->softconnect = (is_on != 0);
1444         if (can_pullup(udc))
1445                 pullup_enable(udc);
1446         else
1447                 pullup_disable(udc);
1448         spin_unlock_irqrestore(&udc->lock, flags);
1449         return 0;
1450 }
1451
1452 static struct usb_gadget_ops omap_gadget_ops = {
1453         .get_frame              = omap_get_frame,
1454         .wakeup                 = omap_wakeup,
1455         .set_selfpowered        = omap_set_selfpowered,
1456         .vbus_session           = omap_vbus_session,
1457         .vbus_draw              = omap_vbus_draw,
1458         .pullup                 = omap_pullup,
1459 };
1460
1461 /*-------------------------------------------------------------------------*/
1462
1463 /* dequeue ALL requests; caller holds udc->lock */
1464 static void nuke(struct omap_ep *ep, int status)
1465 {
1466         struct omap_req *req;
1467
1468         ep->stopped = 1;
1469
1470         if (use_dma && ep->dma_channel)
1471                 dma_channel_release(ep);
1472
1473         use_ep(ep, 0);
1474         UDC_CTRL_REG = UDC_CLR_EP;
1475         if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
1476                 UDC_CTRL_REG = UDC_SET_HALT;
1477
1478         while (!list_empty(&ep->queue)) {
1479                 req = list_entry(ep->queue.next, struct omap_req, queue);
1480                 done(ep, req, status);
1481         }
1482 }
1483
1484 /* caller holds udc->lock */
1485 static void udc_quiesce(struct omap_udc *udc)
1486 {
1487         struct omap_ep  *ep;
1488
1489         udc->gadget.speed = USB_SPEED_UNKNOWN;
1490         nuke(&udc->ep[0], -ESHUTDOWN);
1491         list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list)
1492                 nuke(ep, -ESHUTDOWN);
1493 }
1494
1495 /*-------------------------------------------------------------------------*/
1496
1497 static void update_otg(struct omap_udc *udc)
1498 {
1499         u16     devstat;
1500
1501         if (!udc->gadget.is_otg)
1502                 return;
1503
1504         if (OTG_CTRL_REG & OTG_ID)
1505                 devstat = UDC_DEVSTAT_REG;
1506         else
1507                 devstat = 0;
1508
1509         udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1510         udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1511         udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1512
1513         /* Enable HNP early, avoiding races on suspend irq path.
1514          * ASSUMES OTG state machine B_BUS_REQ input is true.
1515          */
1516         if (udc->gadget.b_hnp_enable)
1517                 OTG_CTRL_REG = (OTG_CTRL_REG | OTG_B_HNPEN | OTG_B_BUSREQ)
1518                                 & ~OTG_PULLUP;
1519 }
1520
1521 static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1522 {
1523         struct omap_ep  *ep0 = &udc->ep[0];
1524         struct omap_req *req = NULL;
1525
1526         ep0->irqs++;
1527
1528         /* Clear any pending requests and then scrub any rx/tx state
1529          * before starting to handle the SETUP request.
1530          */
1531         if (irq_src & UDC_SETUP) {
1532                 u16     ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1533
1534                 nuke(ep0, 0);
1535                 if (ack) {
1536                         UDC_IRQ_SRC_REG = ack;
1537                         irq_src = UDC_SETUP;
1538                 }
1539         }
1540
1541         /* IN/OUT packets mean we're in the DATA or STATUS stage.
1542          * This driver uses only uses protocol stalls (ep0 never halts),
1543          * and if we got this far the gadget driver already had a
1544          * chance to stall.  Tries to be forgiving of host oddities.
1545          *
1546          * NOTE:  the last chance gadget drivers have to stall control
1547          * requests is during their request completion callback.
1548          */
1549         if (!list_empty(&ep0->queue))
1550                 req = container_of(ep0->queue.next, struct omap_req, queue);
1551
1552         /* IN == TX to host */
1553         if (irq_src & UDC_EP0_TX) {
1554                 int     stat;
1555
1556                 UDC_IRQ_SRC_REG = UDC_EP0_TX;
1557                 UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1558                 stat = UDC_STAT_FLG_REG;
1559                 if (stat & UDC_ACK) {
1560                         if (udc->ep0_in) {
1561                                 /* write next IN packet from response,
1562                                  * or set up the status stage.
1563                                  */
1564                                 if (req)
1565                                         stat = write_fifo(ep0, req);
1566                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1567                                 if (!req && udc->ep0_pending) {
1568                                         UDC_EP_NUM_REG = UDC_EP_SEL;
1569                                         UDC_CTRL_REG = UDC_CLR_EP;
1570                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1571                                         UDC_EP_NUM_REG = 0;
1572                                         udc->ep0_pending = 0;
1573                                 } /* else:  6 wait states before it'll tx */
1574                         } else {
1575                                 /* ack status stage of OUT transfer */
1576                                 UDC_EP_NUM_REG = UDC_EP_DIR;
1577                                 if (req)
1578                                         done(ep0, req, 0);
1579                         }
1580                         req = NULL;
1581                 } else if (stat & UDC_STALL) {
1582                         UDC_CTRL_REG = UDC_CLR_HALT;
1583                         UDC_EP_NUM_REG = UDC_EP_DIR;
1584                 } else {
1585                         UDC_EP_NUM_REG = UDC_EP_DIR;
1586                 }
1587         }
1588
1589         /* OUT == RX from host */
1590         if (irq_src & UDC_EP0_RX) {
1591                 int     stat;
1592
1593                 UDC_IRQ_SRC_REG = UDC_EP0_RX;
1594                 UDC_EP_NUM_REG = UDC_EP_SEL;
1595                 stat = UDC_STAT_FLG_REG;
1596                 if (stat & UDC_ACK) {
1597                         if (!udc->ep0_in) {
1598                                 stat = 0;
1599                                 /* read next OUT packet of request, maybe
1600                                  * reactiviting the fifo; stall on errors.
1601                                  */
1602                                 if (!req || (stat = read_fifo(ep0, req)) < 0) {
1603                                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1604                                         udc->ep0_pending = 0;
1605                                         stat = 0;
1606                                 } else if (stat == 0)
1607                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1608                                 UDC_EP_NUM_REG = 0;
1609
1610                                 /* activate status stage */
1611                                 if (stat == 1) {
1612                                         done(ep0, req, 0);
1613                                         /* that may have STALLed ep0... */
1614                                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1615                                         UDC_CTRL_REG = UDC_CLR_EP;
1616                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1617                                         UDC_EP_NUM_REG = UDC_EP_DIR;
1618                                         udc->ep0_pending = 0;
1619                                 }
1620                         } else {
1621                                 /* ack status stage of IN transfer */
1622                                 UDC_EP_NUM_REG = 0;
1623                                 if (req)
1624                                         done(ep0, req, 0);
1625                         }
1626                 } else if (stat & UDC_STALL) {
1627                         UDC_CTRL_REG = UDC_CLR_HALT;
1628                         UDC_EP_NUM_REG = 0;
1629                 } else {
1630                         UDC_EP_NUM_REG = 0;
1631                 }
1632         }
1633
1634         /* SETUP starts all control transfers */
1635         if (irq_src & UDC_SETUP) {
1636                 union u {
1637                         u16                     word[4];
1638                         struct usb_ctrlrequest  r;
1639                 } u;
1640                 int                     status = -EINVAL;
1641                 struct omap_ep          *ep;
1642
1643                 /* read the (latest) SETUP message */
1644                 do {
1645                         UDC_EP_NUM_REG = UDC_SETUP_SEL;
1646                         /* two bytes at a time */
1647                         u.word[0] = UDC_DATA_REG;
1648                         u.word[1] = UDC_DATA_REG;
1649                         u.word[2] = UDC_DATA_REG;
1650                         u.word[3] = UDC_DATA_REG;
1651                         UDC_EP_NUM_REG = 0;
1652                 } while (UDC_IRQ_SRC_REG & UDC_SETUP);
1653
1654 #define w_value         le16_to_cpu(u.r.wValue)
1655 #define w_index         le16_to_cpu(u.r.wIndex)
1656 #define w_length        le16_to_cpu(u.r.wLength)
1657
1658                 /* Delegate almost all control requests to the gadget driver,
1659                  * except for a handful of ch9 status/feature requests that
1660                  * hardware doesn't autodecode _and_ the gadget API hides.
1661                  */
1662                 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1663                 udc->ep0_set_config = 0;
1664                 udc->ep0_pending = 1;
1665                 ep0->stopped = 0;
1666                 ep0->ackwait = 0;
1667                 switch (u.r.bRequest) {
1668                 case USB_REQ_SET_CONFIGURATION:
1669                         /* udc needs to know when ep != 0 is valid */
1670                         if (u.r.bRequestType != USB_RECIP_DEVICE)
1671                                 goto delegate;
1672                         if (w_length != 0)
1673                                 goto do_stall;
1674                         udc->ep0_set_config = 1;
1675                         udc->ep0_reset_config = (w_value == 0);
1676                         VDBG("set config %d\n", w_value);
1677
1678                         /* update udc NOW since gadget driver may start
1679                          * queueing requests immediately; clear config
1680                          * later if it fails the request.
1681                          */
1682                         if (udc->ep0_reset_config)
1683                                 UDC_SYSCON2_REG = UDC_CLR_CFG;
1684                         else
1685                                 UDC_SYSCON2_REG = UDC_DEV_CFG;
1686                         update_otg(udc);
1687                         goto delegate;
1688                 case USB_REQ_CLEAR_FEATURE:
1689                         /* clear endpoint halt */
1690                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1691                                 goto delegate;
1692                         if (w_value != USB_ENDPOINT_HALT
1693                                         || w_length != 0)
1694                                 goto do_stall;
1695                         ep = &udc->ep[w_index & 0xf];
1696                         if (ep != ep0) {
1697                                 if (w_index & USB_DIR_IN)
1698                                         ep += 16;
1699                                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1700                                                 || !ep->desc)
1701                                         goto do_stall;
1702                                 use_ep(ep, 0);
1703                                 UDC_CTRL_REG = udc->clr_halt;
1704                                 ep->ackwait = 0;
1705                                 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1706                                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1707                                         ep->ackwait = 1 + ep->double_buf;
1708                                 }
1709                                 /* NOTE:  assumes the host behaves sanely,
1710                                  * only clearing real halts.  Else we may
1711                                  * need to kill pending transfers and then
1712                                  * restart the queue... very messy for DMA!
1713                                  */
1714                         }
1715                         VDBG("%s halt cleared by host\n", ep->name);
1716                         goto ep0out_status_stage;
1717                 case USB_REQ_SET_FEATURE:
1718                         /* set endpoint halt */
1719                         if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1720                                 goto delegate;
1721                         if (w_value != USB_ENDPOINT_HALT
1722                                         || w_length != 0)
1723                                 goto do_stall;
1724                         ep = &udc->ep[w_index & 0xf];
1725                         if (w_index & USB_DIR_IN)
1726                                 ep += 16;
1727                         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1728                                         || ep == ep0 || !ep->desc)
1729                                 goto do_stall;
1730                         if (use_dma && ep->has_dma) {
1731                                 /* this has rude side-effects (aborts) and
1732                                  * can't really work if DMA-IN is active
1733                                  */
1734                                 DBG("%s host set_halt, NYET \n", ep->name);
1735                                 goto do_stall;
1736                         }
1737                         use_ep(ep, 0);
1738                         /* can't halt if fifo isn't empty... */
1739                         UDC_CTRL_REG = UDC_CLR_EP;
1740                         UDC_CTRL_REG = UDC_SET_HALT;
1741                         VDBG("%s halted by host\n", ep->name);
1742 ep0out_status_stage:
1743                         status = 0;
1744                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1745                         UDC_CTRL_REG = UDC_CLR_EP;
1746                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1747                         UDC_EP_NUM_REG = UDC_EP_DIR;
1748                         udc->ep0_pending = 0;
1749                         break;
1750                 case USB_REQ_GET_STATUS:
1751                         /* USB_ENDPOINT_HALT status? */
1752                         if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT))
1753                                 goto intf_status;
1754
1755                         /* ep0 never stalls */
1756                         if (!(w_index & 0xf))
1757                                 goto zero_status;
1758
1759                         /* only active endpoints count */
1760                         ep = &udc->ep[w_index & 0xf];
1761                         if (w_index & USB_DIR_IN)
1762                                 ep += 16;
1763                         if (!ep->desc)
1764                                 goto do_stall;
1765
1766                         /* iso never stalls */
1767                         if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1768                                 goto zero_status;
1769
1770                         /* FIXME don't assume non-halted endpoints!! */
1771                         ERR("%s status, can't report\n", ep->ep.name);
1772                         goto do_stall;
1773
1774 intf_status:
1775                         /* return interface status.  if we were pedantic,
1776                          * we'd detect non-existent interfaces, and stall.
1777                          */
1778                         if (u.r.bRequestType
1779                                         != (USB_DIR_IN|USB_RECIP_INTERFACE))
1780                                 goto delegate;
1781
1782 zero_status:
1783                         /* return two zero bytes */
1784                         UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
1785                         UDC_DATA_REG = 0;
1786                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
1787                         UDC_EP_NUM_REG = UDC_EP_DIR;
1788                         status = 0;
1789                         VDBG("GET_STATUS, interface %d\n", w_index);
1790                         /* next, status stage */
1791                         break;
1792                 default:
1793 delegate:
1794                         /* activate the ep0out fifo right away */
1795                         if (!udc->ep0_in && w_length) {
1796                                 UDC_EP_NUM_REG = 0;
1797                                 UDC_CTRL_REG = UDC_SET_FIFO_EN;
1798                         }
1799
1800                         /* gadget drivers see class/vendor specific requests,
1801                          * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1802                          * and more
1803                          */
1804                         VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1805                                 u.r.bRequestType, u.r.bRequest,
1806                                 w_value, w_index, w_length);
1807
1808 #undef  w_value
1809 #undef  w_index
1810 #undef  w_length
1811
1812                         /* The gadget driver may return an error here,
1813                          * causing an immediate protocol stall.
1814                          *
1815                          * Else it must issue a response, either queueing a
1816                          * response buffer for the DATA stage, or halting ep0
1817                          * (causing a protocol stall, not a real halt).  A
1818                          * zero length buffer means no DATA stage.
1819                          *
1820                          * It's fine to issue that response after the setup()
1821                          * call returns, and this IRQ was handled.
1822                          */
1823                         udc->ep0_setup = 1;
1824                         spin_unlock(&udc->lock);
1825                         status = udc->driver->setup (&udc->gadget, &u.r);
1826                         spin_lock(&udc->lock);
1827                         udc->ep0_setup = 0;
1828                 }
1829
1830                 if (status < 0) {
1831 do_stall:
1832                         VDBG("req %02x.%02x protocol STALL; stat %d\n",
1833                                         u.r.bRequestType, u.r.bRequest, status);
1834                         if (udc->ep0_set_config) {
1835                                 if (udc->ep0_reset_config)
1836                                         WARN("error resetting config?\n");
1837                                 else
1838                                         UDC_SYSCON2_REG = UDC_CLR_CFG;
1839                         }
1840                         UDC_SYSCON2_REG = UDC_STALL_CMD;
1841                         udc->ep0_pending = 0;
1842                 }
1843         }
1844 }
1845
1846 /*-------------------------------------------------------------------------*/
1847
1848 #define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1849
1850 static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1851 {
1852         u16     devstat, change;
1853
1854         devstat = UDC_DEVSTAT_REG;
1855         change = devstat ^ udc->devstat;
1856         udc->devstat = devstat;
1857
1858         if (change & (UDC_USB_RESET|UDC_ATT)) {
1859                 udc_quiesce(udc);
1860
1861                 if (change & UDC_ATT) {
1862                         /* driver for any external transceiver will
1863                          * have called omap_vbus_session() already
1864                          */
1865                         if (devstat & UDC_ATT) {
1866                                 udc->gadget.speed = USB_SPEED_FULL;
1867                                 VDBG("connect\n");
1868                                 if (!udc->transceiver)
1869                                         pullup_enable(udc);
1870                                 // if (driver->connect) call it
1871                         } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1872                                 udc->gadget.speed = USB_SPEED_UNKNOWN;
1873                                 if (!udc->transceiver)
1874                                         pullup_disable(udc);
1875                                 DBG("disconnect, gadget %s\n",
1876                                         udc->driver->driver.name);
1877                                 if (udc->driver->disconnect) {
1878                                         spin_unlock(&udc->lock);
1879                                         udc->driver->disconnect(&udc->gadget);
1880                                         spin_lock(&udc->lock);
1881                                 }
1882                         }
1883                         change &= ~UDC_ATT;
1884                 }
1885
1886                 if (change & UDC_USB_RESET) {
1887                         if (devstat & UDC_USB_RESET) {
1888                                 VDBG("RESET=1\n");
1889                         } else {
1890                                 udc->gadget.speed = USB_SPEED_FULL;
1891                                 INFO("USB reset done, gadget %s\n",
1892                                         udc->driver->driver.name);
1893                                 /* ep0 traffic is legal from now on */
1894                                 UDC_IRQ_EN_REG = UDC_DS_CHG_IE | UDC_EP0_IE;
1895                         }
1896                         change &= ~UDC_USB_RESET;
1897                 }
1898         }
1899         if (change & UDC_SUS) {
1900                 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1901                         // FIXME tell isp1301 to suspend/resume (?)
1902                         if (devstat & UDC_SUS) {
1903                                 VDBG("suspend\n");
1904                                 update_otg(udc);
1905                                 /* HNP could be under way already */
1906                                 if (udc->gadget.speed == USB_SPEED_FULL
1907                                                 && udc->driver->suspend) {
1908                                         spin_unlock(&udc->lock);
1909                                         udc->driver->suspend(&udc->gadget);
1910                                         spin_lock(&udc->lock);
1911                                 }
1912                                 if (udc->transceiver)
1913                                         otg_set_suspend(udc->transceiver, 1);
1914                         } else {
1915                                 VDBG("resume\n");
1916                                 if (udc->transceiver)
1917                                         otg_set_suspend(udc->transceiver, 0);
1918                                 if (udc->gadget.speed == USB_SPEED_FULL
1919                                                 && udc->driver->resume) {
1920                                         spin_unlock(&udc->lock);
1921                                         udc->driver->resume(&udc->gadget);
1922                                         spin_lock(&udc->lock);
1923                                 }
1924                         }
1925                 }
1926                 change &= ~UDC_SUS;
1927         }
1928         if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1929                 update_otg(udc);
1930                 change &= ~OTG_FLAGS;
1931         }
1932
1933         change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1934         if (change)
1935                 VDBG("devstat %03x, ignore change %03x\n",
1936                         devstat,  change);
1937
1938         UDC_IRQ_SRC_REG = UDC_DS_CHG;
1939 }
1940
1941 static irqreturn_t omap_udc_irq(int irq, void *_udc)
1942 {
1943         struct omap_udc *udc = _udc;
1944         u16             irq_src;
1945         irqreturn_t     status = IRQ_NONE;
1946         unsigned long   flags;
1947
1948         spin_lock_irqsave(&udc->lock, flags);
1949         irq_src = UDC_IRQ_SRC_REG;
1950
1951         /* Device state change (usb ch9 stuff) */
1952         if (irq_src & UDC_DS_CHG) {
1953                 devstate_irq(_udc, irq_src);
1954                 status = IRQ_HANDLED;
1955                 irq_src &= ~UDC_DS_CHG;
1956         }
1957
1958         /* EP0 control transfers */
1959         if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1960                 ep0_irq(_udc, irq_src);
1961                 status = IRQ_HANDLED;
1962                 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1963         }
1964
1965         /* DMA transfer completion */
1966         if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1967                 dma_irq(_udc, irq_src);
1968                 status = IRQ_HANDLED;
1969                 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1970         }
1971
1972         irq_src &= ~(UDC_SOF|UDC_EPN_TX|UDC_EPN_RX);
1973         if (irq_src)
1974                 DBG("udc_irq, unhandled %03x\n", irq_src);
1975         spin_unlock_irqrestore(&udc->lock, flags);
1976
1977         return status;
1978 }
1979
1980 /* workaround for seemingly-lost IRQs for RX ACKs... */
1981 #define PIO_OUT_TIMEOUT (jiffies + HZ/3)
1982 #define HALF_FULL(f)    (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1983
1984 static void pio_out_timer(unsigned long _ep)
1985 {
1986         struct omap_ep  *ep = (void *) _ep;
1987         unsigned long   flags;
1988         u16             stat_flg;
1989
1990         spin_lock_irqsave(&ep->udc->lock, flags);
1991         if (!list_empty(&ep->queue) && ep->ackwait) {
1992                 use_ep(ep, UDC_EP_SEL);
1993                 stat_flg = UDC_STAT_FLG_REG;
1994
1995                 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1996                                 || (ep->double_buf && HALF_FULL(stat_flg)))) {
1997                         struct omap_req *req;
1998
1999                         VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
2000                         req = container_of(ep->queue.next,
2001                                         struct omap_req, queue);
2002                         (void) read_fifo(ep, req);
2003                         UDC_EP_NUM_REG = ep->bEndpointAddress;
2004                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
2005                         ep->ackwait = 1 + ep->double_buf;
2006                 } else
2007                         deselect_ep();
2008         }
2009         mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
2010         spin_unlock_irqrestore(&ep->udc->lock, flags);
2011 }
2012
2013 static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
2014 {
2015         u16             epn_stat, irq_src;
2016         irqreturn_t     status = IRQ_NONE;
2017         struct omap_ep  *ep;
2018         int             epnum;
2019         struct omap_udc *udc = _dev;
2020         struct omap_req *req;
2021         unsigned long   flags;
2022
2023         spin_lock_irqsave(&udc->lock, flags);
2024         epn_stat = UDC_EPN_STAT_REG;
2025         irq_src = UDC_IRQ_SRC_REG;
2026
2027         /* handle OUT first, to avoid some wasteful NAKs */
2028         if (irq_src & UDC_EPN_RX) {
2029                 epnum = (epn_stat >> 8) & 0x0f;
2030                 UDC_IRQ_SRC_REG = UDC_EPN_RX;
2031                 status = IRQ_HANDLED;
2032                 ep = &udc->ep[epnum];
2033                 ep->irqs++;
2034
2035                 UDC_EP_NUM_REG = epnum | UDC_EP_SEL;
2036                 ep->fnf = 0;
2037                 if ((UDC_STAT_FLG_REG & UDC_ACK)) {
2038                         ep->ackwait--;
2039                         if (!list_empty(&ep->queue)) {
2040                                 int stat;
2041                                 req = container_of(ep->queue.next,
2042                                                 struct omap_req, queue);
2043                                 stat = read_fifo(ep, req);
2044                                 if (!ep->double_buf)
2045                                         ep->fnf = 1;
2046                         }
2047                 }
2048                 /* min 6 clock delay before clearing EP_SEL ... */
2049                 epn_stat = UDC_EPN_STAT_REG;
2050                 epn_stat = UDC_EPN_STAT_REG;
2051                 UDC_EP_NUM_REG = epnum;
2052
2053                 /* enabling fifo _after_ clearing ACK, contrary to docs,
2054                  * reduces lossage; timer still needed though (sigh).
2055                  */
2056                 if (ep->fnf) {
2057                         UDC_CTRL_REG = UDC_SET_FIFO_EN;
2058                         ep->ackwait = 1 + ep->double_buf;
2059                 }
2060                 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
2061         }
2062
2063         /* then IN transfers */
2064         else if (irq_src & UDC_EPN_TX) {
2065                 epnum = epn_stat & 0x0f;
2066                 UDC_IRQ_SRC_REG = UDC_EPN_TX;
2067                 status = IRQ_HANDLED;
2068                 ep = &udc->ep[16 + epnum];
2069                 ep->irqs++;
2070
2071                 UDC_EP_NUM_REG = epnum | UDC_EP_DIR | UDC_EP_SEL;
2072                 if ((UDC_STAT_FLG_REG & UDC_ACK)) {
2073                         ep->ackwait = 0;
2074                         if (!list_empty(&ep->queue)) {
2075                                 req = container_of(ep->queue.next,
2076                                                 struct omap_req, queue);
2077                                 (void) write_fifo(ep, req);
2078                         }
2079                 }
2080                 /* min 6 clock delay before clearing EP_SEL ... */
2081                 epn_stat = UDC_EPN_STAT_REG;
2082                 epn_stat = UDC_EPN_STAT_REG;
2083                 UDC_EP_NUM_REG = epnum | UDC_EP_DIR;
2084                 /* then 6 clocks before it'd tx */
2085         }
2086
2087         spin_unlock_irqrestore(&udc->lock, flags);
2088         return status;
2089 }
2090
2091 #ifdef  USE_ISO
2092 static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
2093 {
2094         struct omap_udc *udc = _dev;
2095         struct omap_ep  *ep;
2096         int             pending = 0;
2097         unsigned long   flags;
2098
2099         spin_lock_irqsave(&udc->lock, flags);
2100
2101         /* handle all non-DMA ISO transfers */
2102         list_for_each_entry (ep, &udc->iso, iso) {
2103                 u16             stat;
2104                 struct omap_req *req;
2105
2106                 if (ep->has_dma || list_empty(&ep->queue))
2107                         continue;
2108                 req = list_entry(ep->queue.next, struct omap_req, queue);
2109
2110                 use_ep(ep, UDC_EP_SEL);
2111                 stat = UDC_STAT_FLG_REG;
2112
2113                 /* NOTE: like the other controller drivers, this isn't
2114                  * currently reporting lost or damaged frames.
2115                  */
2116                 if (ep->bEndpointAddress & USB_DIR_IN) {
2117                         if (stat & UDC_MISS_IN)
2118                                 /* done(ep, req, -EPROTO) */;
2119                         else
2120                                 write_fifo(ep, req);
2121                 } else {
2122                         int     status = 0;
2123
2124                         if (stat & UDC_NO_RXPACKET)
2125                                 status = -EREMOTEIO;
2126                         else if (stat & UDC_ISO_ERR)
2127                                 status = -EILSEQ;
2128                         else if (stat & UDC_DATA_FLUSH)
2129                                 status = -ENOSR;
2130
2131                         if (status)
2132                                 /* done(ep, req, status) */;
2133                         else
2134                                 read_fifo(ep, req);
2135                 }
2136                 deselect_ep();
2137                 /* 6 wait states before next EP */
2138
2139                 ep->irqs++;
2140                 if (!list_empty(&ep->queue))
2141                         pending = 1;
2142         }
2143         if (!pending)
2144                 UDC_IRQ_EN_REG &= ~UDC_SOF_IE;
2145         UDC_IRQ_SRC_REG = UDC_SOF;
2146
2147         spin_unlock_irqrestore(&udc->lock, flags);
2148         return IRQ_HANDLED;
2149 }
2150 #endif
2151
2152 /*-------------------------------------------------------------------------*/
2153
2154 static inline int machine_without_vbus_sense(void)
2155 {
2156         return (machine_is_omap_innovator()
2157                 || machine_is_omap_osk()
2158                 || machine_is_omap_apollon()
2159 #ifndef CONFIG_MACH_OMAP_H4_OTG
2160                 || machine_is_omap_h4()
2161 #endif
2162                 || machine_is_sx1()
2163                 );
2164 }
2165
2166 int usb_gadget_register_driver (struct usb_gadget_driver *driver)
2167 {
2168         int             status = -ENODEV;
2169         struct omap_ep  *ep;
2170         unsigned long   flags;
2171
2172         /* basic sanity tests */
2173         if (!udc)
2174                 return -ENODEV;
2175         if (!driver
2176                         // FIXME if otg, check:  driver->is_otg
2177                         || driver->speed < USB_SPEED_FULL
2178                         || !driver->bind
2179                         || !driver->setup)
2180                 return -EINVAL;
2181
2182         spin_lock_irqsave(&udc->lock, flags);
2183         if (udc->driver) {
2184                 spin_unlock_irqrestore(&udc->lock, flags);
2185                 return -EBUSY;
2186         }
2187
2188         /* reset state */
2189         list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
2190                 ep->irqs = 0;
2191                 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2192                         continue;
2193                 use_ep(ep, 0);
2194                 UDC_CTRL_REG = UDC_SET_HALT;
2195         }
2196         udc->ep0_pending = 0;
2197         udc->ep[0].irqs = 0;
2198         udc->softconnect = 1;
2199
2200         /* hook up the driver */
2201         driver->driver.bus = NULL;
2202         udc->driver = driver;
2203         udc->gadget.dev.driver = &driver->driver;
2204         spin_unlock_irqrestore(&udc->lock, flags);
2205
2206         if (udc->dc_clk != NULL)
2207                 omap_udc_enable_clock(1);
2208
2209         status = driver->bind (&udc->gadget);
2210         if (status) {
2211                 DBG("bind to %s --> %d\n", driver->driver.name, status);
2212                 udc->gadget.dev.driver = NULL;
2213                 udc->driver = NULL;
2214                 goto done;
2215         }
2216         DBG("bound to driver %s\n", driver->driver.name);
2217
2218         UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
2219
2220         /* connect to bus through transceiver */
2221         if (udc->transceiver) {
2222                 status = otg_set_peripheral(udc->transceiver, &udc->gadget);
2223                 if (status < 0) {
2224                         ERR("can't bind to transceiver\n");
2225                         if (driver->unbind) {
2226                                 driver->unbind (&udc->gadget);
2227                                 udc->gadget.dev.driver = NULL;
2228                                 udc->driver = NULL;
2229                         }
2230                         goto done;
2231                 }
2232         } else {
2233                 if (can_pullup(udc))
2234                         pullup_enable (udc);
2235                 else
2236                         pullup_disable (udc);
2237         }
2238
2239         /* boards that don't have VBUS sensing can't autogate 48MHz;
2240          * can't enter deep sleep while a gadget driver is active.
2241          */
2242         if (machine_without_vbus_sense())
2243                 omap_vbus_session(&udc->gadget, 1);
2244
2245 done:
2246         if (udc->dc_clk != NULL)
2247                 omap_udc_enable_clock(0);
2248         return status;
2249 }
2250 EXPORT_SYMBOL(usb_gadget_register_driver);
2251
2252 int usb_gadget_unregister_driver (struct usb_gadget_driver *driver)
2253 {
2254         unsigned long   flags;
2255         int             status = -ENODEV;
2256
2257         if (!udc)
2258                 return -ENODEV;
2259         if (!driver || driver != udc->driver || !driver->unbind)
2260                 return -EINVAL;
2261
2262         if (udc->dc_clk != NULL)
2263                 omap_udc_enable_clock(1);
2264
2265         if (machine_without_vbus_sense())
2266                 omap_vbus_session(&udc->gadget, 0);
2267
2268         if (udc->transceiver)
2269                 (void) otg_set_peripheral(udc->transceiver, NULL);
2270         else
2271                 pullup_disable(udc);
2272
2273         spin_lock_irqsave(&udc->lock, flags);
2274         udc_quiesce(udc);
2275         spin_unlock_irqrestore(&udc->lock, flags);
2276
2277         driver->unbind(&udc->gadget);
2278         udc->gadget.dev.driver = NULL;
2279         udc->driver = NULL;
2280
2281         if (udc->dc_clk != NULL)
2282                 omap_udc_enable_clock(0);
2283         DBG("unregistered driver '%s'\n", driver->driver.name);
2284         return status;
2285 }
2286 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2287
2288
2289 /*-------------------------------------------------------------------------*/
2290
2291 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2292
2293 #include <linux/seq_file.h>
2294
2295 static const char proc_filename[] = "driver/udc";
2296
2297 #define FOURBITS "%s%s%s%s"
2298 #define EIGHTBITS FOURBITS FOURBITS
2299
2300 static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2301 {
2302         u16             stat_flg;
2303         struct omap_req *req;
2304         char            buf[20];
2305
2306         use_ep(ep, 0);
2307
2308         if (use_dma && ep->has_dma)
2309                 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2310                         (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2311                         ep->dma_channel - 1, ep->lch);
2312         else
2313                 buf[0] = 0;
2314
2315         stat_flg = UDC_STAT_FLG_REG;
2316         seq_printf(s,
2317                 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2318                 ep->name, buf,
2319                 ep->double_buf ? "dbuf " : "",
2320                 ({char *s; switch(ep->ackwait){
2321                 case 0: s = ""; break;
2322                 case 1: s = "(ackw) "; break;
2323                 case 2: s = "(ackw2) "; break;
2324                 default: s = "(?) "; break;
2325                 } s;}),
2326                 ep->irqs, stat_flg,
2327                 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2328                 (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2329                 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2330                 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2331                 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2332                 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2333                 (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2334                 (stat_flg & UDC_STALL) ? "STALL " : "",
2335                 (stat_flg & UDC_NAK) ? "NAK " : "",
2336                 (stat_flg & UDC_ACK) ? "ACK " : "",
2337                 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2338                 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2339                 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2340
2341         if (list_empty (&ep->queue))
2342                 seq_printf(s, "\t(queue empty)\n");
2343         else
2344                 list_for_each_entry (req, &ep->queue, queue) {
2345                         unsigned        length = req->req.actual;
2346
2347                         if (use_dma && buf[0]) {
2348                                 length += ((ep->bEndpointAddress & USB_DIR_IN)
2349                                                 ? dma_src_len : dma_dest_len)
2350                                         (ep, req->req.dma + length);
2351                                 buf[0] = 0;
2352                         }
2353                         seq_printf(s, "\treq %p len %d/%d buf %p\n",
2354                                         &req->req, length,
2355                                         req->req.length, req->req.buf);
2356                 }
2357 }
2358
2359 static char *trx_mode(unsigned m, int enabled)
2360 {
2361         switch (m) {
2362         case 0:         return enabled ? "*6wire" : "unused";
2363         case 1:         return "4wire";
2364         case 2:         return "3wire";
2365         case 3:         return "6wire";
2366         default:        return "unknown";
2367         }
2368 }
2369
2370 static int proc_otg_show(struct seq_file *s)
2371 {
2372         u32             tmp;
2373         u32             trans;
2374         char            *ctrl_name;
2375
2376         tmp = OTG_REV_REG;
2377         if (cpu_is_omap24xx()) {
2378                 ctrl_name = "control_devconf";
2379                 trans = CONTROL_DEVCONF_REG;
2380         } else {
2381                 ctrl_name = "tranceiver_ctrl";
2382                 trans = USB_TRANSCEIVER_CTRL_REG;
2383         }
2384         seq_printf(s, "\nOTG rev %d.%d, %s %05x\n",
2385                 tmp >> 4, tmp & 0xf, ctrl_name, trans);
2386         tmp = OTG_SYSCON_1_REG;
2387         seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2388                         FOURBITS "\n", tmp,
2389                 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2390                 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
2391                 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
2392                         ? "internal"
2393                         : trx_mode(USB0_TRX_MODE(tmp), 1),
2394                 (tmp & OTG_IDLE_EN) ? " !otg" : "",
2395                 (tmp & HST_IDLE_EN) ? " !host" : "",
2396                 (tmp & DEV_IDLE_EN) ? " !dev" : "",
2397                 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
2398         tmp = OTG_SYSCON_2_REG;
2399         seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2400                         " b_ase_brst=%d hmc=%d\n", tmp,
2401                 (tmp & OTG_EN) ? " otg_en" : "",
2402                 (tmp & USBX_SYNCHRO) ? " synchro" : "",
2403                 // much more SRP stuff
2404                 (tmp & SRP_DATA) ? " srp_data" : "",
2405                 (tmp & SRP_VBUS) ? " srp_vbus" : "",
2406                 (tmp & OTG_PADEN) ? " otg_paden" : "",
2407                 (tmp & HMC_PADEN) ? " hmc_paden" : "",
2408                 (tmp & UHOST_EN) ? " uhost_en" : "",
2409                 (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2410                 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
2411                 B_ASE_BRST(tmp),
2412                 OTG_HMC(tmp));
2413         tmp = OTG_CTRL_REG;
2414         seq_printf(s, "otg_ctrl    %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2415                 (tmp & OTG_ASESSVLD) ? " asess" : "",
2416                 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
2417                 (tmp & OTG_BSESSVLD) ? " bsess" : "",
2418                 (tmp & OTG_VBUSVLD) ? " vbus" : "",
2419                 (tmp & OTG_ID) ? " id" : "",
2420                 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2421                 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2422                 (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2423                 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2424                 (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2425                 (tmp & OTG_BUSDROP) ? " busdrop" : "",
2426                 (tmp & OTG_PULLDOWN) ? " down" : "",
2427                 (tmp & OTG_PULLUP) ? " up" : "",
2428                 (tmp & OTG_DRV_VBUS) ? " drv" : "",
2429                 (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2430                 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2431                 (tmp & OTG_PU_ID) ? " pu_id" : ""
2432                 );
2433         tmp = OTG_IRQ_EN_REG;
2434         seq_printf(s, "otg_irq_en  %04x" "\n", tmp);
2435         tmp = OTG_IRQ_SRC_REG;
2436         seq_printf(s, "otg_irq_src %04x" "\n", tmp);
2437         tmp = OTG_OUTCTRL_REG;
2438         seq_printf(s, "otg_outctrl %04x" "\n", tmp);
2439         tmp = OTG_TEST_REG;
2440         seq_printf(s, "otg_test    %04x" "\n", tmp);
2441         return 0;
2442 }
2443
2444 static int proc_udc_show(struct seq_file *s, void *_)
2445 {
2446         u32             tmp;
2447         struct omap_ep  *ep;
2448         unsigned long   flags;
2449
2450         spin_lock_irqsave(&udc->lock, flags);
2451
2452         seq_printf(s, "%s, version: " DRIVER_VERSION
2453 #ifdef  USE_ISO
2454                 " (iso)"
2455 #endif
2456                 "%s\n",
2457                 driver_desc,
2458                 use_dma ?  " (dma)" : "");
2459
2460         tmp = UDC_REV_REG & 0xff;
2461         seq_printf(s,
2462                 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2463                 "hmc %d, transceiver %s\n",
2464                 tmp >> 4, tmp & 0xf,
2465                 fifo_mode,
2466                 udc->driver ? udc->driver->driver.name : "(none)",
2467                 HMC,
2468                 udc->transceiver
2469                         ? udc->transceiver->label
2470                         : ((cpu_is_omap1710() || cpu_is_omap24xx())
2471                                 ? "external" : "(none)"));
2472         if (cpu_class_is_omap1()) {
2473                 seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2474                         __REG16(ULPD_CLOCK_CTRL),
2475                         __REG16(ULPD_SOFT_REQ),
2476                         __REG16(ULPD_STATUS_REQ));
2477         }
2478
2479         /* OTG controller registers */
2480         if (!cpu_is_omap15xx())
2481                 proc_otg_show(s);
2482
2483         tmp = UDC_SYSCON1_REG;
2484         seq_printf(s, "\nsyscon1     %04x" EIGHTBITS "\n", tmp,
2485                 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2486                 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2487                 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2488                 (tmp & UDC_NAK_EN) ? " nak" : "",
2489                 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2490                 (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2491                 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2492                 (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
2493         // syscon2 is write-only
2494
2495         /* UDC controller registers */
2496         if (!(tmp & UDC_PULLUP_EN)) {
2497                 seq_printf(s, "(suspended)\n");
2498                 spin_unlock_irqrestore(&udc->lock, flags);
2499                 return 0;
2500         }
2501
2502         tmp = UDC_DEVSTAT_REG;
2503         seq_printf(s, "devstat     %04x" EIGHTBITS "%s%s\n", tmp,
2504                 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2505                 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2506                 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2507                 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2508                 (tmp & UDC_USB_RESET) ? " usb_reset" : "",
2509                 (tmp & UDC_SUS) ? " SUS" : "",
2510                 (tmp & UDC_CFG) ? " CFG" : "",
2511                 (tmp & UDC_ADD) ? " ADD" : "",
2512                 (tmp & UDC_DEF) ? " DEF" : "",
2513                 (tmp & UDC_ATT) ? " ATT" : "");
2514         seq_printf(s, "sof         %04x\n", UDC_SOF_REG);
2515         tmp = UDC_IRQ_EN_REG;
2516         seq_printf(s, "irq_en      %04x" FOURBITS "%s\n", tmp,
2517                 (tmp & UDC_SOF_IE) ? " sof" : "",
2518                 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2519                 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2520                 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2521                 (tmp & UDC_EP0_IE) ? " ep0" : "");
2522         tmp = UDC_IRQ_SRC_REG;
2523         seq_printf(s, "irq_src     %04x" EIGHTBITS "%s%s\n", tmp,
2524                 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
2525                 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2526                 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
2527                 (tmp & UDC_SOF) ? " sof" : "",
2528                 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
2529                 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
2530                 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
2531                 (tmp & UDC_SETUP) ? " setup" : "",
2532                 (tmp & UDC_EP0_RX) ? " ep0out" : "",
2533                 (tmp & UDC_EP0_TX) ? " ep0in" : "");
2534         if (use_dma) {
2535                 unsigned i;
2536
2537                 tmp = UDC_DMA_IRQ_EN_REG;
2538                 seq_printf(s, "dma_irq_en  %04x%s" EIGHTBITS "\n", tmp,
2539                         (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2540                         (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2541                         (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2542
2543                         (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2544                         (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2545                         (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2546
2547                         (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2548                         (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2549                         (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2550
2551                 tmp = UDC_RXDMA_CFG_REG;
2552                 seq_printf(s, "rxdma_cfg   %04x\n", tmp);
2553                 if (tmp) {
2554                         for (i = 0; i < 3; i++) {
2555                                 if ((tmp & (0x0f << (i * 4))) == 0)
2556                                         continue;
2557                                 seq_printf(s, "rxdma[%d]    %04x\n", i,
2558                                                 UDC_RXDMA_REG(i + 1));
2559                         }
2560                 }
2561                 tmp = UDC_TXDMA_CFG_REG;
2562                 seq_printf(s, "txdma_cfg   %04x\n", tmp);
2563                 if (tmp) {
2564                         for (i = 0; i < 3; i++) {
2565                                 if (!(tmp & (0x0f << (i * 4))))
2566                                         continue;
2567                                 seq_printf(s, "txdma[%d]    %04x\n", i,
2568                                                 UDC_TXDMA_REG(i + 1));
2569                         }
2570                 }
2571         }
2572
2573         tmp = UDC_DEVSTAT_REG;
2574         if (tmp & UDC_ATT) {
2575                 proc_ep_show(s, &udc->ep[0]);
2576                 if (tmp & UDC_ADD) {
2577                         list_for_each_entry (ep, &udc->gadget.ep_list,
2578                                         ep.ep_list) {
2579                                 if (ep->desc)
2580                                         proc_ep_show(s, ep);
2581                         }
2582                 }
2583         }
2584         spin_unlock_irqrestore(&udc->lock, flags);
2585         return 0;
2586 }
2587
2588 static int proc_udc_open(struct inode *inode, struct file *file)
2589 {
2590         return single_open(file, proc_udc_show, NULL);
2591 }
2592
2593 static const struct file_operations proc_ops = {
2594         .open           = proc_udc_open,
2595         .read           = seq_read,
2596         .llseek         = seq_lseek,
2597         .release        = single_release,
2598 };
2599
2600 static void create_proc_file(void)
2601 {
2602         struct proc_dir_entry *pde;
2603
2604         pde = create_proc_entry (proc_filename, 0, NULL);
2605         if (pde)
2606                 pde->proc_fops = &proc_ops;
2607 }
2608
2609 static void remove_proc_file(void)
2610 {
2611         remove_proc_entry(proc_filename, NULL);
2612 }
2613
2614 #else
2615
2616 static inline void create_proc_file(void) {}
2617 static inline void remove_proc_file(void) {}
2618
2619 #endif
2620
2621 /*-------------------------------------------------------------------------*/
2622
2623 /* Before this controller can enumerate, we need to pick an endpoint
2624  * configuration, or "fifo_mode"  That involves allocating 2KB of packet
2625  * buffer space among the endpoints we'll be operating.
2626  *
2627  * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
2628  * UDC_SYSCON_1_REG.CFG_LOCK is set can now work.  We won't use that
2629  * capability yet though.
2630  */
2631 static unsigned __init
2632 omap_ep_setup(char *name, u8 addr, u8 type,
2633                 unsigned buf, unsigned maxp, int dbuf)
2634 {
2635         struct omap_ep  *ep;
2636         u16             epn_rxtx = 0;
2637
2638         /* OUT endpoints first, then IN */
2639         ep = &udc->ep[addr & 0xf];
2640         if (addr & USB_DIR_IN)
2641                 ep += 16;
2642
2643         /* in case of ep init table bugs */
2644         BUG_ON(ep->name[0]);
2645
2646         /* chip setup ... bit values are same for IN, OUT */
2647         if (type == USB_ENDPOINT_XFER_ISOC) {
2648                 switch (maxp) {
2649                 case 8:         epn_rxtx = 0 << 12; break;
2650                 case 16:        epn_rxtx = 1 << 12; break;
2651                 case 32:        epn_rxtx = 2 << 12; break;
2652                 case 64:        epn_rxtx = 3 << 12; break;
2653                 case 128:       epn_rxtx = 4 << 12; break;
2654                 case 256:       epn_rxtx = 5 << 12; break;
2655                 case 512:       epn_rxtx = 6 << 12; break;
2656                 default:        BUG();
2657                 }
2658                 epn_rxtx |= UDC_EPN_RX_ISO;
2659                 dbuf = 1;
2660         } else {
2661                 /* double-buffering "not supported" on 15xx,
2662                  * and ignored for PIO-IN on newer chips
2663                  * (for more reliable behavior)
2664                  */
2665                 if (!use_dma || cpu_is_omap15xx() || cpu_is_omap24xx())
2666                         dbuf = 0;
2667
2668                 switch (maxp) {
2669                 case 8:         epn_rxtx = 0 << 12; break;
2670                 case 16:        epn_rxtx = 1 << 12; break;
2671                 case 32:        epn_rxtx = 2 << 12; break;
2672                 case 64:        epn_rxtx = 3 << 12; break;
2673                 default:        BUG();
2674                 }
2675                 if (dbuf && addr)
2676                         epn_rxtx |= UDC_EPN_RX_DB;
2677                 init_timer(&ep->timer);
2678                 ep->timer.function = pio_out_timer;
2679                 ep->timer.data = (unsigned long) ep;
2680         }
2681         if (addr)
2682                 epn_rxtx |= UDC_EPN_RX_VALID;
2683         BUG_ON(buf & 0x07);
2684         epn_rxtx |= buf >> 3;
2685
2686         DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2687                 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2688
2689         if (addr & USB_DIR_IN)
2690                 UDC_EP_TX_REG(addr & 0xf) = epn_rxtx;
2691         else
2692                 UDC_EP_RX_REG(addr) = epn_rxtx;
2693
2694         /* next endpoint's buffer starts after this one's */
2695         buf += maxp;
2696         if (dbuf)
2697                 buf += maxp;
2698         BUG_ON(buf > 2048);
2699
2700         /* set up driver data structures */
2701         BUG_ON(strlen(name) >= sizeof ep->name);
2702         strlcpy(ep->name, name, sizeof ep->name);
2703         INIT_LIST_HEAD(&ep->queue);
2704         INIT_LIST_HEAD(&ep->iso);
2705         ep->bEndpointAddress = addr;
2706         ep->bmAttributes = type;
2707         ep->double_buf = dbuf;
2708         ep->udc = udc;
2709
2710         ep->ep.name = ep->name;
2711         ep->ep.ops = &omap_ep_ops;
2712         ep->ep.maxpacket = ep->maxpacket = maxp;
2713         list_add_tail (&ep->ep.ep_list, &udc->gadget.ep_list);
2714
2715         return buf;
2716 }
2717
2718 static void omap_udc_release(struct device *dev)
2719 {
2720         complete(udc->done);
2721         kfree (udc);
2722         udc = NULL;
2723 }
2724
2725 static int __init
2726 omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv)
2727 {
2728         unsigned        tmp, buf;
2729
2730         /* abolish any previous hardware state */
2731         UDC_SYSCON1_REG = 0;
2732         UDC_IRQ_EN_REG = 0;
2733         UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
2734         UDC_DMA_IRQ_EN_REG = 0;
2735         UDC_RXDMA_CFG_REG = 0;
2736         UDC_TXDMA_CFG_REG = 0;
2737
2738         /* UDC_PULLUP_EN gates the chip clock */
2739         // OTG_SYSCON_1_REG |= DEV_IDLE_EN;
2740
2741         udc = kzalloc(sizeof(*udc), GFP_KERNEL);
2742         if (!udc)
2743                 return -ENOMEM;
2744
2745         spin_lock_init (&udc->lock);
2746
2747         udc->gadget.ops = &omap_gadget_ops;
2748         udc->gadget.ep0 = &udc->ep[0].ep;
2749         INIT_LIST_HEAD(&udc->gadget.ep_list);
2750         INIT_LIST_HEAD(&udc->iso);
2751         udc->gadget.speed = USB_SPEED_UNKNOWN;
2752         udc->gadget.name = driver_name;
2753
2754         device_initialize(&udc->gadget.dev);
2755         strcpy (udc->gadget.dev.bus_id, "gadget");
2756         udc->gadget.dev.release = omap_udc_release;
2757         udc->gadget.dev.parent = &odev->dev;
2758         if (use_dma)
2759                 udc->gadget.dev.dma_mask = odev->dev.dma_mask;
2760
2761         udc->transceiver = xceiv;
2762
2763         /* ep0 is special; put it right after the SETUP buffer */
2764         buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2765                         8 /* after SETUP */, 64 /* maxpacket */, 0);
2766         list_del_init(&udc->ep[0].ep.ep_list);
2767
2768         /* initially disable all non-ep0 endpoints */
2769         for (tmp = 1; tmp < 15; tmp++) {
2770                 UDC_EP_RX_REG(tmp) = 0;
2771                 UDC_EP_TX_REG(tmp) = 0;
2772         }
2773
2774 #define OMAP_BULK_EP(name,addr) \
2775         buf = omap_ep_setup(name "-bulk", addr, \
2776                         USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2777 #define OMAP_INT_EP(name,addr, maxp) \
2778         buf = omap_ep_setup(name "-int", addr, \
2779                         USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2780 #define OMAP_ISO_EP(name,addr, maxp) \
2781         buf = omap_ep_setup(name "-iso", addr, \
2782                         USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2783
2784         switch (fifo_mode) {
2785         case 0:
2786                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2787                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2788                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2789                 break;
2790         case 1:
2791                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2792                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2793                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2794
2795                 OMAP_BULK_EP("ep3in",  USB_DIR_IN  | 3);
2796                 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
2797                 OMAP_INT_EP("ep10in",  USB_DIR_IN  | 10, 16);
2798
2799                 OMAP_BULK_EP("ep5in",  USB_DIR_IN  | 5);
2800                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2801                 OMAP_INT_EP("ep11in",  USB_DIR_IN  | 11, 16);
2802
2803                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2804                 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
2805                 OMAP_INT_EP("ep12in",  USB_DIR_IN  | 12, 16);
2806
2807                 OMAP_BULK_EP("ep7in",  USB_DIR_IN  | 7);
2808                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2809                 OMAP_INT_EP("ep13in",  USB_DIR_IN  | 13, 16);
2810                 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2811
2812                 OMAP_BULK_EP("ep8in",  USB_DIR_IN  | 8);
2813                 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
2814                 OMAP_INT_EP("ep14in",  USB_DIR_IN  | 14, 16);
2815                 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2816
2817                 OMAP_BULK_EP("ep15in",  USB_DIR_IN  | 15);
2818                 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
2819
2820                 break;
2821
2822 #ifdef  USE_ISO
2823         case 2:                 /* mixed iso/bulk */
2824                 OMAP_ISO_EP("ep1in",   USB_DIR_IN  | 1, 256);
2825                 OMAP_ISO_EP("ep2out",  USB_DIR_OUT | 2, 256);
2826                 OMAP_ISO_EP("ep3in",   USB_DIR_IN  | 3, 128);
2827                 OMAP_ISO_EP("ep4out",  USB_DIR_OUT | 4, 128);
2828
2829                 OMAP_INT_EP("ep5in",   USB_DIR_IN  | 5, 16);
2830
2831                 OMAP_BULK_EP("ep6in",  USB_DIR_IN  | 6);
2832                 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2833                 OMAP_INT_EP("ep8in",   USB_DIR_IN  | 8, 16);
2834                 break;
2835         case 3:                 /* mixed bulk/iso */
2836                 OMAP_BULK_EP("ep1in",  USB_DIR_IN  | 1);
2837                 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2838                 OMAP_INT_EP("ep3in",   USB_DIR_IN  | 3, 16);
2839
2840                 OMAP_BULK_EP("ep4in",  USB_DIR_IN  | 4);
2841                 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2842                 OMAP_INT_EP("ep6in",   USB_DIR_IN  | 6, 16);
2843
2844                 OMAP_ISO_EP("ep7in",   USB_DIR_IN  | 7, 256);
2845                 OMAP_ISO_EP("ep8out",  USB_DIR_OUT | 8, 256);
2846                 OMAP_INT_EP("ep9in",   USB_DIR_IN  | 9, 16);
2847                 break;
2848 #endif
2849
2850         /* add more modes as needed */
2851
2852         default:
2853                 ERR("unsupported fifo_mode #%d\n", fifo_mode);
2854                 return -ENODEV;
2855         }
2856         UDC_SYSCON1_REG = UDC_CFG_LOCK|UDC_SELF_PWR;
2857         INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2858         return 0;
2859 }
2860
2861 static int __init omap_udc_probe(struct platform_device *pdev)
2862 {
2863         int                     status = -ENODEV;
2864         int                     hmc;
2865         struct otg_transceiver  *xceiv = NULL;
2866         const char              *type = NULL;
2867         struct omap_usb_config  *config = pdev->dev.platform_data;
2868         struct clk              *dc_clk;
2869         struct clk              *hhc_clk;
2870
2871         /* NOTE:  "knows" the order of the resources! */
2872         if (!request_mem_region(pdev->resource[0].start,
2873                         pdev->resource[0].end - pdev->resource[0].start + 1,
2874                         driver_name)) {
2875                 DBG("request_mem_region failed\n");
2876                 return -EBUSY;
2877         }
2878
2879         if (cpu_is_omap16xx()) {
2880                 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2881                 hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck");
2882                 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2883                 /* can't use omap_udc_enable_clock yet */
2884                 clk_enable(dc_clk);
2885                 clk_enable(hhc_clk);
2886                 udelay(100);
2887         }
2888
2889         if (cpu_is_omap24xx()) {
2890                 dc_clk = clk_get(&pdev->dev, "usb_fck");
2891                 hhc_clk = clk_get(&pdev->dev, "usb_l4_ick");
2892                 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2893                 /* can't use omap_udc_enable_clock yet */
2894                 clk_enable(dc_clk);
2895                 clk_enable(hhc_clk);
2896                 udelay(100);
2897         }
2898
2899         INFO("OMAP UDC rev %d.%d%s\n",
2900                 UDC_REV_REG >> 4, UDC_REV_REG & 0xf,
2901                 config->otg ? ", Mini-AB" : "");
2902
2903         /* use the mode given to us by board init code */
2904         if (cpu_is_omap15xx()) {
2905                 hmc = HMC_1510;
2906                 type = "(unknown)";
2907
2908                 if (machine_without_vbus_sense()) {
2909                         /* just set up software VBUS detect, and then
2910                          * later rig it so we always report VBUS.
2911                          * FIXME without really sensing VBUS, we can't
2912                          * know when to turn PULLUP_EN on/off; and that
2913                          * means we always "need" the 48MHz clock.
2914                          */
2915                         u32 tmp = FUNC_MUX_CTRL_0_REG;
2916
2917                         FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
2918                         tmp |= VBUS_MODE_1510;
2919                         tmp &= ~VBUS_CTRL_1510;
2920                         FUNC_MUX_CTRL_0_REG = tmp;
2921                 }
2922         } else {
2923                 /* The transceiver may package some GPIO logic or handle
2924                  * loopback and/or transceiverless setup; if we find one,
2925                  * use it.  Except for OTG, we don't _need_ to talk to one;
2926                  * but not having one probably means no VBUS detection.
2927                  */
2928                 xceiv = otg_get_transceiver();
2929                 if (xceiv)
2930                         type = xceiv->label;
2931                 else if (config->otg) {
2932                         DBG("OTG requires external transceiver!\n");
2933                         goto cleanup0;
2934                 }
2935
2936                 hmc = HMC_1610;
2937
2938                 if (cpu_is_omap24xx()) {
2939                         /* this could be transceiverless in one of the
2940                          * "we don't need to know" modes.
2941                          */
2942                         type = "external";
2943                         goto known;
2944                 }
2945
2946                 switch (hmc) {
2947                 case 0:                 /* POWERUP DEFAULT == 0 */
2948                 case 4:
2949                 case 12:
2950                 case 20:
2951                         if (!cpu_is_omap1710()) {
2952                                 type = "integrated";
2953                                 break;
2954                         }
2955                         /* FALL THROUGH */
2956                 case 3:
2957                 case 11:
2958                 case 16:
2959                 case 19:
2960                 case 25:
2961                         if (!xceiv) {
2962                                 DBG("external transceiver not registered!\n");
2963                                 type = "unknown";
2964                         }
2965                         break;
2966                 case 21:                        /* internal loopback */
2967                         type = "loopback";
2968                         break;
2969                 case 14:                        /* transceiverless */
2970                         if (cpu_is_omap1710())
2971                                 goto bad_on_1710;
2972                         /* FALL THROUGH */
2973                 case 13:
2974                 case 15:
2975                         type = "no";
2976                         break;
2977
2978                 default:
2979 bad_on_1710:
2980                         ERR("unrecognized UDC HMC mode %d\n", hmc);
2981                         goto cleanup0;
2982                 }
2983         }
2984 known:
2985         INFO("hmc mode %d, %s transceiver\n", hmc, type);
2986
2987         /* a "gadget" abstracts/virtualizes the controller */
2988         status = omap_udc_setup(pdev, xceiv);
2989         if (status) {
2990                 goto cleanup0;
2991         }
2992         xceiv = NULL;
2993         // "udc" is now valid
2994         pullup_disable(udc);
2995 #if     defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2996         udc->gadget.is_otg = (config->otg != 0);
2997 #endif
2998
2999         /* starting with omap1710 es2.0, clear toggle is a separate bit */
3000         if (UDC_REV_REG >= 0x61)
3001                 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
3002         else
3003                 udc->clr_halt = UDC_RESET_EP;
3004
3005         /* USB general purpose IRQ:  ep0, state changes, dma, etc */
3006         status = request_irq(pdev->resource[1].start, omap_udc_irq,
3007                         IRQF_SAMPLE_RANDOM, driver_name, udc);
3008         if (status != 0) {
3009                 ERR("can't get irq %d, err %d\n",
3010                         (int) pdev->resource[1].start, status);
3011                 goto cleanup1;
3012         }
3013
3014         /* USB "non-iso" IRQ (PIO for all but ep0) */
3015         status = request_irq(pdev->resource[2].start, omap_udc_pio_irq,
3016                         IRQF_SAMPLE_RANDOM, "omap_udc pio", udc);
3017         if (status != 0) {
3018                 ERR("can't get irq %d, err %d\n",
3019                         (int) pdev->resource[2].start, status);
3020                 goto cleanup2;
3021         }
3022 #ifdef  USE_ISO
3023         status = request_irq(pdev->resource[3].start, omap_udc_iso_irq,
3024                         IRQF_DISABLED, "omap_udc iso", udc);
3025         if (status != 0) {
3026                 ERR("can't get irq %d, err %d\n",
3027                         (int) pdev->resource[3].start, status);
3028                 goto cleanup3;
3029         }
3030 #endif
3031         if (cpu_is_omap16xx()) {
3032                 udc->dc_clk = dc_clk;
3033                 udc->hhc_clk = hhc_clk;
3034                 clk_disable(hhc_clk);
3035                 clk_disable(dc_clk);
3036         }
3037
3038         if (cpu_is_omap24xx()) {
3039                 udc->dc_clk = dc_clk;
3040                 udc->hhc_clk = hhc_clk;
3041                 /* FIXME OMAP2 don't release hhc & dc clock */
3042 #if 0
3043                 clk_disable(hhc_clk);
3044                 clk_disable(dc_clk);
3045 #endif
3046         }
3047
3048         create_proc_file();
3049         status = device_add(&udc->gadget.dev);
3050         if (!status)
3051                 return status;
3052         /* If fail, fall through */
3053 #ifdef  USE_ISO
3054 cleanup3:
3055         free_irq(pdev->resource[2].start, udc);
3056 #endif
3057
3058 cleanup2:
3059         free_irq(pdev->resource[1].start, udc);
3060
3061 cleanup1:
3062         kfree (udc);
3063         udc = NULL;
3064
3065 cleanup0:
3066         if (xceiv)
3067                 put_device(xceiv->dev);
3068
3069         if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
3070                 clk_disable(hhc_clk);
3071                 clk_disable(dc_clk);
3072                 clk_put(hhc_clk);
3073                 clk_put(dc_clk);
3074         }
3075
3076         release_mem_region(pdev->resource[0].start,
3077                         pdev->resource[0].end - pdev->resource[0].start + 1);
3078
3079         return status;
3080 }
3081
3082 static int __exit omap_udc_remove(struct platform_device *pdev)
3083 {
3084         DECLARE_COMPLETION_ONSTACK(done);
3085
3086         if (!udc)
3087                 return -ENODEV;
3088         if (udc->driver)
3089                 return -EBUSY;
3090
3091         udc->done = &done;
3092
3093         pullup_disable(udc);
3094         if (udc->transceiver) {
3095                 put_device(udc->transceiver->dev);
3096                 udc->transceiver = NULL;
3097         }
3098         UDC_SYSCON1_REG = 0;
3099
3100         remove_proc_file();
3101
3102 #ifdef  USE_ISO
3103         free_irq(pdev->resource[3].start, udc);
3104 #endif
3105         free_irq(pdev->resource[2].start, udc);
3106         free_irq(pdev->resource[1].start, udc);
3107
3108         if (udc->dc_clk) {
3109                 if (udc->clk_requested)
3110                         omap_udc_enable_clock(0);
3111                 clk_put(udc->hhc_clk);
3112                 clk_put(udc->dc_clk);
3113         }
3114
3115         release_mem_region(pdev->resource[0].start,
3116                         pdev->resource[0].end - pdev->resource[0].start + 1);
3117
3118         device_unregister(&udc->gadget.dev);
3119         wait_for_completion(&done);
3120
3121         return 0;
3122 }
3123
3124 /* suspend/resume/wakeup from sysfs (echo > power/state) or when the
3125  * system is forced into deep sleep
3126  *
3127  * REVISIT we should probably reject suspend requests when there's a host
3128  * session active, rather than disconnecting, at least on boards that can
3129  * report VBUS irqs (UDC_DEVSTAT_REG.UDC_ATT).  And in any case, we need to
3130  * make host resumes and VBUS detection trigger OMAP wakeup events; that
3131  * may involve talking to an external transceiver (e.g. isp1301).
3132  */
3133
3134 static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
3135 {
3136         u32     devstat;
3137
3138         devstat = UDC_DEVSTAT_REG;
3139
3140         /* we're requesting 48 MHz clock if the pullup is enabled
3141          * (== we're attached to the host) and we're not suspended,
3142          * which would prevent entry to deep sleep...
3143          */
3144         if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
3145                 WARN("session active; suspend requires disconnect\n");
3146                 omap_pullup(&udc->gadget, 0);
3147         }
3148
3149         udc->gadget.dev.power.power_state = PMSG_SUSPEND;
3150         udc->gadget.dev.parent->power.power_state = PMSG_SUSPEND;
3151         return 0;
3152 }
3153
3154 static int omap_udc_resume(struct platform_device *dev)
3155 {
3156         DBG("resume + wakeup/SRP\n");
3157         omap_pullup(&udc->gadget, 1);
3158
3159         /* maybe the host would enumerate us if we nudged it */
3160         msleep(100);
3161         return omap_wakeup(&udc->gadget);
3162 }
3163
3164 /*-------------------------------------------------------------------------*/
3165
3166 static struct platform_driver udc_driver = {
3167         .probe          = omap_udc_probe,
3168         .remove         = __exit_p(omap_udc_remove),
3169         .suspend        = omap_udc_suspend,
3170         .resume         = omap_udc_resume,
3171         .driver         = {
3172                 .owner  = THIS_MODULE,
3173                 .name   = (char *) driver_name,
3174         },
3175 };
3176
3177 static int __init udc_init(void)
3178 {
3179         INFO("%s, version: " DRIVER_VERSION
3180 #ifdef  USE_ISO
3181                 " (iso)"
3182 #endif
3183                 "%s\n", driver_desc,
3184                 use_dma ?  " (dma)" : "");
3185         return platform_driver_register(&udc_driver);
3186 }
3187 module_init(udc_init);
3188
3189 static void __exit udc_exit(void)
3190 {
3191         platform_driver_unregister(&udc_driver);
3192 }
3193 module_exit(udc_exit);
3194
3195 MODULE_DESCRIPTION(DRIVER_DESC);
3196 MODULE_LICENSE("GPL");
3197